JPS58111450A - デ−タの標本化速度変換回路 - Google Patents
デ−タの標本化速度変換回路Info
- Publication number
- JPS58111450A JPS58111450A JP20798381A JP20798381A JPS58111450A JP S58111450 A JPS58111450 A JP S58111450A JP 20798381 A JP20798381 A JP 20798381A JP 20798381 A JP20798381 A JP 20798381A JP S58111450 A JPS58111450 A JP S58111450A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- input
- conversion circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
Landscapes
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20798381A JPS58111450A (ja) | 1981-12-24 | 1981-12-24 | デ−タの標本化速度変換回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20798381A JPS58111450A (ja) | 1981-12-24 | 1981-12-24 | デ−タの標本化速度変換回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58111450A true JPS58111450A (ja) | 1983-07-02 |
| JPH0117618B2 JPH0117618B2 (enExample) | 1989-03-31 |
Family
ID=16548731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20798381A Granted JPS58111450A (ja) | 1981-12-24 | 1981-12-24 | デ−タの標本化速度変換回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58111450A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60253311A (ja) * | 1984-05-30 | 1985-12-14 | Hitachi Ltd | デイジタルフイルタ |
| US5020053A (en) * | 1989-04-17 | 1991-05-28 | Fujitsu Limited | Channel access system |
-
1981
- 1981-12-24 JP JP20798381A patent/JPS58111450A/ja active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60253311A (ja) * | 1984-05-30 | 1985-12-14 | Hitachi Ltd | デイジタルフイルタ |
| US5020053A (en) * | 1989-04-17 | 1991-05-28 | Fujitsu Limited | Channel access system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0117618B2 (enExample) | 1989-03-31 |
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