JPS58106942U - ワイヤボンデイング用回路基板 - Google Patents

ワイヤボンデイング用回路基板

Info

Publication number
JPS58106942U
JPS58106942U JP1982003169U JP316982U JPS58106942U JP S58106942 U JPS58106942 U JP S58106942U JP 1982003169 U JP1982003169 U JP 1982003169U JP 316982 U JP316982 U JP 316982U JP S58106942 U JPS58106942 U JP S58106942U
Authority
JP
Japan
Prior art keywords
circuit board
wire bonding
integrated circuit
wire
iyanibon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982003169U
Other languages
English (en)
Inventor
有 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1982003169U priority Critical patent/JPS58106942U/ja
Publication of JPS58106942U publication Critical patent/JPS58106942U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
一第１図は、従来のワイヤーボンデイング用回路碁板に
ＩＣを搭載した概観即、第２図は、従来の７壽ヤー承ン
デイング用一基板にＩＣを搭載した概観図。第３図は本
考案のワイヤーボンデイング用回路基板』こＩＣを搭載
した竺観図である。 １はＩＣ，２は導電性を有する接着剤文は導電性を有さ
ない接着剤〜３１一回蕗基板ζ４は回路基板上に配線さ
れたワイヤーボンデイング用パターン、５は一路基板上
！こ配線されたアース用パター、・−６は接竺剤流れ止
めの溝である。

Claims (1)

    【実用新案登録請求の範囲】
  1. 集積回路（以下ＩＣとい゛う）を搭職し、ワイｙ一ボン
    デイングを行なう回路基板に於で、該集積回路の外周に
    相当する部分に、溝を設けたことを特徴と７′ｔる？イ
    ヤニボンでイング用回路基板。１、
JP1982003169U 1982-01-13 1982-01-13 ワイヤボンデイング用回路基板 Pending JPS58106942U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982003169U JPS58106942U (ja) 1982-01-13 1982-01-13 ワイヤボンデイング用回路基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982003169U JPS58106942U (ja) 1982-01-13 1982-01-13 ワイヤボンデイング用回路基板

Publications (1)

Publication Number Publication Date
JPS58106942U true JPS58106942U (ja) 1983-07-21

Family

ID=30016117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982003169U Pending JPS58106942U (ja) 1982-01-13 1982-01-13 ワイヤボンデイング用回路基板

Country Status (1)

Country Link
JP (1) JPS58106942U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293557A (ja) * 1988-05-20 1989-11-27 Mitsubishi Electric Corp 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339869A (en) * 1976-09-24 1978-04-12 Sharp Corp Semiconductor chip mounting base plate
JPS5533077A (en) * 1978-08-30 1980-03-08 Nec Corp Hybrid integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339869A (en) * 1976-09-24 1978-04-12 Sharp Corp Semiconductor chip mounting base plate
JPS5533077A (en) * 1978-08-30 1980-03-08 Nec Corp Hybrid integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293557A (ja) * 1988-05-20 1989-11-27 Mitsubishi Electric Corp 半導体装置

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