JPS5339869A - Semiconductor chip mounting base plate - Google Patents
Semiconductor chip mounting base plateInfo
- Publication number
- JPS5339869A JPS5339869A JP11521576A JP11521576A JPS5339869A JP S5339869 A JPS5339869 A JP S5339869A JP 11521576 A JP11521576 A JP 11521576A JP 11521576 A JP11521576 A JP 11521576A JP S5339869 A JPS5339869 A JP S5339869A
- Authority
- JP
- Japan
- Prior art keywords
- chip mounting
- base plate
- semiconductor chip
- mounting base
- effluence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
PURPOSE: To improve working efficiency by providing a dam around a chip mounting portion through thick film printing thereby preventing the effluence of bonding agent or sealing resin.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11521576A JPS5339869A (en) | 1976-09-24 | 1976-09-24 | Semiconductor chip mounting base plate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11521576A JPS5339869A (en) | 1976-09-24 | 1976-09-24 | Semiconductor chip mounting base plate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5339869A true JPS5339869A (en) | 1978-04-12 |
Family
ID=14657205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11521576A Pending JPS5339869A (en) | 1976-09-24 | 1976-09-24 | Semiconductor chip mounting base plate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5339869A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58106942U (en) * | 1982-01-13 | 1983-07-21 | セイコーエプソン株式会社 | Circuit board for wire bonding |
JPS59136496A (en) * | 1983-01-25 | 1984-08-06 | Seiko Instr & Electronics Ltd | Dial plate for wristwatch |
-
1976
- 1976-09-24 JP JP11521576A patent/JPS5339869A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58106942U (en) * | 1982-01-13 | 1983-07-21 | セイコーエプソン株式会社 | Circuit board for wire bonding |
JPS59136496A (en) * | 1983-01-25 | 1984-08-06 | Seiko Instr & Electronics Ltd | Dial plate for wristwatch |
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