JPS58103222A - フリツプフロツプ回路 - Google Patents

フリツプフロツプ回路

Info

Publication number
JPS58103222A
JPS58103222A JP56202139A JP20213981A JPS58103222A JP S58103222 A JPS58103222 A JP S58103222A JP 56202139 A JP56202139 A JP 56202139A JP 20213981 A JP20213981 A JP 20213981A JP S58103222 A JPS58103222 A JP S58103222A
Authority
JP
Japan
Prior art keywords
circuit
delayed
flip
output
spike
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56202139A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0157848B2 (enrdf_load_stackoverflow
Inventor
Tomoaki Isozaki
磯崎 智明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56202139A priority Critical patent/JPS58103222A/ja
Publication of JPS58103222A publication Critical patent/JPS58103222A/ja
Publication of JPH0157848B2 publication Critical patent/JPH0157848B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
JP56202139A 1981-12-15 1981-12-15 フリツプフロツプ回路 Granted JPS58103222A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56202139A JPS58103222A (ja) 1981-12-15 1981-12-15 フリツプフロツプ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56202139A JPS58103222A (ja) 1981-12-15 1981-12-15 フリツプフロツプ回路

Publications (2)

Publication Number Publication Date
JPS58103222A true JPS58103222A (ja) 1983-06-20
JPH0157848B2 JPH0157848B2 (enrdf_load_stackoverflow) 1989-12-07

Family

ID=16452600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56202139A Granted JPS58103222A (ja) 1981-12-15 1981-12-15 フリツプフロツプ回路

Country Status (1)

Country Link
JP (1) JPS58103222A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2628878A1 (fr) * 1988-03-18 1989-09-22 Radiotechnique Compelec Cellule de memorisation adressable, registre a decalage et memoire comportant de telles cellules

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553234A (en) * 1978-06-22 1980-01-11 Toshiba Corp Self-supporting cmos latch circuit
JPS55100734A (en) * 1979-01-26 1980-07-31 Hitachi Ltd Output buffer circuit with latch function

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553234A (en) * 1978-06-22 1980-01-11 Toshiba Corp Self-supporting cmos latch circuit
JPS55100734A (en) * 1979-01-26 1980-07-31 Hitachi Ltd Output buffer circuit with latch function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2628878A1 (fr) * 1988-03-18 1989-09-22 Radiotechnique Compelec Cellule de memorisation adressable, registre a decalage et memoire comportant de telles cellules

Also Published As

Publication number Publication date
JPH0157848B2 (enrdf_load_stackoverflow) 1989-12-07

Similar Documents

Publication Publication Date Title
JP2621993B2 (ja) フリップフロップ回路
JPS61191114A (ja) パルス発生回路
US3971960A (en) Flip-flop false output rejection circuit
US6456115B2 (en) Clock gate buffering circuit
US5111066A (en) Clock frequency doubler
JPS6365711A (ja) 半導体集積論理回路
JPH0199314A (ja) シンクロナイザ‐フリツプフロツプ回路装置
JPS61101113A (ja) フリツプフロツプ回路
JP2870629B2 (ja) 論理回路
JPS58103222A (ja) フリツプフロツプ回路
US6509772B1 (en) Flip-flop circuit with transmission-gate sampling
KR890001104A (ko) 반도체집적회로
JP2541244B2 (ja) クロック発生回路
JPS6187299A (ja) デジタル信号の中間メモリ回路
JPH05102312A (ja) 半導体集積回路
JP3130592B2 (ja) 二相クロック発生回路
JP3133089B2 (ja) 書込み応答回路
US5270580A (en) Pulse generator circuit for producing simultaneous complementary output pulses
JP2570575B2 (ja) フリップフロップ回路
JPH07202131A (ja) 半導体集積回路
KR930010940B1 (ko) 입력인지 회로
JPH0254690B2 (enrdf_load_stackoverflow)
JPS6229929B2 (enrdf_load_stackoverflow)
JPH01164119A (ja) レベル変換入力回路
JPS62194726A (ja) Cmos半導体装置から成るバイナリフリツプフロツプ