JPS5794826A - Control system of input/output device for information processing system - Google Patents

Control system of input/output device for information processing system

Info

Publication number
JPS5794826A
JPS5794826A JP17095280A JP17095280A JPS5794826A JP S5794826 A JPS5794826 A JP S5794826A JP 17095280 A JP17095280 A JP 17095280A JP 17095280 A JP17095280 A JP 17095280A JP S5794826 A JPS5794826 A JP S5794826A
Authority
JP
Japan
Prior art keywords
input
output device
output
information processing
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17095280A
Other languages
Japanese (ja)
Inventor
Takashi Kano
Tadashi Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17095280A priority Critical patent/JPS5794826A/en
Publication of JPS5794826A publication Critical patent/JPS5794826A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To prevent the delay of scanning in case access is given to an input/ output device from a CPU, by setting the speed of response of an input/output module in the input/output device at the maximum level of the capacity of each module. CONSTITUTION:An input buffer memory 3 and an output buffer memory 4 are provided between a CPU1 and an input/output device 2. The data is transferred between the CPU1 and the device 2 via these buffer memories 3 and 4. In this connection, a scanner 5, a multiplexer 6, an input/output module 7 and an output module 8 are connected to bus lines 9 and 10 at the side of the CPU1 as well as to bus lines 11-13 at the side of the device 2, respectively.
JP17095280A 1980-12-05 1980-12-05 Control system of input/output device for information processing system Pending JPS5794826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17095280A JPS5794826A (en) 1980-12-05 1980-12-05 Control system of input/output device for information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17095280A JPS5794826A (en) 1980-12-05 1980-12-05 Control system of input/output device for information processing system

Publications (1)

Publication Number Publication Date
JPS5794826A true JPS5794826A (en) 1982-06-12

Family

ID=15914416

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17095280A Pending JPS5794826A (en) 1980-12-05 1980-12-05 Control system of input/output device for information processing system

Country Status (1)

Country Link
JP (1) JPS5794826A (en)

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