JPS5723159A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5723159A
JPS5723159A JP9854880A JP9854880A JPS5723159A JP S5723159 A JPS5723159 A JP S5723159A JP 9854880 A JP9854880 A JP 9854880A JP 9854880 A JP9854880 A JP 9854880A JP S5723159 A JPS5723159 A JP S5723159A
Authority
JP
Japan
Prior art keywords
output
data processing
priority
request
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9854880A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9854880A priority Critical patent/JPS5723159A/en
Publication of JPS5723159A publication Critical patent/JPS5723159A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To speed up data processing efficiently by determining the priority of the acquisition of an interleaving bus at a high speed. CONSTITUTION:An FF45 sets in response to the fall of the output of an AND gate 44, and subsequently the Q output also changes. The Q output of the FF45 outputted as a request signal L for the exclusive use of an interleaving bus 24 to a priority deciding circuit 33 via an OR gate 46. Consequently, the priority deciding circuit 31 indicates that the request for the exclusive use of the interleaving bus 24 for access to a memory bank 22 is sent. In addition, it is evident from the set state of an FF41 that the access request from a CPU25 to the memory bank 22 is accepted.
JP9854880A 1980-07-18 1980-07-18 Data processing system Pending JPS5723159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9854880A JPS5723159A (en) 1980-07-18 1980-07-18 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9854880A JPS5723159A (en) 1980-07-18 1980-07-18 Data processing system

Publications (1)

Publication Number Publication Date
JPS5723159A true JPS5723159A (en) 1982-02-06

Family

ID=14222734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9854880A Pending JPS5723159A (en) 1980-07-18 1980-07-18 Data processing system

Country Status (1)

Country Link
JP (1) JPS5723159A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01144594U (en) * 1988-03-29 1989-10-04

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01144594U (en) * 1988-03-29 1989-10-04

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