JPS56143036A - Response synchronizing system - Google Patents
Response synchronizing systemInfo
- Publication number
- JPS56143036A JPS56143036A JP4664380A JP4664380A JPS56143036A JP S56143036 A JPS56143036 A JP S56143036A JP 4664380 A JP4664380 A JP 4664380A JP 4664380 A JP4664380 A JP 4664380A JP S56143036 A JPS56143036 A JP S56143036A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- timing
- response
- coincidence
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To achieve desired transfer speed without delaying the requested cycle time, by operating the values of 2nd timing and present timing stored at the data response processing and returning the response signal to the request device. CONSTITUTION:When the response controlling circuit 6 receives the response signal 13 from the memory controlling device 100, synchronism is taken, and the output signal 20 consisting of the 2nd timing signal 19 read out from the storage circuit 4, and the request reception signal 17, is compared with the present 2nd timing signal 19. If the result of comparison is in coincidence and it is in coincidence with the 1st timing 14, the response signal 16 is produced to the data request device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4664380A JPS6022778B2 (en) | 1980-04-09 | 1980-04-09 | Response synchronization method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4664380A JPS6022778B2 (en) | 1980-04-09 | 1980-04-09 | Response synchronization method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56143036A true JPS56143036A (en) | 1981-11-07 |
JPS6022778B2 JPS6022778B2 (en) | 1985-06-04 |
Family
ID=12752984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4664380A Expired JPS6022778B2 (en) | 1980-04-09 | 1980-04-09 | Response synchronization method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6022778B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0346779A (en) * | 1989-07-12 | 1991-02-28 | Fujitsu Ltd | Ic socket |
JPH07161425A (en) * | 1993-12-02 | 1995-06-23 | Nec Corp | Package accommodation socket |
-
1980
- 1980-04-09 JP JP4664380A patent/JPS6022778B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6022778B2 (en) | 1985-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5464941A (en) | Weight generator circuit | |
JPS5797133A (en) | Control system of data transfer | |
JPS57182257A (en) | Data interchange system of data processing system | |
JPS56143036A (en) | Response synchronizing system | |
JPS5399142A (en) | Ignition control system | |
JPS53145536A (en) | Interruption process system | |
JPS5415620A (en) | Buffer memory unit | |
JPS53126828A (en) | Storage control unit | |
JPS5525176A (en) | Memory unit control system | |
JPS5733472A (en) | Memory access control system | |
JPS5356936A (en) | Transfer control system | |
JPS5247330A (en) | Storage control system | |
JPS5487140A (en) | Data transfer control system | |
JPS5329480A (en) | Program controller | |
JPS53121513A (en) | Signal transfer system | |
JPS573155A (en) | Input and output control circuit for memory device | |
JPS52120731A (en) | Refresh control circuit | |
JPS55118168A (en) | Memory reading control system | |
JPS52106242A (en) | Character multiple communication system | |
JPS53132227A (en) | Output unit for video data | |
JPS5654696A (en) | Memory device | |
JPS5335439A (en) | Store control system | |
JPS56119992A (en) | Dynamic type fixed memory device | |
JPS5658185A (en) | Buffer memory control device | |
JPS5416941A (en) | Read control system for memory unit |