JPS5784163A - Inspecting method for complementary mos integrated circuit - Google Patents

Abstract

PURPOSE:To contrive to make failures being produced due to deterioration during operation positively detectable without performing a life test. CONSTITUTION:A CMOS integrated circuit 2 which is a reference for comparison with a CMOS integrated circuit 1 to be tested is supplied with a source voltage from a power source device 3, and an input signal is applied on it from an input signal generating circuit 4. The input signal is synchronized with a clock signal from a clock signal generating circuit 7 and is pulse which is kept to be ''1'' until the next clock signal is applied, the power source voltage is a voltage generated by a pulse voltage which is kept to be ''1'' for a short duration from the moment at which the clock signal is initiated to be superposed on a D.C. voltage, and by these signals being applied, when the CMOS integrated circuit 1 to be tested has developed a fault, a different output from an output of an integrated circuit 2 to be used as a reference is outputted, which is detected at a comparing detector circuit 5, and a judgement if it is defective or not is performed.