JPH07280880A - Stationary power supply current tester for ic - Google Patents

Abstract

PURPOSE:To detect abnormality in the stationary power supply current for an IC to be tested while generating a test pattern at a normal rate. CONSTITUTION:The power supply current tester comprises a timing generator 48 generating an operation signal being fed to an IC to be tested, a mask signal for a power supply current measuring circuit, and a signal for starting a sample clock generator 41, a clock generator 40 generating a clock synchronized with the timing generator 48, a burst counter 42 for setting the number of sample clocks, and a sample clock generator 41 generating sample clocks when the sample clock operation is started until the operation is stopped by a burst counter 40. An analog current value obtained from a current detection output is converted through a waveform digitizer 43 into a digital value for every sample clock and stored in a memory 44. A digital signal processor 45 then calculates a stationary current value according to the lowering curve of power supply current stored in the memory 44.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault which is difficult to find by observing a signal output end, such as a short circuit fault of a CMOS circuit.
Detects at high speed due to an abnormality in the current flowing through the IC power supply,
The present invention relates to a static power supply current test device for an IC.

[0002]

2. Description of the Related Art An IC quiescent power supply current test device is a device for detecting a failure by measuring the power supply current of an IC under test while the circuit is not operating. Especially C
In the case of a MOS circuit, the power supply current when the circuit is not operating is very small, so observing an abnormal current value at rest is an effective method for improving the failure detection rate. For example, as an example, in an IC in which almost no power supply current flows when stationary during normal operation, if an abnormal current occurs due to a short-circuit with the power supply, a failure can be detected by measuring the power supply current during stationary. Further, if a test pattern having a large current difference between a normal state and an abnormal state at rest can be obtained by an appropriate input test pattern, a failure such as a dynamic open or short circuit can be detected.

FIG. 3 shows a circuit block diagram for measuring the power supply current of the IC under test 10 and a current detection output waveform diagram. The output of the power supply driver 20 has an output impedance low enough to drive the IC under test 10. Power driver 2
A resistor R is connected in series between 0 and the IC under test 10, and a voltage change caused by the resistor R with respect to the power supply voltage of the output voltage of the power supply driver 20 represents a change in current. The amplifier 30 amplifies the difference between the output of the power supply driver 20 and the power supply voltage, and outputs a current detection value. The resistor R includes a diode D1 and a diode D so that the output voltage of the power supply driver 20 is not saturated due to an abnormality in the IC under test.
2 are connected in parallel. Further, in order to further reduce the change in the output voltage of the power supply driver 20, the analog switch SW that operates by the mask signal is connected in parallel to the resistor R.
The capacitor C is for reducing the impedance of the power supply line when the IC under test 10 operates, and is attached in the vicinity of the IC under test 10.

[0004]

As described above,
A method of detecting an abnormality by measuring a current at rest in the power source of the IC is useful. However, in the conventional circuit, I
After the operation of C, it takes several tens of μs until the current value at rest becomes stable, and the interval between test patterns must be reduced to about several tens of μs, which increases the test time. Further, since the test patterns have a large interval, there is a drawback that a failure that occurs only at a normal speed cannot be found. An object of the present invention is to detect a power supply current abnormality when the IC under test is stationary, while generating the test pattern at a normal speed without slowing it down.

[0005]

A timing generator is provided for generating an operation signal supplied to an IC under test, a mask signal for a power supply current measuring circuit, and a sample clock start signal for starting a sample clock generator. A clock generator that generates a clock synchronized with the timing generator is provided. A burst counter that sets the number of sample clocks that start counting with a sample clock start signal is provided, and a sample clock generator that generates a sample clock from the start of the sample clock to the stop of the burst counter is provided.
The analog current value obtained from the current detection output is converted to digital by the waveform digitizer for each sample clock, the converted current value for each sample clock is stored in the memory, and from the falling curve of the power supply current stored in the memory ,
A digital signal processing device calculates the current value at rest.

[0006]

By the means described above, the target IC to be tested can be stopped by the current value at rest obtained by calculation from the downward curve of the current without waiting for several tens of microseconds for the current value at rest to stabilize. It is possible to detect abnormal power supply current.

[0007]

1 is a circuit block diagram of the present invention, and FIG. 2 is a timing diagram thereof. As shown in FIG.
When is operated, a pulsed current flows to the power supply at the same time as the operation. At this time, in order to prevent saturation of the current detection circuit, a mask signal is output and the voltage of the current detection output is limited.
When the power supply current value drops, the mask signal is released and a plurality of sample clocks are output. This sample clock gives the falling curve of the power supply current. The current at rest is calculated from the curve.

FIG. 1 is a circuit block for realizing the above procedure. The timing generator 46 is an IC to be tested.
To generate a mask signal for the power supply current measuring circuit and a sample clock start signal for starting the sample clock generator 41,
It is also synchronized with the clock of the clock generator 40. When the mask signal ends, the sample clock generator 41 is started and the number of sample clocks set in the burst counter 42 is generated. The sample clock is input to the waveform digitizer 43, and the falling curve of the power supply current, which is an analog value, is converted into a digital value at each sampling time. The current value converted into a digital value is stored in the memory 44, and the digital signal processing device 45 calculates the current at rest by calculation.

[0009]

Since the present invention is constructed as described above, it is not necessary to increase the interval between test patterns, and the quiescent power supply current of the IC can be observed at a normal speed.
Therefore, the test time is shortened, and the failure that occurs only at the normal speed can be found, which is effective.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of the present invention.

FIG. 2 is a timing diagram of the present invention.

FIG. 3 is a block diagram of a power supply current detection circuit.

[Explanation of symbols]

 10 IC under Test 20 Power Supply Driver 30 Amplifier 40 Clock Generator 41 Sample Clock Generator 42 Burst Counter 43 Waveform Digitizer 44 Memory 45 Digital Signal Processor 46 Timing Generator

Claims (1)

[Claims] 1. An operation signal applied to an IC under test (10),
Timing generator (4) for generating a mask signal of the power supply current measuring circuit and for generating a sample clock start signal for starting the sample clock generator (41)
6), a clock generator (40) that generates a clock synchronized with the timing generator (46), and a burst counter (4) that sets the number of sample clocks that start counting with the sample clock start signal.
2), a sample clock generator (41) that generates a sample clock from the start of the sample clock until it stops at the burst counter, and a waveform digitizer (41) that converts the analog current value obtained from the current detection output to digital for each sample clock. Four
3), a memory (44) that stores a digitally converted current value for each sample clock, a digital signal processing device (45) that calculates a current value at rest from a falling curve of the power supply current, and the above A static power supply current test device for an IC, comprising: