SU748422A1 - Integrated circuit testing device - Google Patents

Description

(54) DEVICE FOR INTEGRAL CHART CONTROL 1 I. The invention relates to the field of computing and can be applied to control integrated circuits (ies). A device for controlling integrated circuits 1 is known, which provides control of the integrated circuit (s) with checking the presence of contact of probes-probes and integrated circuit during control on the plates. The disadvantage of such a device is the inability to check the presence of the closure of two adjacent probes and the lack of automatic control of the thresholds of amplitude discriminators, with the help of which the integrated circuits are examined. It is also known a device for trolling integrated circuits 2, which monitors the closure of two adjacent terminals of the IC or probe probe during the control on the plates, but the device must be applied to a voltage opposite to the polarity of the power supply of the integrated circuit, which leads to application of electromagnetic relays and increases the capacity of the measuring circuit. The disadvantage of this device is the lack of automatic self-checking of measuring circuits. The closest to the technical essence of this invention is a control device containing two electronic keys, two triggers, a multichannel amplitude discriminator, an OR element, two AND elements, a control unit. A disadvantage of this device is the inability to control the thresholds of amplitude discriminators and check the closure of two adjacent probes, which does not provide sufficient reliability of the control. The aim of the invention is to increase the reliability of control of integrated circuits. The goal is achieved in that the device for controlling integrated circuits containing serially connected multichannel amplitude discriminator, the first OR element, the control unit and the clock pulse generator, the second output of the control unit being connected to the inputs of the memory unit and the programmable power source, a block of keys and a sequentially sequenced circular shift register and a block of second OR elements, whose outputs are connected to the master inputs of a multichannel amplitude discriminator, and the second inputs to the outputs of the memory block, the outputs of the key block are connected to the measuring inputs of the multichannel amplitude discriminator, the setting inputs to the output of the programmable power source, the first control inputs to the outputs of the ring shift register, and the second control inputs to the second the output of the control unit and with the input of the recording of the annular shift register connected by the clock input with the output of the generator of takt pulses, and the output of the high-order bit with the second input of the control unit. The drawing shows a block diagram of the device. The drawing shows integrated circuit 1, multichannel amplitude discriminator 2, first element OR 3, programmable power source 4, control unit 5, memory block 6, clock pulse generator 7, shift register 8, key block 9 and block of second elements OR 10 The device operates in four modes. The first mode is the search for possible closures of probe probes during control on the plates. The second mode is the e-mail of the integrated circuit, the third mode is the control for clocking, and the fourth is the verification of the thresholds of the multichannel amplitude discriminator. When searching for possible closures of probes, JC 1 is not connected and the device operates as follows. The control unit 5 writes a unit 8 into the 5th bit of the register, and the remaining ones - zeros. At the same time, the input of block 9 is given an enable signal from the control unit 5. On the other inputs of block 9, only one will have an enable signal, the others will be banned. The high potential of only one input through the discriminator 2 enters through the master input block 9 from the source 1 4, if it is not shorted to the adjacent probe. In this case, in the same channel of the discriminator 2, pos 1, the waiting signal is dropped by the unit from the output of register 8 through block 10. At the output of the discriminator 2, there is no reject signal. In the case of shorter two probes (even not adjacent ones) or more with this probe, at the output of the discriminator 2, a fault occurs at the output of those channels whose probes are closed with the selected probe, whose number is fixed

Claims (3)

748422 by the register 8. Block 5 receives a signal from the output of the element OR 3. The operator corrects the shortening and re-starts this mode. From oscillator 7, the signal will be fed to the input of register 8, in which the velocity will move from the first bit to the second. This will check for the closure of the second probe with the remaining probes, and so on until the last probe. Transferring a unit from the high register to 8 c. the first one fixes the end of the first mode and the absence of closures between the probes. When monitoring the operation, the control unit 5 writes into the shift register 8 zeroes in all bits, the source 4 is disconnected from the measuring circuits. The expected combinations come from the memory block 6 through the block 10 to the driver input of the discriminator 2. The outputs of the IC 1 through the key block 9 are connected to the inputs of the discriminator 2. The functional control of the IC is performed as follows. The output from the IC 1 goes to the discriminator 2, where it is compared with the expected combinations coming from block 10. The signal of noncomparability, if it occurs, from the output of discriminator 2 through the element OR 3 goes to the input of block 5, fixing the defect on this IC. In monitoring the contacting of the probes to the contact pads of IC 1, a register from block 5 is recorded in register 8 corresponding to the substrate of IC 1. In this case, the voltage from block 4 comes from source 4 through block 9. If the probes are not contacted by all the probes, then on the outputs of the discriminator 2, according to the Vits, a non-comparison signal, which is fixed by the block 5 through the element OR 3. If there is contact, the monitoring of contact ends. When checking the thresholds of the discriminator 2, the source 4 is connected through the key block 9 successively one after another to the inputs of the discriminator 2 by moving the unit in the shift register 8 from the clock pulses coming from the generator 7. This channel search is performed four times, each time the voltage changes on the source 4. Initially, the threshold of the threshold is set to U l, where Unopora (o), is the threshold of the discriminator 2, l is the maximum permissible measurement error of the signal as and "orogs" (o) Then exposes the voltage threshold (o) +. In the first case, none of the channels of the discriminator 2 should be rejected. In the second case, none of the channels of the discriminator 2 should show a valid signal. Reject and go signals are fixed each time separately. for each channel, so the fault is automatically identified. Similarly, the unit threshold is checked on the ultrasonic voltage threshold U (i and U, "rUnoporaUyb Y When and J the control unit 5 should not fix the signal, but receive a signal for faults. If all four cases are correctly executed in the fourth mode, then The thresholds of discriminator 2 are set correctly. Otherwise, a malfunction is fixed for the operator who takes measures to eliminate the detected malfunction. Thus, using this device will provide enhanced functionality (the ability to detect the closure of any probes), The accuracy of the controller (automatic control of the thresholds of the multichannel amplitude discriminator) will increase, which will increase the percentage of yield of the circuits, increase the performance of the integrated circuit control device. The invention contains a device for controlling integrated circuits containing serially connected multichannel amplitude discriminator, the first element OR, a control unit and a clock pulse generator, the second output of the control unit being connected to the inputs of the memory unit and programmable power source, which is based on the fact that, in order to increase the reliability of the control, a key block and a series-connected ring shift register and a second electrically HTOB OR block are entered into it, the outputs of which are connected to the master inputs of the multichannel amplitude discriminator, and the second inputs to the outputs of the block the memory, the outputs of the key block are connected to the measuring inputs of the multichannel amplitude discriminator, which define the inputs — to the output of the programmable power source; the first control inputs — to the outputs, are circular shift register, and the second control inputs to the second output of the control unit and to the write input of the ring shift register connected to the clock input to the output of the clock generator, and the high-level output to the second input of the control unit. Sources of information taken into account during the examination 1. USSR author's certificate No. 472346, cl. G About F 11/00, 1972. 2. Authors certificate of the USSR 531104, cl. G 01 R 31/02, 1975. 3. USSR author's certificate for application number 2428043 / 18-24, cl. G About F 11/00, 1976 (prototype).