SU1005061A1 - Digital assembly checking device - Google Patents

Description

The invention relates to digital computing, in particular, devices for checking digital computer components, such as microchips.

A device for controlling digital nodes is known, comprising a pulse generator, a binary counter, an AND element, a reference chip, indicators, a comparison unit, a reset key.

A disadvantage of this device is that code combinations defined by all the states of a binary counter are supplied to the inputs of the tested and reference microcircuits, although there are prohibited states among them.

Closest to the proposed technical entity is a device for controlling digital nodes, comprising a pulse generator, a binary counter, an AND element, an e-chip, indicators, a comparison unit, a reset key, a single pulse generator, a single step key, an exception block prohibited states, two elements OR C2.

However, in this device, binary code code combinations are also supplied to the input of the tested and reference microcircuits, among which there are also prohibited ones. If there are RS-flip-flops in the tested microcircuit, after the supply of forbidden combinations to the R and S inputs, the flip-flops turn into odd-valued states determined only by the asymmetry of their circuits. This may lead to the theme that, as a result of supplying the input signals, the triggers of the tested and reference microcircuits are set to

15 different states, after which further testing of the microcircuit becomes unreliable. In the known device, the exclusion block of inhibition states only masks the signal from the block

20 comparisons when applying to the inputs of the tested and reference microcircuits of forbidden kszhbination, i.e. This device does not allow reliable control of circuits with RS-Triggers.

The purpose of the invention is to increase the reliability of the control.

This goal is achieved by the fact that a device for controlling digital nodes containing a counter, a reference node, a pulse generator, a single pulse generator, a first AND element, an OR element, a two-switch body, three display units, a block comp. In this case, the outputs of the counter are connected respectively to the inputs of the block of exclusion of prohibited states of the single pulse generator input through the first switch connected to the positive potential bus, the output of the single pulse generator is connected to the p. input of the OR element, the second input is connected to the output the first element And, the output of the Element OR is connected with the counting input of the counter, the installation inputs of the counter, the reference node and the tested node are connected via a second switch to the field bus A potential loss, the outputs of the tested node are connected to the first group of inputs of the comparison unit and the inputs of the first display unit, the outputs of the reference node are connected to the second group of inputs of the comparison unit and to the inputs of the second display unit, the output of the comparison unit is connected to the first input the first element And the second input is connected to the output of the pulse generator; a register is entered, the element is NOT; the second element is AND, the output of which is connected to the control input of the register, the installation input of which is connected to the installation input the information inputs of the register are connected to the outputs of the counter, the outputs of the register are connected respectively to the inputs of the checked node, to the inputs of the reference node, to the inputs of the third display unit, the output of the prohibited states exclusion block is connected to the input of the NOT element, the output of which is connected to the first input the second element. And, the second input of which is connected to the output of the pulse generator. FIG. 1 is a diagram of the device of FIG. 2 - block diagram of the removal of prohibited states. The device contains checked 1 and reference 2 digital nodes, a generator of 3 pulses, a generator of 4 single pulses, element 5, element OR b, counter 7, first switch 8, second switch 9 blocks 10, 11 and 12 of the display, block 13, block 14 of the prohibited states elimination, the element NOT 15, element 16 and 16, the register 17. The block of the prohibited states elimination (Fig. 2) consists of the decoder 18, the switches 19 and the element OR 20. The digital node test starts with the switch 9. this resets counter 7, register 17, check dth 1 and reference 2 nodes to initial state. The display unit 10 shows the zero state, the corresponding combination of logic levels applied to the inputs of nodes 1 and 2. If there are identical combinations of logic levels at the inputs of nodes 1 and 2, the display units 12 and 11 show the same numbers, and the block 13 Comparison sends an enable signal to the input of the element AND 5 and the next pulse from the generator 3 passes through the element OR 6 to the input of the counter 7. On the leading edge of this pulse, the counter 7 changes its state by one. The new state of the counter 7 is fed to the inputs of the register 17 and the forbidden state exception block 14. The switch 19 of the forbidden state block 14, corresponding to the forbidden states, is set to the position where the outputs of the decoder 18 are connected to the inputs of the OR element 20. When a permitted combination appears at the output of the counter 7, the block 14 forms a zero potential at its output, which through the element DOES NOT enter the input of the element I 16. Due to this, the pulse from the generator 3 enters the control input of the reg Stra 17. By this falling edge ca momentum state counter 7 is recorded in the register 17 and fed to the inputs checked emogo 1 and 2 of the reference nodes. When a combination of logic levels representing the forbidden state appears at the output of the counter 7, a single potential arises at one of the outputs of the decoder 18, which through the corresponding switch 19, the element OR 20 and the element NOT 15 enters the input Ka of the element 16. As a result, the pulse from generator 3 does not pass to the control input of register 17. Thus, the forbidden combination is not recorded in register 17 and is not identical to Tynaei; to the inputs of digital nodes 1 and 2-. If, when a logical combination is applied to the inputs of nodes 1 and 2, various states are formed at their outputs, from the comparison unit 13, the potential and pulse from the generator 3 output to the input element 5 is not fed to the input of the counter 7. According to the blocks 10, 11 and 12 indications can be registered: log the logic levels to; the inputs and outputs of nodes 1 and 2. To continue the test, in this case, switch 8 must be turned on. Generator 4 triggers one pulse that changes the state of the counter by one, then the process repeats. Introduction to the device of register 17, element 16 and element 15 does not allow 15 to exclude forbidden combinations from the number of sets of logic levels arriving at the inputs of the digital nodes to be checked and that, increase the accuracy of the control, ensure the control of elements pag mti with prohibited input influences.

Claims (2)

1. Universal logic tester for testing chips in production. - Electronics M., World ,. /, 1974, 8, p. 65-67. 2. USSR author's certificate number 648981, cl. G 06 F 11/00, 1977 (prototype).