JPH0458584B2 - - Google Patents

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention relates to an improvement of an IC testing device, and in particular, a function for automatically detecting that a storage means for storing the results of determining whether an IC is good or bad has become defective. The purpose of this project is to provide an IC testing device with the following features.

<Prior art> Fig. 1 shows a conventional IC testing device. In the figure, 1 indicates the main body of the test device. The test device main body 1 has an expected value pattern generation source 2 and a test pattern generation source 3, and a test pattern signal 5 is applied from the test pattern generation source 3 to the IC under test 4. The IC under test 4 generates a response signal 6 in response to the given test pattern signal 5.
Output. For example, if the IC 4 under test is a digital memory element, the response signal 6 can be a signal obtained by once writing the test pattern signal 5 into the IC 4 under test and reading it out.

The response signal 6 outputted from the IC under test 4 is compared with the expected value pattern signal 8 outputted from the expected value pattern generation source 2 in the logic comparator 7, and it is determined whether they match or do not match. The judgment result of the logical comparator 7 is taken into a storage means 9 constituted by, for example, a D-type flip-flop, and by taking out the output of the storage means 9 with an OR gate 11, a pass/fail judgment output is obtained at an output terminal 12. I can do it.

In other words, assuming that the logic comparator 7 outputs L logic as a match output, when all output terminals of the IC under test 4 match the expected value pattern, it outputs an L logic signal indicating good to the output terminal 12. .
When a response signal that does not match the expected value is output from any one terminal of the IC under test 4, the logic comparator 7 to which the response signal is applied outputs H logic. As a result, an H logic signal indicating a defect is output to the output terminal 12. Therefore, when an H logic signal is output to the output terminal 12, it indicates a defect, and when an L logic signal is output, it indicates a good state.

The storage means 9 is generally a D-type flip-flop, which takes in the comparison result of the logic comparator 7 using the clock signal 13, and resets the memory using a reset signal at the end of the test to prepare for the next test.

<Conventional Disadvantages> As described above, the IC testing apparatus is structured to compare the response output of the IC under test with the expected value pattern, and to store the comparison results in the storage means 9. Therefore, an erroneous determination result will be output that the D-type flip-flop constituting the storage means 9 has become defective. In other words, if it is defective in the set state, H logic continues to be output from the output terminal Q, so there is a drawback that a defective judgment result is output even if the IC 4 under test is a good product.

Furthermore, if the storage means 9 becomes defective in the reset state, the L logic signal continues to be output from the output terminal Q, so there is a drawback that even if the IC 4 under test is defective, it outputs a determination result that it is a good product.

For this reason, conventionally, in order to diagnose whether or not the storage means 9 is operating normally, an element that is guaranteed to operate normally is connected in place of the IC 4 under test.
At that time, a method is adopted in which it is determined whether or not the storage means 9 is normal by looking at the determination result outputted to the output terminal 12.

However, when using this diagnostic method, if the IC is being continuously tested automatically, the test must be temporarily interrupted.
Self-diagnosis must be performed by connecting a normally operating element to the part where the IC4 under test is installed. Therefore, since the test must be temporarily interrupted, there is an inconvenience that the test time is wasted. In addition, in such a diagnostic method, each time the IC under test is replaced, the storage means 9 is
It is impossible to self-diagnose. For this reason, the storage means 9 is diagnosed, for example, when a certain number of consecutive bad determination results occur, or when a certain number of consecutive good determination results occur.

Therefore, the judgment result immediately before diagnosing whether or not the storage means 9 is normal becomes unreliable, and in this respect, the reliability of the test is deteriorated.

<Object of the Invention> The present invention aims to provide an IC testing device that can monitor the state of the storage means 9 every time the test of the IC under test is completed.

<Summary of the Invention> In this invention, when the IC under test is being replaced, the storage means is operated to the set state and the reset state all at once, and it is determined whether the storage means is indeed operating according to the instructions. , when it is confirmed that all storage means are working as instructed, the next test subject
It is configured to perform IC testing.

Therefore, according to the present invention, since the quality of the storage means is always self-diagnosed before testing each IC under test, the test results are reliable, and highly reliable IC tests can be performed.

<Embodiment of the Invention> FIG. 2 shows an embodiment of the invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals. In this invention, a reset signal 14 is applied to the terminal 15 from the test apparatus main body 1. This reset signal 14 is applied to the reset terminal R of the D-type flip-flop forming the storage means 9 through an OR gate forming the reset signal generating means 16.

The off gate 11 indicates that all the storage means 9 have entered the reset state by supplying the reset signal 14.
The reset state detection signal 18 is obtained as an H logic signal 18 from the inverted output terminal 17 of the reset signal generating means 19, and is applied to one input terminal of an AND gate. A test start signal 21 is applied from the test apparatus main body 1 to the other input terminal of the set signal generating means 19.

Assuming that everything in the storage means 9 has been reset, the inverted output terminal 17 of the OR gate 11
A reset state detection signal 18 of H logic is outputted from. As a result, when the self-diagnosis start signal 21 shown in FIG. 3B is applied to the set signal generating means 19 after the reset, the set signal generating means 19 outputs an H logic signal. This H logic signal is applied to the set terminal S of the storage means 9 to invert all of the storage means 9 to the set state.

In order to detect that all of the storage means 9 have entered the set state, a set state detection means 22 constituted by an AND gate is provided, and when all of the storage means 9 have entered the set state from this set state detection means 22. A set state detection signal 23 of H logic is obtained. The set state detection signal 23 is applied to the reset signal generating means 16 through the differentiating circuit 24 and the delay circuit 25, and a reset signal is applied to the reset terminal R of each storage means 9 through the reset signal generating means 16.

At the same time, the output of the delay circuit 25 is applied to one input terminal of an AND gate 26. and gate 26
A non-test signal 27, which becomes H logic when no test is in progress, is applied from the test apparatus main body 1 to the other input terminal of the test apparatus main body 1. Therefore, in the non-test state, the differential pulse output from the delay circuit 25 is applied to the delay circuit 28 through the AND gate 26, and the test start command signal 29 is applied to the test apparatus main body 1 through the delay circuit 28.

<Operations and Effects of the Invention> According to the configuration of the present invention described above, when the reset signal 14 shown in FIG. R is applied to invert all storage means 9 to the reset state.

When all of the storage means 9 are inverted to the reset state, an H logic reset state detection signal 18 is obtained at the inverted output terminal 17 of the OR gate 11, and this reset state detection signal 18 is applied to one input terminal of the set signal generation means 19. . After the reset state detection signal 18 is obtained, the test device main body 1 is
When the self-diagnosis start signal 21 shown in FIG.

Here, for example, in a reset operation, the storage means 9
If one of them remains set and becomes defective, the inverting output terminal 1 of the OR gate 11
7, an H logic reset state detection signal cannot be obtained. Therefore, if such a defect exists in the storage means 9, the set signal generating means 19 is kept closed and no set signal is supplied to the storage means 9. Therefore, the set state detection signal 23 cannot be obtained because the subsequent operation, that is, the set state detection means 22 cannot detect that all the storage means 9 have been inverted to the set state. Therefore, the differential pulse 25' is output from the differentiating circuit 24.
will not be output, and as a result, the reset signal will not be given to the storage means 9 through the reset signal generating means 16, so the test start command signal 29 will not be given to the test apparatus main body 1 forever, and the test will not start. It is possible to know if there is an abnormality because it does not occur.

On the other hand, if any one of the storage means 9 remains in the reset state and becomes defective, the reset state detection signal 18 can be obtained from the inverting output terminal 17 of the OR gate 11. Therefore, since the set signal generating means 19 is controlled to be open, the self-diagnosis starting means 21 is applied to the set terminal S of the storage means 9 through the set signal generating means 19. Assuming that one of them is defective in the reset state, the AND gate 22 cannot detect the set state. Therefore, since the set state detection signal 23 is not output, the differential pulse 25' is not output from the differentiating circuit 24. Therefore, in this case as well, the test device main body 1
The test start command signal 29 will not be given to the test start command signal 29.

As explained above, according to the present invention, the reset signal 14 and the self-diagnosis start signal 21 are output after the test is completed, and these signals are used to operate the storage means 9 into the set state and the reset state, and the state is reversed. If there is an abnormality, the tester enters a hibernation state so as not to perform the next test, so it is possible to perform highly reliable tests without producing erroneous test results.

[Brief explanation of drawings]

Fig. 1 is a connection diagram for explaining a conventional IC test device, Fig. 2 is a connection diagram for explaining an embodiment of the present invention, and Fig. 3 is a waveform diagram for explaining the operation of this explanation. . 1... Test device main body, 2... Expected value pattern generation source, 3... Test pattern generation source, 4... Test target
IC, 7...Logical comparator, 9...Storage means, 11
. . . Reset state detection means, 16 . . . Reset signal generation means, 19 . . . Set signal generation means, 22
. . . Set state detection means, 26 . . . Test start command signal generation means.

Claims (1)

[Claims] 1. A. An IC testing device that compares a response output output from an IC under test with an expected value and tests the IC based on whether or not they match, B: a plurality of storage means for storing the comparison results; , C reset signal generating means for supplying a reset signal to all of the storage means; D determination means for detecting that all the storage means have entered the reset state when this reset signal is applied; E of this determination means. A reset signal generating means for inverting the storage means to the set state by a diagnosis start command when the judgment result is good; and G test start command generation means for resetting the storage means and giving a test start command to the test equipment based on the detection output.