JPS58148974A - Card tester - Google Patents

Abstract

PURPOSE:To separate a faulty route from a feedback loop, by generating CRC data and utilizing an initial signal waveform at each node in a circuit as acquisition diagnostic information. CONSTITUTION:According to a pattern from a pattern generation part 21, the CRC of each node of a logical circuit card 22 is generated at the generation part CRC-P of a CRC generation part 23. Then, CRCs generated at generation parts CRC-1, CRC-2... when a normal card storing in the CRC data memory 24a of a control processor 24 is used, are compared with CRCs generated successively at the generation part 23 to diagnose each node. On the other hand, waveforms of respective nodes in a specific initial period are stored in a time memory 28 through a waveform transistor sensor 25, pattern counter 26, etc., and used as the acquisition information by a processor 24 to obtain timepiece functions; even when a feedback loop is present, a faulty loop is specified. Then, the faulty loop is separated from the feedback loop and the rate of automatic diagnosis is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Summary of the Invention The present invention relates to a tester for automatic diagnosis of logic circuit cards (printed circuit boards 1) used in various digital devices. The system is such that each node KsP in the card observes the signal sequence, compresses the signal sequence into 411-character tCRC, etc., and performs diagnostic processing.

The initial signal liquid form at each node is used as supplementary information during diagnostic processing, and the present invention relates to a nine-card tester.

Background of the technology It determines whether the logic circuit is true or not, and furthermore, if there is a failure in the logic m* path! F. The process for detecting the failure point becomes more difficult as the number of logic stages in the logic circuit increases and the number of connection relationships of logic 3II elements involved increases.

Conventionally, for this purpose, a turn sequence is given to the circuit under test in a series of test nodes, and the signal sequence of the logic value at each clock point in the operation of the signal node of the nine circuits is interpreted as a signal sequence of logical values and converted into CRC data. Therefore, the quality of the data is determined by comparing it with similar CRC data. Normally, at the same time as collecting CRC compressed data, changes in node states that occur during the input period of the test pattern sequence are collected as information such as the number of pulses within one period, the number of transitions, and the length of high signal level time. This will also be done. here.

Collectively refers to compressed data regarding these signal characteristics.

This will be referred to as characteristic compressed data, however, in the explanation of specific examples to be described later, to simplify the explanation, all CRC data will be represented as 1% compressed data.

Mamemasashi Jojoen! Figure 1 shows a schematic configuration of a conventional card tester, in which 1 is a non-defective or logic circuit card to be tested, and 2 is a series of test sets applied to the external input terminal of the card.

3 is the generation of CRC characteristic compressed data, CRC-1
CRC-P to CRC-P; 4 is a control processor that controls the entire card tester; and 5 is a signal sequence connected to the external output terminals tcRc-l to CRC-1-Kll of the card 1; The output line 6 is a signal output line for monitoring internal nodes of the card 1, such as an automatic probe, and is connected to the CRC-P. 7 indicates the control line for start, stop, and 0. During operation, a CRC is generated for non-defective O cards. A series of seven test turns is input to the card, and at the same time the state of the external output terminal and internal node is set to Il!
measure Then, for each external output terminal and internal node, an operation based on the 0CRC generating polynomial is performed on all data to generate a CRC. Obtained 9 CRC
The data is stored in memory within the control processor 4.

Next, a similar CRC generation process is performed on the circuit card under test, and the results are stored.

In this way, 7tCRCt! , which compresses the characteristics of the nine operating states that occur at specific nodes such as external output terminals and internal nodes in response to a series of test patterns, so KCRCt can be compared for each node between a non-defective circuit and a circuit under test. By doing so, it is possible to detect the presence or absence of a single circuit failure and its location. Fault point tracing by checking the correctness of the CRC is performed from the output side to the input side.

This is called the reverse search method.

FIG. 2 is an explanatory diagram of the circuit failure detection method. The same figure (→ is a circuit without a feedback loop, the same figure (h
) shows an example of a circuit with a feedback loop. In the figure, 8.14 represents an external input terminal, 13°19Fi external output terminal, 9 to 12 and 15 to 18 represent in-circuit logic elements, G is a normal CRC node, Bt; i Abnormal C
RC node is shown.

Figure 2 (in →, if the CRC of the output terminal 13 is found to be abnormal, the logic elements 9 to 12 connected to the output terminal 13) I'll investigate. Since the CRC of the node changes from B to G before and after element 11, it can be determined that element 11 has a failure.

However, this CRC reverse search method has a problem in that it takes a long time to process one diagnosis because a single CRC is generated for the entire test pattern series after inputting it.

Further, in the circuit of FIG. 2(A), a feedback loop is provided from after the logic element 180 to the logic element 16. In this case, even if there is a failure in element 111, after a certain period of time, the abnormal signal will be transmitted to all nodes in the feedback loop, and each C of these nodes will be
RC becomes abnormal. Therefore, when entering the center of the feedback loop using CRC inverse search, if the feedback loop is complex, it is necessary to observe many points to round the loop itself. It is impossible to specify further.

As described above, the conventional method has a problem in that the diagnostic resolution is low when diagnosing circuits with a feedback batter loop.

OBJECTIVES AND SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the conventional rounding system, and, as in the conventional case, generates a single CRC data from the entire turn sequence by adding two circuits at an internal node. , observe the pulse signal changes over a certain period of time,
It can be recorded along with the timing and used as supplementary diagnostic information.

It provides a card tester with a built-in design.

1% of the initial pulse signal waveform observed at each node
In many normal logic circuit cards, the waveform of the first few dozen pulses accurately represents the propagation status of the fault signal waveform arising from the fault point.

This information is extremely effective in determining the correlation between signal changes at successive nodes, that is, in determining whether the operation of a logic circuit element is correct or not.

In addition, in reality, most failures in logic circuit cards manifest abnormal waveforms in the first few pulses, and there are very few cases in which the presence or absence of a failure can be finally determined from the subsequent pulse waveforms. It's a good thing.

The present invention has been made by focusing on two or more points, and includes a turn generating means for generating a series of test patterns for testing a logic circuit card;
Observe the signals at the external output node and circuit internal node of the logic circuit card.

means for generating compressed characteristic data such as one CRC for each injection of the entire test pattern series for each node;
a characteristic compressed data message for storing the generated nine characteristic compressed data; an IIK for injecting the test pattern series into the logic circuit card; a means for displaying the injection current time of the armpit test pattern series; and an external device for the logic circuit card. Equipped with means for observing signals at output nodes and circuit internal nodes and extracting waveform information for an appropriate number of initial pulses for each node, and a waveform information memory for storing nine extracted waveform information @t nodes. It is considered to be moldy.

Examples of the invention A detailed explanation will be given below based on examples.

FIG. 3 is a block diagram of two embodiments of the present invention. In m-,
21 is the test pattern source and Dew! 1. Logic circuit card of good quality or subject to test, 26 is its external output terminal, 22h is internal observation terminal for automatic programming, etc., g3 is CR
C generation unit # 24 a control processor, 24α a CRC data memory, 25 a waveform transition sensor, 26 a pattern counter, 27 jy'-), and 28 a time memory, respectively.

The logic circuit card 22 has external output terminals 01.01°...
, Or, and the internal node P1. Ps, . . . , PA. Although only one internal observation terminal 22b is shown, it is merely an example.

The control processor 24 controls the pattern generator 21, the CRC generator 23, and the memories 24a, 2B.
Controls read/write, data management layer, card diagnostic processing, etc.

Figure 4 is the input cover turn in the circuit of Figure $3.

Two examples of node waveforms and transition times are shown.

Next, the operation of the embodiment will be explained.

■ Generation of diagnostic data Collecting correct status information during operation of the non-defective card, which is the basis of diagnosis. The test pattern source 21 is activated by the pattern generation program of the control processor 24 . During the test pattern series, the external output terminal l! of the upper three non-defective cards 22 of the CRC generation section! am and the signals appearing above at the internal observation terminal 22 are continuously observed.

The entire deformity of the signal waveform is compressed to generate 90 RC data. The generated RC data is sent to the control processor 24
It is stored in the internal memory.

The signal waveforms on the external output terminal 22g and the internal observation terminal smh are input to the CRC generator @R3, and at the same time are also input to the waveform transition sensor 25, and the /J pulse rising 9 and falling transition timing iy is input. Observed.

The pattern counter 26 has the role of a clock that displays the current point in time of the input test l (turn sequence).

When the waveform transition sensor 25 detects a rising or falling transition in the observation signal, it opens the Y-toe 27t-, reads out the time at that point from the Nosetan hand quantity 26, and stores it in the 1-time memo IJ a B. The amount d of the 0 time memory 28 to be written depends on the number of observation target signal lines in the card and the number of observation target signal lines in the card.
The number of observed pulses determined by the number of pulses is set to several tens of pulses, and the amount of information increases as the number increases, but is limited by the processing performance of the control processor.

Three primary data are collected for all nodes including all signal lines and external output terminals of the card.

aC v for the entire C+ input test pattern sequence:! #! Logic level t in the initial state on the measurement node: the first few tens of ξ (no 1, 2, ... rL
) The diagnostic data of node NL with node number t at the time of occurrence of minute signature 11 is:

(Ci, U&, tal, tin, …, ttn
) ■ Judging whether the card is good or bad Set the card under test in the card tester, obtain the CRC data C, / of the external output terminal group, and compare it with the CRC data of the non-defective card collected in step ■. If they match, it is determined to be a good product, and if they do not match, it is determined to be a defective product.

■ Fault point tracing diagnosis For the defective product card, search backwards from the external output terminal that has become Ci'5lCi in the direction of the input terminal ・Cs'〆(
If there are multiple terminals indicating j, the data ν.

The levels and transition points of both waveforms are compared using t, and the waveforms are classified into the following two types, 81 and B2O, based on the differences.

B1: The discrepancy with the non-defective waveform was recorded on the 2nd day of the 9th time, and it occurred within the first few tens of pulses. If there is a terminal of type B1 that occurs later, the time F E P (F
irstErrorPa1nt) is selected as the reverse search start terminal. This terminal is
Since the time it takes for abnormal waveforms to propagate and reach the external terminals after they occur at the fault point is minimized, the influence of defective waveforms passing around can be minimized, making it the easiest to trace the fault point. It is highly likely that

On the other hand, if all of the output terminals exhibiting an abnormality are of the B2 type, the one with the smallest tiz is selected. In this case, since the waveform up to tits was normal, in other words, at worst, after tirL, the product starts to behave differently from the non-defective product. Normally, this state occurs when a certain node group is frequently activated as a path for test patterns of other circuit groups, and when such a test is performed, it behaves exactly the same as a good product (no debris around the fault).
It happens when something like that happens.

The reverse search process is started from one external output terminal carefully selected as described above. Go back to the head input side,
For each node, the CaC data CL and CL' are compared to trace the point of failure.

When faced with a fan-in circuit having multiple lines as shown in FIG. 5, the same concept as that used for selecting external output terminals can be applied. In the figure, 29 to 32 are logical elements.

34 to 37 are signal lines (nodes), one type of each line is shown and 7'tB1. B2. Ha.

It is G.

Now, when selecting the next line from line 34, the first discrepancy waveform occurrence point in line 34 F E P
t"h, and the 'I final transition recording time of lines 35 and 36 are tan and tsB.

(1) When fl < tttn, fz < tsB, at time f1 when all the input lines of the logic element 29 show correct signal waveforms, the signal waveform of the seventh output line becomes an interference waveform. Therefore, it is determined that the failure point is near the logical element 29.

(1) When h > tm + fl < tsK, select 35 as the secondary observation line.

If multiple Bl type lines are observed.

The line with the minimum discrepancy occurrence time FEP is always selected and the search line is extended.

If a point is reached where the next input lines all have FEPs that are slower than the current line's FEP, or all have normal CRCs.

The search ends. In this case, the failure point can be predicted to be near the arrival point.

If you run into a feedback loop before finding a point that meets the above conditions and it becomes difficult to proceed with the search, select the B1 line with the minimum FEP and the B2 line with the minimum FEP above the minimum FEP. A group of lines with a small final transition time t can be selected as a region candidate near the failure point.

Effects of the Invention As mentioned above, with only the conventional CRC reverse search method, it is impossible to track the direction in which the harmful waveform is transmitted when it enters the feedback loop. However, according to the present invention, Since it is used on the signal waveform in the initial stage after pattern input, it is easy to separate the fault route from the feedback loop, and a high automatic diagnosis rate can be obtained.
Diagnostic costs can be reduced.

[Brief explanation of drawings]

FIG. 91 is a schematic configuration diagram of a card tester using a conventional CRC reverse search method, and FIG. 2 is an explanatory diagram of its operation. FIG. 3 is a configuration diagram of an embodiment of the present invention, FIG. 4 is an operation waveform diagram thereof, and FIG. 5 is an operation explanatory diagram. In the figure, 21 is a pattern generation section, 22 is a logic circuit card for non-defective and non-defective tests, and 23 is a CRC generation section. 24 is a control processor, 24at'i is a CRC data memory, 25 is a waveform transition sensor, 26 is a pattern needle counter,
27 is a gate, and 28 is a time memory. Patent Applicant User Tsuta Electronics Industry Co., Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) 1 figure f 2 figure 3 figure 4 figure

Claims (1)

[Scope of Claims] The present invention includes pattern generation means for generating a series of test patterns for testing a logic circuit card. Observe the signals of the external output node and the circuit internal node of the circuit card, and test each node above.) Generate compressed characteristic data such as one CRC for each injection of the entire Hattern series, and use these data as well. In a tester that uses a method to troubleshoot problems. In addition to these mechanisms, means for observing signals at external output nodes and circuit internal nodes of a logic circuit card and extracting waveform information regarding an initial appropriate number of pulses for each target node; This card tester is equipped with a waveform information memory that stores waveform information for each node, and has an enhanced obstacle ruin mechanism.