SU1312580A1 - Device for checking and diagnostic testing of digital units - Google Patents

Abstract

The invention allows in the dialogue mode before each step of testing with a logic probe to conduct an intermediate analysis of the situation and. to determine control points, the check of which is necessary at this step, and, accordingly, weed out unnecessary points. The purpose of the invention is to increase the device performance by reducing the number of manual operations. The device includes an interfacing unit 8 to which it is connected (L from 0 el 00

Description

object to be tested 12, control block 1, test information memory block 7, indication block 2, logical probe 9, input 5 of the initial device setup, address counter 6, dialog input 10 start the troubleshooting process in the dialog mode, automatic process start input 11 control, block 3 of the memory of the object model and block 4 of the analysis. The control unit 1 operates on the basis of a predetermined firmware and ensures the interaction of all the other units. In the process of automatic testing, the control unit provides

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The invention relates to computing, more specifically to the means of automatic control of digital objects, and can be used to check the integrated circuits, as well as assembled on the basis of their nodes and blocks of electronic computers and other digital automation both in production conditions and during experienced design work. In connection with the increasing complexity of computer units, the amount of control operations required for evaluating the quality of these units increases, so the automation of diagnostic operations, as one of the more labor-intensive stage in the process of manufacturing computer blocks and other digital equipment, greatly increases productivity.

The purpose of the invention is to increase productivity by reducing the amount of manual operations.

1 shows a block diagram of the device; in fig. 2 - block diagram of the interface and control unit; Fig. 3 is a block diagram of a micro-control unit; 4 is a flowchart of the operation of the firmware control unit.

The device (Fig. "1) contains the microprogram control unit 1 of the display unit 2, the block of memory of the object model, the analysis block 4 of the controllable input signal block and compares the response of the latter with the reference signals. In the event of a fault, the automatic check is suspended and the device goes to an interactive mode in which the analysis unit, by generating and solving a differential equation describing all possible causes of a false signal at the output of the suspect chip, determines the inputs, the test Otori at this step necessary with logic probe, and otseivaetvhody, checks are not: a smysla.4il. 2 tab.

pivot points, device setup input 5, 6 address counter, test (reference) information memory block 7, interface 8 and control block 8

ohic probe 9, input 10 start-up of the diagnostic process, input 11 start of the monitoring process, In the process of monitoring and troubleshooting, a monitored device is connected to the device

object 12.

The analysis unit 4 contains the first (address) register 13, the second register 14, the switch 15, the first multiplexer 16, the second multiplexer 17, the first comparison circuit 18, the fifth trigger 19, the decoder 20 zero, the third multiplexer 21, the fourth multiplexer 22j the third register 23 , the second comparison circuit 24, the fifth multiplexer 25, the first to fourth triggers, respectively 26 to 29, the Interface 8 and Control unit 8 (FIG. 2) contain the encoder 30, the OR element 31, the register 32, the comparison block 33, and the input signal driver 34 .

Firmware control unit 1 is designed to synchronize the operation of all units of the device, to control the exchange of data between the blocks, as well as between the device and the monitored unit to control the automatic control mode, as well as the process of troubleshooting in the dialogue mode, to analyze the test results and generate

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no messages for visualization in display unit 2.

Unit 1 ensures the interaction of all units of the device by generating appropriate control signals in accordance with the values of the informative signals arriving at the inputs of the logical conditions of the unit. The operation algorithm of the control unit 1 is shown in the form of a flowchart in FIG. 4. The control signals Y; (1-1t-24), specified in the operator vertices of the algorithm, are microcommands described in Table 1, where each signal is assigned the number and discharge of the output of block 1, which is the source of this signal, the block number the signal is controlled as well as the action performed under the control of this signal. Informative signals representing conditions X; in conditional verbs of the algorithm, are described in Table 2, where each signal X is associated with the number and bit of the input of block 1, the number of the block that is the source of this signal, and the characteristic of the logical condition represented by this signal.

The firmware control unit 1 (FIG. 3) contains a multiplexer 35, a multiplexer 36, a register 37, an incrementor 38, a clock generator 39, a micro-command register 40, a block 41 of the firmware ROM. Multiplexer 35 is designed for switching logical conditions, multiplexer 36 is for selecting the address of the next microcommand, register 37 is for storing the address of microcommand, block 38 of the incrementor is for adding one to the address of the current microcommand, clock generator 39 is for synchronizing operation of block 1, register 40 is for storing the microcommand, and block 41 of the ROM is for dp storing the microcommand of the algorithm. The cells of the ROM 41 and the register 40 microcommands contain 34 bits. The bits 1-24 of the register 40 micro-commands correspond to the 24th control signal Y., i 1-24, of which bits 1-3 and

23 form a five-bit you; : one block 1, bits 4-8 form, respectively, the sixth, first second, third, fourth one-bit outputs of block 1 and bits 9/23 form a 15-bit group of outputs of block 1 (Table 1) bit d 24 connect4

whose input to the clock generator 39, the output of which is connected to the etching inputs of registers 37 and 40, bits 25-28 are connected to the control inputs of the multiplexer 35 and bits 29-34, designed to set the transition addresses to the microprogram, are connected to the first information input of the multiplexer 36.

H} The information inputs of the one-bit multiplexer 35 together with the input 5 of the initial installation, which is connected to the reset input of the register 37, form the inputs of block 1 (Table 2),

and the output of the multiplexer 35 is connected to the control input of the multiplexer 36 which determines which of the logical conditions X ;, j 1-13, is transmitted to the output of the multiplexer. Code 0000 corresponds to zero transmission (the corresponding input of the multiplexer is grounded), codes 0001 - 1101 correspond to the transmission of signals xx 1, respectively, and code 1111 corresponds to transmission of the unit (the corresponding information input of the multiplexer 35 is connected to a power source).

Mylt Schlekcop 36 is intended for

transfer the next next, the address of the micro-command to the address input of the block 41 of the ROM of the micro-command.

With code 0000, the multiplexer 35 has a natural transition to microprogramming: a gate (transition in a microcommand in the next cell), with code 1111 an unconditional transition to an address in bits 29-34 of register 40 microinstruction is implemented, and for other codes 0001- 1101, a conditional transition is implemented according to the signals of conditions X - X.

The display unit 2 is designed to visualize the results of monitoring and troubleshooting, as well as messages to the operator to continue the search process. Block 2 contains a board where the signs “Good”, Diagnostics, Put a probe, Fault localized and two addresses — the address of the component (the element of the device under test at the chip level) and the address of its contact can be spotted. The sign GOD appears with a positive outcome of the automatic control process. The inscription Diagnostics in progress is an indication that in the auto513 mode

Mathematical control detected a false signal and started troubleshooting mode in the dialog mode. The text Put a probe is an indication to the operator that in order to continue the process of finding a defect, measurement with a signal probe is required at the control point whose location is indicated by the indication of the address of the chip and its contact. The caption Fault Localized appears at the conclusion of the troubleshooting process. Illuminated, while the addresses of the component and its contact indicate the localized location of the defect. If both addresses are illuminated, the defect is localized on the specified contact of the component. If only the address of the component is illuminated, the component itself is defective.

Block 2 is controlled: from the side of the block. Each of the four labels and each of the two indicated addresses has its own control signal, available at the right time from the block (tab.).

The block 3 of the memory of the object model is intended for storing the mathematical model of the controlled block in the form of alternative ones. For each co-unit of the monitored block with an output Z, some alternative graph G (2) is associated (whose vertex in3G (Z) is weighted by variable Z (m) s representing the signals at the input of the component and the state of its memory. The weight variables have signs G (t) and (w), the unit values of which mean that the value of Z (m) refers to the previous relative to the current set of clock (when specifying the function of memory circuits) and that the value of Z (m) needs to be taken with inversion. 3 pshu words are stored in each cell, describing o, cn, vertex al An ernamental graph (AG). The word consists of the following 1 (their fields are: address A (t) of the lower sequence of vertex t, address A., (t) of the right sequence, vertex of t, address Agj (m) d / 1k of transition to another graph G (Z (m)), representing some other Component of the controlled block 12 with the output Z (m), address А (ш) values of the variable Z (m) for accessing the bits of the memory cells 7 where the table of correct reactions of the controlled block 12 is stored , sign of a shift in time

L (m) menus, inversion sign jb (ja), special check sign

2 (t), the address of the K (t) component in the controlled block 12, issued

5 through the register 14 and the switch 15 to the unit 2 to indicate the next step of connecting the probe or location to the localized fault, the address N (m) of the contact component is 0, also through the blocks. 14 and 15 in block 2 for display,

Analysis unit 4 is designed to screen out unpromising troubleshooting and to determine 15

NIN of those inputs of the components, at the output of which a false signal was detected, which should later be manually checked using a logic probe. Block 4 does not work when the automatic control mode is active and participates only in the online troubleshooting mode.

Register 13 in block 4 is designed to store addresses for accessing memory block 3, in the cells of which the description of the object model is stored in the form of alternative graphs. The output of register 13 is connected to the address input of memory block 3, the control input (read input ) which is connected to the second microprogram control unit v1. Register 14 is intended to receive from block 3 pgs of the word describing the current vertex of the alternative graph. - The information input of register 14 is connected with the output of block 3, and the control input is connected to the sixth bit of the block of outputs of block 1.

0 Register 14 contains 9 subregisters, - intended to receive .codes, respectively A (t), A (t), Hell (t), AjCm), TSt) ,, 1b (t), r (m), K (m), N (m),

5 Switch 15 is designed to transmit addresses K (t) and N (m) to display unit 2 for visualization.

The multiplexer 16 is designed to transmit addresses, respectively, from the conjugation unit 8 or from the multiplexer 17 to the register 13,

Multiplexer 17 is designed to transmit one of the addresses), 5 - (w) or A j (tn) from register 14 to the inputs of multiplexer 16 and decoder 20 zero.

The trigger 9 is for storing the feature Shift in time.

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The decoder 20 zero is designed to find the zero address at the output of the multiplexer 17.

The multiplexer 21 is designed to transmit to the input of the circuit 18 compare, direct or reverse value of the trigger 26, the selection of which is carried out by the unit 1 of the firmware.

The multiplexer 22 is designed to transmit to the input of the comparison value circuit 18 either from trigger 27 or from trigger 28, which is selected by block 1.

Register 23 is for temporarily storing the contents of the address counter 6.

The multiplexer 25 is designed to select the reference value Z (m) from the output of memory block 7 and transfer it to one of trigger 26 or 27. The multiplexer bit should be equal to the sum of the bits at the input of the monitored block 12 and the internal control points of the block 12 assigned to for control with the probe. Trigger 26 and 27 are designed to store the reference value obtained from multiplexer 25. The selection of the target of the reference signal at the output of multiplexer 25, i, e, the selection of triggers 26 or 27 is performed by microprogram control unit 1. The trigger 28 is designed to capture and temporarily store the signal received from the probe. The trigger 29 is intended to store the idle mode indication when the device is paused and waiting for the operator to operate with the probe (i.e., press the restart button 10 to continue the troubleshooting process in the dialog mode),

The input 5 of the initial installation is intended for installation in the zero state of the counter 6 of the addresses of the test program sets and the register 37 of the microcommand in block 1 of the firmware control.

The address counter 6 is designed to store, increment, and decrement the addresses of the test program sets stored in memory block 7.

The test memory block 7 (reference information is intended for storing the input sets of the test program, the reference output sets, and also

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the entire table of correct reactions for the internal control points of the controlled unit. The word width of the memory is equal to the sum of the bits at the input and output of the block 12 and the internal control points of the block 12, designed to control with the probe.

Buffer storage of the current test suite occurs in register 32. Input actions are formed in block 34. Comparison of the output reactions of the object under test 12 with expected reference signals occurs in comparison block 33, Cipher 5 is intended to form {address transmitted via the multiplexer 16 and a register 13 for the memory block in case of detecting a spurious signal at the output of the block 12 during an automatic verification process. Element HIM 31 is designed to generate a knowledge signal in case of non-comparison at least in one of the bits of a multi-bit controlled object 12,

Logic probe 9 is an electromechanical probe for troubleshooting. It transmits the measured signal to analysis block 4 for

Q further comparison with the expected reference response of the object at the test point on which the probe was placed.

Input 10 is used to conduct the next step in the troubleshooting process in the dialogue mode. It is a button that the operator presses after he put the probe on the control panel.

Q point, the address of which is indicated on the scoreboard in the display unit.

Input 11 is used for the initial start-up of the automatic control process. The device works as follows.

Controlled unit I2 is connected via interface 8 unit and control to the device. After starting the device with button 11, the process starts.

P automatic checks using test information stored in memory block 7. The firmware control unit 21 provides reading from the memory of 7 test sets at the addresses

5, counter 6, input (stimulus) signals to the inputs of block 12 and acceptance of the corresponding reactions oi of its outputs. By comparing real reactions with expected ones (reference)

signals, in block 8, the result of the control is generated. If the result is positive, the cycle of the automatic verification process is repeated with the following test set found in the next cell of memory block 7,

In case of a positive outcome of the entire test (the results of the control on all sets are positive), the message “Good” is displayed in the display of block 2, and the device stops,

In case of detection — at some set of test at least one discharge of the multi-bit output of block 12 of the nose corresponds to the real and expected response, the test-driving process, i.e., the automatic check mode, stops. On the display of the display block 2, the message “Diagnostics goes on, and the online search mode M €; starts automatically; the defect is detected; In this mode, under the control of unit 1, a manual search for the defect is performed by measuring with a probe 9 signals at the internal test points of the object under test 12, Points for each step are determined by the analysis unit 4, and their addresses are inditsiruk the score indicating unit 2.

The device in the troubleshooting mode in the dialogue mode works as follows.

Analysis unit 4 opr) unites the number of a component (microcircuit) and its output contact number (connected to the output pin of block 12, on which a false signal is detected. For this, analysis block 4 uses a structural-functional model of the object under test 12 alternative graphs stored in the object description memory block 3. The address for accessing the memory of block 3 is determined by the encoder 30 according to the contact number on the code of block 12 on which a spurious signal is detected, and transmitted through K5 to the multiplexer 1 6 to register 13, Number found the component and its output contact are read from memory block S to register 14, transmitted through switch 15 to block 2 and induced there together with the label Probe Then the operator, using a logic probe 9, determines the correctness of the signal directly on the KONfflOHeHTa pin (microcircuits), info

20

25

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unit 2. When an electrical contact is made between the probe and the corresponding test point, the operator presses button 10,

The analysis unit 4 compares the signal outputted by the probe 9 with the reference signal value at a given test point read from block 7 of the test information memory.

If the signal at the output contact of the component is correct, it can be concluded that the connection is broken between the output contact of block 12 (where the false signal is detour) and the output contact of the component (chip), since there are different values of the signals at different; the ends of the same bond. The address of the detected faulty communication is displayed in the display unit 2 together with the inscription Fault localized.

If the signal at the output contact of the component (microcircuit) of block 12 is also incorrect, further testing of the input contacts of this component is necessary in order to detect a false input signal or if all the input signals are correct to confirm the failure of the component of the microcircuit itself.

Based on the data obtained from block 3 of the volume description description (mathematical model of the component being tested in the form of alternative graphs) and block 7 of the test information memory (table of correct object reactions), analysis block 4 conducts a preliminary analysis of the situation in order to determine input contacts - component components that may be potential sources of a false signal at the component output, and those 45 that cannot be in this role for this situation; Component input contacts qualifying in the intermediate th analysis as a search unused branches dead-rectified 50 are excluded from further manual inspection, and the indicating unit 2 inditsiruyuts component only those addresses of contacts that can be sources of spurious The signal 55 Nala,

The process of intermediate situation analysis is based on modeling the behavior of a component with a false output signal at the current input30.

35

40

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The test set and the state of the memory of the object under test 12, using the alternative graph model (AG).

The analysis starts with setting the reference value of the output signal of the component to the trigger 27. When a spurious signal is detected at the output of block 12, the encoder 30 determines the address corresponding to this output of the vertex m AG and is transmitted through multiplexer 16 to register 13. At this address from memory block 3 In the register 14, information is transmitted that is associated with the vertex ga. The read word consists of the following fields: А {, (t), А (t) Ag (m), Aj (m), tn, (in),, 3 (m), (m), K (m) N (m ). At the address) transmitted from register 14 to the input of multiplexer 25, from memory block 7, the value of the corresponding variable Z (m) (the reference value of the signal at the component output) is found and sent to trigger 27, the starting vertex of the graph of this component is located at address AD (t), which is transmitted from register 14 through multiplexers 17 and 16 to the address register 13. Corresponding information to this vertex is entered from memory block 3 to vertex register 14. Modeling the behavior of the component begins .3 to this initial vertex.

In the process of modeling, there is a movement along a certain path on the graph, according to the values of the variables Z (m) at the vertices m along this path. These values represent the current test set and the corresponding signal values at the internal control points of block 12, which are from the corresponding row of the table of correct reactions (from memory block 7), by addresses) are transmitted through multiplexer 25 to trigger 26. The next vertex the graph on the advanced path for each current vertex m, according to the definition of the AG model, is located at:

A (t)

Ag (m), if Z (m) + i (m) O, .A.i (m), if Z (m) (m) 1,

In the case when a shift in time is required (at T (go) 1), the unit is subtracted from the counter 6 addresses and read from block 7 at the received address of the value of the variable Z (m) for the previous clock cycle. Value

012

Addresses A, (t) or A (t) selected by I according to the appropriate firmware are transferred from register 14 through multiplexers 17 and 16 to register 13 for reading from memory block 3 to register 14: 1 the information word of the next vertex AG on this path .

Two non-intersecting isolates on AG

sets of vertices: a set of M vertices, for which for any path that goes from a vertex to the right (down), and from a graph down (to the right) it does not exist -. doesn’t intersect with per-,

vym path going from the vertex down (to the right), and from the graph to the right (down), the set Mj of the vertices for which the stated condition is not satisfied.

It is known that the vertices from the set Mj that are on the simulated path should always be checked with the probe, and with respect to the vertices from M that are on the simulated -path, the following direction rule applies.

Direction rule: among the vertices of the set M located on the modulated path coming out of the AG

down (to the right), it is necessary to check only those from which the path goes in the same direction, i.e. to the right (down)

The vertices related to the set M can be easily determined for any AH. For such vertices, the sign j- (m) 1 is entered. Accordingly, for the vertices of those have (y) O, the value of the sign yyCu is determined by the feasibility of directional rules. According to this rule, the test with a probe of those component inputs for which it has

a place

Z (m) + / i (m) E,

where Е is the reference value of the output signal of the component (Е 1 corresponds to the output from the graph to the right and Е Е О - to the output from the graph down).

In the process of modeling the behavior of a component with a false 1M signal at the output, in each current

the vertex, where y (t) O, by the rule of direction checks the necessity of checking the corresponding input Z (m) of the component. The value of the reference signal E is stored

in trigger 27, the value of this signal transmitted via multiplex10

sor 22 is compared in comparison circuit 18 with the value 2 (w) for the current vertex m, which is transmitted from trigger 26 via multiplexer 21 in direct or inverse form, respectively, to the value of the inversion attribute p, (ha),

If it is necessary to check the signal Z (ni) with a probe, the addresses K (t) and N (m) are displayed on the display of block 2, which are transmitted from register 14 through switch 15 to block 2. When you press button 10, received by probe 9 of the control point is fixed in trigger 28; Comparison of the reference signal stored in trigger 26 and the real signal stored in trigger 28 also occurs in 20 comparison circuit 18, to which these signals are transmitted, respectively, through multiplexers 21 and 22,

In the case of T (t) 1, a time shift is required to obtain the actual value of the signal Z (m). To do this, first in register 23, the number of the previous clock cycle obtained from counter 6 is fixed. Then, the test segment returns to the beginning by cyclic subtraction of units from counter 6 and checking the sign of the beginning of the segment in memory cells 7. The test segment is re-implemented, but now prior to dialing, whose address is stored in pet HCTpe 23, this set is found by block 24, where the addresses in register 23 and counter 6 are compared,

If the real signal found with the probe matches the reference signal, the process continues.

The renderer also transmits the number, K (t) of the faulty block.

When a probe with a probe 9 detects a false signal on one of the inputs of the monitored component, two cases may occur.

The first is the case when the input of the component on which a spurious signal is detected is at the same time the input of the monitored block 12 itself. Then the fault is also considered localized, the diagnostics process ends and the addresses K (t) and 15 N are transmitted to the display block 2 (m) corresponding to localized defective input.

In the second case, troubleshooting continues with the component connected at the input from the test point30

Coy, which detected a false signal. To do this, the register 13 is transmitted through the multiplexers 16 and 17 from the register 14 to the address Ag (m) for reading from the memory block 3 of the information word 5 of the initial vertex of the graph corresponding to the new component. The reference value of the signal E at the component output is transmitted from block 7 memory through multiplexer 25 to trigger 27. After this, a new simulation process starts, which is associated with analyzing the behavior and checking the necessary input signals of the selected component.

The operation of the device as a whole under the control of the microprogram control unit 1 occurs according to the algorithm in FIG. 4, the steps of the algorithm are commented below.

Step 1, After starting the device (X 1), the next test set is read from memory block 7

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40

(Y), transfer it to the buffer register 32, the formation of input stimulations and the displacement according to,..:,, "

 45 actions rta block 12 and analysis of its reactions. With a positive outcome

path on the graph. The simulation process ends with the zero value of the address A (t) detected by the decoder 20 zero (this corresponds to the completion of the path passed by the rta graph). The end of the path on the graph without detection of complex signals corresponds to the fact that the component itself is faulty. The diagnostics process is over, on the board in block 2 the inscription Fault is localized is displayed. In addition, from register 14 through switch 15 to block 2 of indication for

(X4. 0) go to step 2 to pass the test, if a false signal is detected (X O go to step 3,

Step 2 After the last test set (Xj 1) has been implemented, the device stops (Y), the message Fit (Yj) is displayed on the display of the display unit 2. If the test is not finished (X 0), the unit is added to the contents of the 6-address counter (Yf ). and go to step 1 dl

The renderer also transmits the number, K (t) of the faulty block.

When a probe with a probe 9 detects a false signal on one of the inputs of the monitored component, two cases may occur.

The first is the case when the input of the component that detected a false signal is at the same time the input of the monitored block 12 itself. Then the fault is also considered localized, the diagnostic process ends and the addresses K (t) and N ( m) corresponding to the localized defective input.

In the second case, troubleshooting continues with the component connected to the input from the test point

Coy, which detected a false signal. To do this, the register 13 is transmitted through the multiplexers 16 and 17 from the register 14 to the address Ag (m) for reading from the memory block 3 of the information word of the initial vertex of the graph corresponding to the new component. ty through multiplexer 25 to trigger 27. After this, a new simulation process begins, which is associated with analyzing the behavior and checking the desired input signals of the selected component.

The operation of the device as a whole under the control of the microprogram control unit 1 occurs according to the algorithm in FIG. 4, the steps of the algorithm are commented below.

Step 1, After starting the device (X 1), the next test set is read from memory block 7

(X4. 0) go to step 2 to pass the test, if a false signal is detected (X O go to step 3,

Step 2 After the last test set (Xj 1) has been implemented, the device stops (Y), the message Fit (Yj) is displayed on the display of the display unit 2. If the test is not finished (X 0), the unit is added to the contents of the 6-address counter (Yf ). and go to step 1 dl

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reading and implementation of the next test set.

Step 3. The process of troubleshooting in dialogue mode begins. The display of indication block 2 is highlighted. Diagnostics (Yj) is going on, the multiplexer 16 transmits to register 13 the address of the initial vertex of the AG model found by encoder 30 (t ij) and then the information word is read from this block 3 vertices m AG, corresponding to the output of the object on which a false signal is detected. The resulting word is fixed in register 14 of the vertex (-

Step 4. Begin analysis of the behavior and control with the probe of the input signals of the next component of the object, at the output of which a false signal is detected. The reference value of the E signal at the component output in the trigger 27 (g) is fixed. Remove the attribute Time shift by resetting the trigger 19 (Y). If the transition from the t cycle to the t-1 cycle is performed, removing this characteristic means that the behavior of the component is carried out for the so-called. the previous set in the t- cycle. An address is prepared for reference to the initial vertex of the component graph (10 n) and will be fixed in the register. 13 (Y ,,

Step 5. The information word of the next vertex m AG is read at the address in register 13 from memory block 3 (4) and written to register 14 (Y). If there is no sign of a time shift (X g 0), the reference 26 will be fixed in trigger 26 the value of the signal at input Z (A) found in memory block 7 at) (Yj), then go to step 7. In the case of X g 1, the reference value of signal Z (m) is from the previous clock cycle in step 6.

Step 6. Shifts back in time. Unit (Y) is subtracted from counter 6, then the set corresponding to the preceding cycle (Y,) is read from memory block 7, the reference value of variable Z (m) at the address is found and transmitted to trigger 26 (2). 6 The previous value corresponding to the address of the current typing (Yj).

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Step 7. Determine whether the signal is tested by a probe. If y (tp) 1 (X (, 1), verification is required, proceed to step 11. In the reverse case, the direction rule applies. In the case where the exit direction from the vertex and the exit direction of the simulated path from the graph coincide, Provering is also required and proceeds to step 11. These matches are checked by circuit 18 (on signal X), where the reference value E, taken from trigger 27, and the value

5 Z (m) i taken from the direct trigger code 26, if jb (ha) O (Xd 0), and from the reverse output of the trigger 26 (), if (t) 1 (X g 1). In the case where the exit direction of

0 vertices and from the graph do not match, verification is not required and the modeling process continues. Go to step 8 to determine the address A (t) of the next vertex on the path,

5 Step 8. Determine the address of the next vertex (Y, o, or Y) depending on the direction of the exit from the vertex and write it to register 13 (). The termination check is performed.

0 ways. At zero address A (t) O (), the path is completed and the transition to step 9 occurs. Otherwise, the simulation continues, the transition to step 10.

Step 9. The diagnostic process is complete. The message Fault is localized (Y,) is displayed on the display of block 2, the address of the localized defective component K (t), () is displayed in block 2 for indication, the device stops (Yj),

Step 10, In the case when the probe control of the signal required a shift in the previous clock cycle (X 2 1), the current test set is restored. For this, the address in the counter 6 is incremented by one (5 the set from memory block 7 (Y) is read and transferred to block 8 (Yg) for implementation on the monitored block 12. Symptom The time shift is removed (Y)

0

five

Return to step 5.

Step 11. If a time shift is not required, tSt) O, (Xp 0), the display of the display unit 2 gives an indication to the operator for the next session with the probe, the words Put probe (enter the address of the chip K (t) (Y) together with the N (m) number of its contact (.), the Device pauses - 5 seconds to wait for the operator to proceed. Go to step 15,

Step 12. If a shift in time is required, T (t) 1 (Xg 1), a transition to the previous clock is made. That is, t.-1. transferred to storage in register 23 (Yg)

Step 13, Returns 15 to the set corresponding to the test segment. To do this, cyclically unit (Y) is subtracted from counter 6 and memory block 7 is read (Y),

It is necessary to enter and check that. (, Y) If the address-A d (ha) is zero (X7 l) i the fault is localized, since the control point Z (m) corresponds to the primary input of the object under test 12, go to step 17 in order to achieve the result of the diagnosis; Otherwise, the process of modeling a new component begins by going to step 4,

Step 17, The diagnostic process is complete. On the display of block 2, the message Fault is localized (Y) is displayed, the address K (t) of the component under consideration () and the number of its defective input contact are also displayed in block 2 for indication

until the start of seg-20 N (m), () is found. The stopping device (XD 1) in some cell, memory block 7.

Step 14, The test is carried out cyclically by reading from the block 7 memory sets (Y-,), giving them to block 12 (Yg) and then incrementing the address counter 6 (Yy), starting with the address found in step 13 recruitment and finishing with the formula of the invention

A device for monitoring and diagnosing digital blocks containing a firmware control block, a test information memory block, an indication block, a logic probe, a count collector whose address is transmitted to the address storage, a comparison block, an input driver, an encoder, a register and PtlTH element, with the first, second, third and fourth outputs of the firmware control block

40

register 23, the sign of the end of this process is the coincidence of the addresses in the counter 6 and register 23 (x 1), then set

the sign Shift in time (Y.,) pro-35 o of Dineny, respectively, the transition to step 11 proceeds to give an indication to the operator.

Step 15 After the device is started by pressing the button 10, the reference signal of the reference point Z (in) stored in trigger 26, and the real signal found with the probe and fixed in trigger 28 (Yj), is compared in block 18 If these signals coincide ( ) the modeling process continues: on this way, the transition to step 8 takes place. If these signals do not match, t, e, if a false signal is detected with the probe, the transition to modeling and checking the next component occurs, the output of which is connected to this test point with a point where a false signal is detected (go to step 16),

Step 16. Select the address of the AT (s), the initial vertex of the graph representing the new component, to the input signals modeler, the register and the PtlTH element, and the second, third, and fourths of the microprogram block.

addition and subtraction of the counts that control the inputs of the test information module; the information inputs of the kit with the outputs of the test memory block of the test tool; the first group of outputs; the group of inputs of the block;

45 with a group of inputs

connections to the outputs of the block, the second group of the gistra is connected to the input of the first input signals,

50 that form a disconnection group for connecting monitored blocks., The unit cd compares the encoder's connections and the element the course of the address counter by the external input of the memory block}, whose output standards and output elements are connected respectively

55

It is necessary to enter and check that. (, Y) If the address-A d (ha) is zero (X7 l) i the fault is localized, since the control point Z (m) corresponds to the primary input of the object under test 12, go to step 17 in order to achieve the result of the diagnosis; Otherwise, the process of modeling a new component begins by going to step 4,

Step 17, The diagnostic process is complete. On the display of block 2, the message Fault is localized (Y) is displayed, the address K (t) of the component under consideration () and the number of its defective input contact are also displayed in block 2 for indication

Claims (1)

Invention Formula A device for monitoring and diagnosing digital blocks comprising a firmware control block, a test information memory block, an indication block, a logic probe, an address counter, a comparison block, a transmitter o Dinen respectively input signal encoder, encoder, register and PtlTH element, with the first, second, third and fourth outputs of the firmware control block with entrances adding and subtracting the address counter, the control inputs of the memory block of test information and the register, whose information inputs are connected to the outputs of the test actions of the memory block of test information, and the first group of outputs with the first group of inputs of the comparison block, the second group of inputs of which is a group device inputs for connection to the outputs of the monitored block, the second group of outputs of the register is connected to the inputs of the input signal generator 1, the outputs of which form a group of outputs of the device for connection to the inputs of the monitored blocks., the group of outputs of the comparison block is connected to the inputs of the encoder and the ILI element the input of the test memory block},; the output of the reference reactions of which and the output of the OR element are connected respectively nineteen and the second by inputs of the logic conditions of the firmware control unit, the initial setup input of which and the installation input of the counter are connected to the installation input of the device, the fifth output of the firmware control unit is connected to the control input of the display unit, and the third input of the logic condition to the input starting the process of monitoring the device, the logic probe input is connected to the control points of the monitored unit, characterized in that, in order to increase productivity by reducing the volume of the ru It contains an object model memory block and a control point analysis block consisting of three registers, five multiplexers, two comparison circuits, five triggers, a switch and a zero decoder, with the information input and output of the first register connected to the output the first multiplexer and the address input of the memory block of the object model, the control input and output of which are connected respectively to the sixth output of the firmware control block and the information input of the second register, the first group The outputs of which are connected to the group of information inputs of the second multiplexer, the group of outputs of which is connected to the group of inputs of the decoder zero and the first group of information inputs of the first multiplexer, the second group of information inputs of which are connected to the group of outputs of the encoder, are first connected to the second with the first and second information inputs of the switch, the output of which is connected to the information input of the ind. one W 258020 the outputs of the third and fourth multiplexers are connected respectively to the first and second inputs of the first comparison circuit, the first and second information inputs of the third multiplexer are connected respectively to the first and second outputs of the first trigger, the first and second information inputs of the fourth multiplexer are connected respectively to the outputs of the second and third flip-flops, the information inputs of the first and second flip-flops are connected to the output of the fifth multiclexer, the information and control inputs of which are connected Respectively with the outputs of the test actions of the memory block of the test information and the third bit BE of the second register, the information input of the third trigger is connected to the output of the logic probe, and the synchronous input and the reset input of the fourth trigger are connected to the device diagnostics start, the first input of the second circuit comparison is connected to the output of the address counter and to the information input of the third register, the output of which is connected to 30 by the second input of the second comparison circuit, the output of which, the outputs of the fourth and fifth triggers, the decoder zero, the first comparison circuit and the second group of outputs of the second register 35 are connected to a group of inputs of the logic conditions of a firmware control unit, the outputs of which group are connected to the control inputs of the switch, the first, second and third registers, the first, second, the third and fourth multiplexers, the first and second setup inputs of the fifth trigger, the sync inputs of the first and second triggers, and 45 the primary input of the fourth trigger. 20 25 Indication Fault localized Indication table 2 Starting the control process. Test completed. Beginning of the test segment. A false signal was found. Start the troubleshooting process Found the desired input set Sign of the zero address Sign of the shift in time T (t Sign of inversion (t) Sign of check (t) Coincidence of signal values Symptom A time shift was made. Reference value Initial setting 86lM16)  " great el.b i 8SA.5 AML BSA.8 BSnf In 6l.1 with in Sj -n  Yag {The end Editor N.Rogulich Compiled by I. Khazov Tehred N. Glushchenko Order 2675 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 , "-, s - h ..- - - - -. -. - - - - -. - - - - - - - ---- - -. - - -: - -. Production and printing company, Uzhgorod, Projecto st., 4 Fi & M Proofreader I. Muska