JPH03158972A - Simulator - Google Patents

Abstract

PURPOSE:To highly precisely detect a break point and to interrupt simulation at necessary timing by detecting the break point by setting the break point in accordance with the variation of the prescribed number of times of a bit pattern. CONSTITUTION:A variation detecting means 11 to detect the variation of the bit pattern during the simulation and a comparing means 10 to compare the detected variation of the bit pattern with the set bit pattern are provided. Then, the setting of the break point to interrupt the simulation is set in accordance with the variations of the prescribed number of times of the bit pattern of a binary signal, and the variation of the bit pattern during the simulation is detected, and every time it is detected, it is compared successively with the set bit pattern, and when all compared results coincide, the break point is detected. Thus, the break point by a micro pulse comes not to be misdetected, and detecting precision is improved, and the simulation can be interrupted at the necessary timing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a simulator that simulates a circuit under test such as a logic circuit and detects defective parts thereof.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional simulator disclosed in, for example, Japanese Unexamined Patent Publication No. Sho 62-156739. In the figure, 3 is a CPU, and a key manual device 2 and a display device 1 are connected to the CPU 3.

The display device 1 graphically displays the state of input/output signals of each gate of a circuit under test (not shown) such as a logic circuit when performing reverse tracing.

Also, from the key manual device 2, break points and signal names are set when performing reverse tracing. Also C
The PU 3 includes, via a path line 13, a storage module 4 that stores results during simulation, an event processing module 5 that performs simulation for each gate, a backtrace module 6 that performs reverse tracing from set breakpoints, and a display module. 7. A breakpoint detection module 8 for detecting whether a specified breakpoint has been reached and a state restoration module 9 for reading out and restoring the state value stored immediately before from the storage module 4 when performing reverse tracing are connected. ing.

Next, the operation of the conventional simulator configured as described above will be explained. FIG. 5 is a circuit diagram of a logic circuit to be simulated, and this logic circuit has input signals A and B.
, C, and D, and outputs an output signal G. Input signals A and B are applied to an AND gate 20, and the logical product thereof is outputted as an output signal E. The output signal E is applied to the AND gate 21 together with the input signal C, and the logical product thereof is outputted as the output signal F. The output signal F is equal to the input signal A
It is applied to the ND gate 22, and outputs the logical product as the output signal G.

FIG. 6 is a diagram showing the simulation results of the logic circuit, and shows the contents stored in the storage module A. Each signal A at time T=O11, 2, 3, 4,
The states of B, C, D, and G are shown, x'' indicates undefined, and 61'' indicates H level. Here, it is shown that the output signal G becomes "1" at time T=4.

FIG. 7 shows the occurrence of events at each time T when the logic circuit shown in FIG. 5 is successfully simulated. When the signal B changes at time T=1, an event occurs at the AND gate 20, and when the signal B changes at time T=2, an event occurs at the AND gates 20 and 21. Similarly, when signal C changes at time T=3, event 1- occurs in AND gates 21 and 22, and when signal C changes at time T=4, AND gate 22
indicates that an event will occur.

Next, an overview of the operation will be explained. When the input signals A, B, C, and D change to "1" in the logic circuit shown in FIG. 5, the output signal G becomes "1" if the logic circuit is normal. However, as a result of the simulation, if the output signal strength does not become 11", a breakpoint is set on the signal G, and the signal G becomes 1".
”The simulation is interrupted at time T, which should be reached.

When the process is interrupted, the process enters a waiting state for input commands, and the operator interactively sets the input signals of each gate and reverse traces the logic state of the logic circuit. At this time, the state value of each signal is displayed on the display device 1 at each reverse traced time T. The operator can detect a defective location in the logic circuit by specifying the name of the defective signal from the state value and continuing reverse tracing.

FIG. 8 is a flowchart showing the details of the simulation operation of the conventional simulator. Here, a case will be explained using as an example a case where a disconnection occurs between AND gates 20 and 21 in the logic circuit shown in FIG. First, set a breakpoint, for example, at signal G using the key manual device 2. Step 11
00), start the simulation. When “1” is sent to the input signal A at time T=1, the AND gate 20
An event occurs, its simulation is performed (step 11101), and the state of the output signal E becomes undefined.

However, since the output signal E has not changed from its initial value, the event is not propagated, and this is determined in step 1102, and the process proceeds to step 1104. In step 1104, the breakpoint detection module 8 detects whether or not it is a breakpoint, but since it is not a breakpoint at this time, the process returns to step 1101.

Next, when input signal B is set to 1'' at time T=2,
The AND gate 20 event occurs again, and the AND game i.20 is simulated (step 111).
01), the signal E becomes 1". However, to NO gate 2
The input signal E' to 1 remains undefined due to the disconnection therebetween. When 11'' is sent to the input signal C at time T=3, an event of the ND gate 21 occurs, and a simulation of the AND gate 21 is performed (step 11101).
), the output signal F becomes undefined. Since this value has also not changed from the initial value, the event is not propagated (step #102). When the input signal is set to 1'' at time T=4, an event occurs in the ND gate 22, and the AN
A simulation of the D gate 22 is performed (step #101). When the simulation is performed, the output signal G
becomes indeterminate. In this way, at times T=1 to 4, input signals A, B, C, and D change from indeterminate to 1, so each time T
Then, those change values are stored in the storage module 4 (step #l03). When all event processing (step 1101) is completed at time T = 4, the breakpoint detection module 8 stores the bit pattern (breakpoint condition) input from the key human power device 2 at - time, and
Each time an event occurs, the stored bit pattern and the input bit pattern are compared, and if they match, the simulation is interrupted and the process proceeds to the next step 1105 (
Step 1104).

9 to 11 are diagrams showing the display state of the display device during reverse tracing. In step 1105, the input/output state of the AND gate 22 is displayed as shown in FIG.

The operator then inputs the signal name F from the key input device 2 (step 11207). Then, the state restoration module 9 sets the state at time T=3, the bank trace module 6 obtains the ND gate 21 (step 11108), and the input/output state of the NO gate 21 becomes as shown in FIG. Is displayed. Furthermore, if you input the signal name E' from the key input device 2 in the same way and proceed with the backtrace, a display as shown in FIG. 11 will appear, indicating that the signal E'
It is shown that there is a disconnection between and E'. In this way, the operator can detect a defective location in the circuit by specifying the signal name.

[Problem to be solved by the invention]

However, in conventional simulators, breakpoints are set by bit patterns at a certain time, and the simulation operation is interrupted when information that matches that bit pattern is input. There was a problem that a breakpoint could be detected due to a minute pulse, making it impossible to interrupt the simulation at the necessary timing.

This invention was made to solve the above problems, and by setting breakpoints by changing the bit pattern a predetermined number of times, breakpoints can be detected with high accuracy and simulation can be interrupted at the necessary timing. The purpose is to provide a simulator that can.

[Means to solve the problem]

The simulator according to the present invention includes: a breakpoint setting means for setting a breakpoint by a predetermined number of changes in a bit pattern; a change detection means for detecting a change in a focus pattern during simulation; and a comparison means for comparing with the bit pattern,
A breakpoint is detected when the comparison results match a predetermined number of times.

[Effect]

In this invention, a breakpoint for interrupting the simulation is set by a predetermined number of changes in the bit pattern of a binary signal, a change in the bit pattern during simulation is detected, and each time a change in the bit pattern is detected, the set focus pattern is set. are compared in order, and a breakpoint is detected when all comparison results match. This prevents false detection of breakpoints due to minute pulses, improves detection accuracy, and allows simulation to be interrupted at the required timing.

〔Example〕

Hereinafter, the present invention will be described in detail based on drawings showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a simulator according to the present invention. In the figure, reference numeral 3 denotes a CPU, and a key input device 2 and a display device 1, which are also used for setting break points, are connected to the CPU 3. The display device 2 graphically displays the input/output state of each gate of a circuit to be measured (not shown) such as a logic circuit when performing reverse tracing. Further, from the key input device 2, changes in bit patterns of break points are inputted a predetermined number of times, and simulation input operations such as setting of each signal during bank tracing are performed. The CllU 3 also has a memory module 4 that stores the results during the simulation and stores them in the bit pattern of the set breakpoint, an event processing module 5 that performs simulation for each gate, and a set A bank trace module 6 performs reverse tracing from the breakpoint set, a display module 7 controls the display device 1, and a display module 7 controls the display device 1 to determine whether a specified breakpoint has been reached, that is, whether or not a predetermined bit pattern has been set. Breakpoint detection module to detect8.
A state restoration module 9 that restores the previously stored state value, a change detection module 11 that detects changes in bit patterns during simulation, and a change detection module that compares the set bit pattern with the bit pattern at the time of change. It is connected to a module 10 and a counter module 12 that counts the number of matches.

Next, the operation of the simulator of this invention will be explained.

First, a predetermined number of changes in the bit pattern are input using the key input device 2, and a break point is set (step #100). For example, the bits of the four signals S, T, U, ■ are all "1" to "l"J".

0", "1" → "1", "0"3 "0", 1" → "1"
, “0′, “ON “0” → “1” 0”, “1” ”]
→ “ON” Set the breakpoint condition to be met when it changes 6 times to “0”, “0” and “1” (4th
(see figure a). When the breakpoint setting is completed, it is stored in the storage module 4, and the event processing module simulates each gate and processes the event (step 11101). Here, a change in the focus pattern is detected by the change detection module 11 (step 11102), and when it has changed, the bit pattern is stored in the storage module 4 (step 1103). Next, the first bit pattern of the breakpoint focus pattern stored in the storage module 4 is read out, and the comparison module 10 compares it with the bit pattern stored in step 1103 (step 11
10), and when there is a match, counter module 1
Step 1111 to increment the count value of 2.
1), request the bit pattern of the next breakpoint 1 (step 11114),
It is determined whether the count value of the counter module 12 has reached the set count (step 11113). When the set count has not been reached, that is, when the bit patterns do not match the predetermined number of times (set count), the process returns to step #101.

Further, if it does not match the bit pattern of the breakpoint in step 11110, the count value of the counter module I2 is reset (step #112).

When the set count is reached, it means that the bit patterns have matched a predetermined number of times, so the breakpoint detection module 8 determines this and interrupts the simulation.
The CPU 3 enters an input waiting state.

Next, display the status of the input and output signals of the gate.Step 11
105), traces backward to the bank trace module 6, and determines the end of the trace in step #106,
If it is not completed, that is, if the defective part cannot be found, specify the input/output signal of the gate (step 1107).
, List the previous state from the storage module 4 Step #10B> Return to step #105 in Step 2.

FIG. 3 is a timing diagram showing the effect of this invention, and four signals S, 1', U, and ■ change as shown in the figure. If a breakpoint is set as before, for example, using only a bit pattern in which all four signals S, T, U, ■ are "1", breakpoints will be set at timings b and C in addition to the timing shown at a in Figure 3. However, in this invention, when the bit pattern changes a predetermined number of times from timing a, that is, when the bit pattern changes during the period shown by the arrow from timing a, those bit patterns and the set bit are detected. Since it is determined that all the patterns match, the number of false detections of bit patterns is reduced.

In this embodiment, the results of the storage module simulation and the breakpoint bit patterns are stored, but the present invention is not limited to this, and these may be stored separately.

Furthermore, in this embodiment, a breakpoint is set by a change in the bint pattern at one timing, but the invention is not limited to this, and the comparison module can be set by AND, O, etc.
By adding arithmetic functions such as R and NOT, breakpoints may be set at a combination of a plurality of timings, thereby allowing the breakpoint to be detected. This allows breakpoints to be detected with even higher precision.

〔Effect of the invention〕

As explained above, in this invention, breakpoints are set by changing the bit pattern a predetermined number of times, and breakpoints are detected thereby.
The break point I can be detected with high precision without being affected by minute pulses generated due to the delay time of C, etc., and the simulation can be interrupted at the necessary timing, which is an excellent effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a simulator according to the present invention, Fig. 2 is a flowchart showing the simulation operation of the simulator, Fig. 3 is a timing chart showing the effects of this invention, and Fig. 4 is the configuration of a conventional simulator. 5 is a logic diagram of the logic circuit that is the circuit under test. FIG. 6 is a diagram showing conventional simulation results. FIG. FIG. 8 is a flowchart showing the simulation operation of a conventional simulator, and FIGS. 9 to 11 are diagrams showing the display state of the display device during reverse tracing. 2... Key human power device 4... Memory module 8.
...Breakpoint detection module IO...Comparison module 11...Change detection module 1
2...Counter module In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Set a breakpoint to stop the simulation in the circuit under test that processes a binary signal, simulate the circuit under test, and when the breakpoint is detected, stop the simulation and perform reverse tracing. , the simulator for detecting a defective location in the circuit under test, further comprising breakpoint setting means for setting the breakpoint at a predetermined number of changes in the bit pattern of the binary signal; A change detection means for detecting a change, a storage means for storing a change in a bit pattern of a set breakpoint, and each time the change detection means detects a change in a bit pattern, the detected bit pattern and the storage means are stored in the storage means. A simulator comprising: a comparison means for comparing the bit patterns obtained by the comparison means; and means for detecting the break point when the comparison result of the comparison means matches the predetermined number of times.