JPH0736732A - Logical simulator - Google Patents

Abstract

PURPOSE:To shorten simulation execution time and to reduce a required file capacity by outputting both an instruction level simulated result and a logical simulated result to a file when they are compared and do not coincide. CONSTITUTION:This simulator is constituted of an instruction level simulated result storage means 5 for storing the instruction level simulated result generated by an instruction level simulator 6 for performing simulation at an instruction set level, a logical simulation execution means 4, a simulated result comparing means 1 for comparing the logical simulated result outputted from the execution means 4 with a value held in the result storage means 5, a comparison instruction means 2 for generating the timing of comparison for the comparing means 1 and a simulated result output means 13 for outputting a logical simulation internal state history from the logical simulation execution means 4 and the instruction level simulated result to an external file 8 at the time of receiving the compared result of non-coincidence from the comparing means 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulator for detecting an erroneous design of a logic circuit by comparing simulation results of an instruction level simulation and a logic level simulation.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional logic simulator includes an instruction level simulator 6 for performing an instruction level simulation, an instruction level simulation result storage file 9 for storing an output value of the instruction level simulation, and a logical simulation. It has a logic simulator 7 to perform, a logic simulation result storage file 10 for storing the output value of the logic simulator, and a mismatch detection means 11 for detecting a mismatch between the files 9 and 10 and outputting a mismatch list. In this configuration, the instruction level simulation result and the logic simulation result are all dropped to a file, the two files are then compared, and the portions where the results do not match are collectively extracted. As such a conventional technique, for example, the IPSJ 37th National Convention Proceedings, "Effective Logic Verification by Ultra-High Speed Logic Simulator (HAL)" (p.
p. 1761 to 1762).

[0003]

As described above, in the conventional logic simulator, after the instruction level simulation and the logic simulation are separately performed to generate a result file, the result files are compared to verify the correctness of the logic. Was. However, since the result data of the logic simulation is generally enormous, the load on the input / output device is increased and it is difficult to perform a large-scale simulation.

[0004]

In order to solve the above-mentioned problems, the logic simulator of the present invention stores an instruction level simulation result generated by an instruction level simulator for simulating an information processing apparatus at an instruction set level. Instruction level simulation result storage means, logic simulation execution means for executing logic circuit level simulation, and logic simulation results output from this logic simulation execution means and values held in the instruction level simulation result storage means And a comparison result indicating that there is a mismatch from the simulation result comparison unit, a comparison instruction unit that generates a timing to be compared for the simulation result comparison unit, and a comparison result indicating that they do not match. Wherein and a simulation result outputting means for outputting an instruction level simulation results from the logic simulation internal state history and the instruction level simulation result storage means from the logic simulation execution means to the external file when.

[0005]

An embodiment of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, in one embodiment of the present invention, an instruction level simulator 6 simulates the operation of the information processing apparatus in units of instruction set level instructions of the information processing apparatus. The instruction level simulation result storage means 5 stores the instruction level simulation result from the instruction level simulator 6. The logic simulation executing means 4 simulates a logic circuit level operation of the information processing apparatus. The simulation result comparison means 1 compares the instruction level simulation result from the instruction level simulation result storage means 5 with the logic simulation result from the logic simulation execution means 4. The comparison instructing means 2 gives the simulation result comparing means 1 a timing to be compared. The simulation result output means 3 simulates the logic simulation internal state history from the logic simulation execution means 4 and the command level simulation result from the command level simulation result storage means 5 when the two results in the simulation result comparison means 1 do not match. Output to the result output file 8.

Next, the operation of the above embodiment will be described.

The instruction level simulation result by the instruction level simulator 6 is transferred to the instruction level simulation result storage means 5 every one instruction. here,
The instruction level simulation result is specifically a set of register group values defined on an instruction set of a computer or the like and provided to software. Since the capacity of the instruction level simulation result storage means 5 is finite,
It is necessary to exchange control signals with the instruction level simulator 6 so that the instruction level simulation result storage means 5 will not overflow. This procedure is shown in Figure 3.
It is FIG.

FIG. 3 is a flow chart of processing when the instruction level simulator 6 side transfers the instruction level simulation result to the instruction level simulation result storage means 5 of the logic simulator 7. The processing from (301) is repeated until the instruction level simulation is completed. First,
It is checked whether there is an interruption instruction from the simulation result output means 3 (302), and if there is an interruption instruction, the instruction level simulation is ended. If not, the state of the instruction level simulation result storage means 5 is checked (303), and if not full, the instruction level simulation result for one instruction is transferred to the instruction level simulation result storage means 5 (304). If the instruction level simulation result storage means 5 is full, it waits until it becomes available. FIG. 4 will be described later together with the description of the operation of the simulation result comparing means 1.

The logic simulation executing means 4 performs logic circuit level simulation and has an internal state of an amount corresponding to the flip-flop of the target circuit. From the internal state, the register value group on the above-mentioned instruction set is transferred to the simulation result comparing means 1.

Further, the logic simulation executing means 4 transfers to the comparison instructing means 2 the value of the register which indicates the timing to be compared by the simulation result comparing means 1 from the internal state. The register for instructing this timing is provided as an internal state of the logic simulation executing means 4 for logic verification, and the timing to be compared can be set in advance. Specifically, if a 1-bit register that becomes "1" is provided in the last clock of the period corresponding to one instruction on the instruction level simulation, the logic verification can be performed in the instruction unit. In addition, if another 1-bit register is provided at the same time so that it becomes "1" for each specific instruction group, a higher-level compound instruction (for example, a shift instruction in an information processing device that does not have a multiplication instruction in its instruction set). And a case where a multiplication instruction is realized by combining an addition instruction).

The simulation result comparison means 1 retrieves the instruction level simulation result from the instruction level simulation result storage means 5 for each instruction and compares it with the logic simulation result in accordance with the timing instructed by the comparison instruction means 2. If the register value groups obtained by both simulations are all the same, the next comparison is sequentially performed after waiting for the timing instructed by the comparison instructing means 2. If a register value group that does not match in both simulations is detected, the logic simulation internal state history from the logic simulation execution means 4 and the instruction level simulation result storage means 5 are detected.
The instruction level simulation result from the above is output to an external file through the simulation result output means 3.
At this time, a signal name (or a flip-flop name) to be output, a simulation period (for example, 100 clocks before a mismatch occurs), and the like can be set in advance in the simulation result output means 3. Further, by setting the interruption of simulation in the simulation result output means 3, the simulation result output means 3 issues a simulation interruption instruction to the instruction level simulator 6 and the logic simulation execution means 4.

FIG. 4 is a flow chart of processing when the simulation result comparison means 1 side receives the instruction level simulation result from the instruction level simulation result storage means 5. The processes below (401) are repeated until the comparison of both simulation results is completed. First, it is checked whether there is an interruption instruction from the simulation result output means 3 (402), and if there is an interruption instruction, the logic simulation execution means 4 ends the logic simulation. If not, the state of the instruction level simulation result storage means 5 is checked (403), and if there is an instruction level simulation result, one instruction is taken out from the instruction level simulation result storage means 5 (404). If the instruction level simulation result storage means 5 is empty, it waits until it is transferred.

In the present invention, the instruction level simulation and the logic level simulation do not always need to proceed simultaneously. For example, at first, only the instruction level simulation is executed, and when a certain instruction is reached, the internal logic state (flip-flop value, main memory content, etc.) is transferred from the instruction level simulator 6 to the logic simulation executing means 4. Good. As a result, it is possible to focus the test only on the part that is really desired to be tested, and the other parts can be executed at high speed only by the instruction level simulation. Note that such a simulation method involving cooperative operation between simulators is a conventional technique and is described in, for example, Japanese Patent Laid-Open No. 63-292337.

In the present invention, the following effects can be obtained by adopting the above-mentioned structure. First, the logic simulation internal state history and the instruction level simulation result can be output as an external file only when both results conflict, not only every clock, and the output file size can be reduced, and the simulation can be performed. The execution speed can be improved. Second, by executing the instruction level simulation and the logic simulation in synchronization with each other, it is not necessary to transfer extra simulation result data. That is, when handing over the simulation results for comparison, they are transferred according to the progress of the comparison process, not all at once.
The simulation scale can be selected without depending on the capacity of the storage area required for delivery. Third,
When both simulation results are inconsistent and subsequent simulations are unnecessary, each simulation can be suspended to save CPU time.

Next, the present invention will be described with reference to the specific examples shown in FIGS.

FIG. 5 shows an example of an instruction code string to be simulated. In the figure, “step” represents the execution order of the instruction code, and “instruction” represents the instruction code. The column to the right of "IC" represents the contents of each register before execution of the instruction code. Here, "I
“C” is the instruction counter, “IR” is the instruction register,
"GR1" is the first general register, "GR2"
Indicates the general register No. 2, “GR3” means the general register No. 3, and “GR4” means the general register No. 4.

FIG. 6 shows an example of the result of executing the logic simulation. In the figure, "time" represents an elapsed clock value when the logic simulation start time is set to 0. The clock mentioned here is based on the logic simulation, and may be further divided on the actual logic circuit.
Further, in FIG. 6, the column to the right of “IC” represents the contents of each register at the simulation time. Here, "BCR" is a register holding the condition code of the branch instruction, "CRRY" is a register holding the carry occurrence information in the arithmetic unit, and "instruction end REG" is "1" at the last clock of each instruction. "Registered to TEST" represents a register that becomes "" and a register that becomes "1" at the last clock of the mode in which both simulation results are compared.

In the concrete example shown in FIGS. 5 and 6, steps 1 to 100 are executed only by the instruction level simulator, and steps 101 to 110 are tested while being simultaneously simulated by the instruction level simulator and the logic simulator. Is assumed to be executed again only by the instruction level simulator. First,
The instruction level simulator 6 sequentially simulates the instructions shown in FIG. 5 from step 1. Then, when the transfer instruction (switch instruction) is executed in step 100, the test mode is entered, and thereafter the logic simulator 7
However, a comparative test of both results is performed while simultaneously simulating. When the test mode is entered, the instruction level simulator 6 prepares the register values (I) shown in the right column of FIG.
(C, IR, etc.) and part of the main storage area are transferred.

When the comparison test starts in the test mode, the instruction level simulator 6 transfers the instruction level simulation result (each register value, etc.) to the instruction level simulation result storage means 5 step by step. An appropriate value should be selected for the capacity of the instruction level simulation result storage means 5 according to the system, but here, for convenience of explanation, it is assumed that the area is already full. For example, if the instruction level simulation result storage means 5 runs out of space when the result of step 105 is transferred, the instruction level simulator 6 interrupts the subsequent simulation, and the instruction level simulation result storage means 5 can store new data. It waits until it becomes (303 in FIG. 3).

On the other hand, the logic simulation executing means 4 performs a logic simulation based on the register value transferred at the head of the test mode, and the simulation result as shown in the right column of FIG. 6 is obtained by the simulation result comparing means 1 and the comparison instructing means 2. Output to. Then, this comparison instruction means 2
Monitors the value of the instruction end REG output from the logic simulation executing means 4, and instructs the simulation result comparing means 1 to compare when the value becomes "1". At time = 8 in FIG. 6, the instruction end REG becomes “1”, indicating that the instruction simulation in step 101 ends. Simulation result comparison means 1
The comparison instruction from the comparison instruction means 2 compares the result of the instruction level simulator 6 with the result of the logic simulation execution means 4.

As a result of this comparison, if a mismatch is detected, the simulation result comparing means 1 notifies the simulation result outputting means 3 of the mismatch. At this time, if it is preset in the simulation result output means 3 that "the two simulations are stopped when they do not match", the simulation result output means 3 causes the instruction level simulator 6 and the logic simulation execution means 4 to stop both simulations. Give instructions. The simulation result output means 3 includes an instruction level simulation result storage means 5 and a logic level simulation execution means 4.
The history of the internal state is received from and output as the simulation result output file 8. The history of this internal state is
The register value and the flip-flop value by each simulation in the step where the mismatch occurs and each step before that. The user can specify, for each item, how many periods to output, etc.

If no mismatch is detected as a result of the comparison by the simulation result comparing means 1, both simulations are continued. After that, when the logic simulation executing means 4 executes the transfer instruction of step 110, the test end REG is "1" as shown at time = 10010 in FIG.
Then, the test mode ends. After that, the logic simulation executing means 4 enters the standby state and waits for the new transfer instruction to enter the test mode. On the other hand, only the instruction level simulator 6 continues the simulation of the instruction after step 111.

In this embodiment, the transfer is triggered by the transfer instruction, but it may be triggered by another trigger, such as when the value of the instruction counter reaches a preset value. Also, although an example of an instruction group composed of a plurality of instructions has been described as an instruction to be subjected to logic simulation, only a single instruction may be used.

[0025]

As described above, the logic simulator according to the present invention can output the logic simulation internal state history and the instruction level simulation result not as every clock but as an external file only when both results conflict. Not only can the output file size be reduced, but the simulation execution speed can also be improved.

Further, by executing the instruction level simulation in synchronization with the logic simulation, it is not necessary to transfer extra simulation result data. In other words, when the simulation results are transferred for comparison, they are transferred not collectively but according to the progress of the comparison process, so that the simulation scale can be selected without depending on the capacity of the storage area required for the transfer. .

Further, when the two simulation results are inconsistent and the subsequent simulations are unnecessary, each simulation is interrupted, so that the CPU time can be saved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a conventional technique.

FIG. 3 is a diagram showing a procedure of transfer processing by an instruction level simulator 6.

FIG. 4 is a diagram showing a procedure of a receiving process by the simulation result comparing means 1.

FIG. 5 is an example of an instruction code string to be simulated.

FIG. 6 is an example of an execution result by a logic simulation.

[Explanation of symbols]

 1 simulation result comparison means 2 comparison instruction means 3 simulation result output means 4 logic simulation execution means 5 instruction level simulation result storage means 6 instruction level simulator 7 logic simulator 8 simulation result output file 9 instruction level simulation result storage file 10 logic simulation result storage File 11 Mismatch detection means

Claims (4)

[Claims] 1. An instruction level simulation result storage means for storing an instruction level simulation result generated by an instruction level simulator that performs an instruction set level simulation of an information processing device, and a logical simulation for executing a logic circuit level simulation. The execution means, the simulation result comparison means for comparing the logic simulation result output from the logic simulation execution means with the value held in the instruction level simulation result storage means, and the comparison for the simulation result comparison means should be made. When the comparison instruction means for generating the timing and the comparison result indicating the non-coincidence are received from the simulation result comparison means, the logic simulation internal state information from the logic simulation execution means is received. A logic simulator having a history and a simulation result output means for outputting the instruction level simulation result from the instruction level simulation result storage means to an external file. 2. The logic simulator according to claim 1, wherein the simulation result output means instructs the instruction level simulator and the logic simulation executing means to suspend the simulation in accordance with a preset condition. 3. The logic simulator according to claim 1, wherein the result of the instruction level simulator is transferred to the logic simulation executing means, and the result is used to continue the simulation in the logic simulation executing means. . 4. The logic simulator according to claim 2, wherein the result of the instruction level simulator is transferred to the logic simulation executing means, and the result is used to continue the simulation in the logic simulation executing means. .