JPH02224141A - Logical simulation system - Google Patents

Abstract

PURPOSE:To obtain a logical simulation system with a simple constitution by organically connecting plural hardware logical simulators through lines. CONSTITUTION:The 1st to 4th hardware logical simulators 1 to 4 are connected to a general purpose computer 5 respectively through a loop connecting device 9. Respective simulators 1 to 4 are provided with logical simulation parts 11, 21, 31, 41, simulation control parts 12, 22, 32, 42 and channel control circuits 13, 23, 33, 43 and the computer 5 is provided with an I/O processor 51, a main storage device 52 and an instruction processor 55. Since plural hardware logical simulators 1 to 4 are connected by the line system connecting device, a large- scale logical system consisting of plural logical devices can be simulated without developing a large-scale hardware logical simulator.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a logic simulation method, and particularly to a logic simulation method with a simple configuration in which a plurality of hardware logic simulators are organically connected.

(Prior Art) Conventionally, this type of logic simulation method has been proposed, for example, in Japanese Patent Laid-Open No. 11459/1982, in which the operation equivalent to that of a target logic device is constructed from a plurality of logic blocks. There is a method in which logic designs are inspected by performing simulations in a short time using a hardware logic simulator.

(Problem to be Solved by the Invention) In the conventional logic simulation method described above, when simulating a large-scale logic system consisting of a plurality of logic devices, a simulation model of the logic system is created and a single hardware logic Since the simulation must be performed using a simulator, there is a drawback that the scale of the hardware logic simulator must be sufficiently large.

(Means for Solving the Problems) A logic simulation method according to the present invention includes a plurality of hardware logic simulators each simulating the logic of a device to be simulated, and a plurality of hardware logic simulators that are connected to these logic simulators via a line. The apparatus includes an execution control means that contains a simulation execution program for simulating and controls the hardware logic simulator to perform logic simulation based on a logic simulation model and a test program.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the logic simulation method according to the present invention, in which first to fourth hardware logic simulators 1 to 4 and a general-purpose computer 5 are connected via a loop connection device 9, respectively. has been done. Each hardware logic simulator includes a logic simulation section 11, 21゜31.41, and a simulation control section 1.
2, 22° 32.42, channel control circuit 13, 23
It is equipped with ゜33.43. In addition, general-purpose computer 5
is equipped with an input/output processing device 51, a main storage device 52, and an instruction processing device 55, and the main storage device 52 stores first to fourth hardware logic simulators 1 to 1 under the control of an operating system 54. A simulation execution control program 53 for controlling 4 is stored.

FIG. 2 shows a configuration diagram of a logical system simulated by this embodiment. Main memory unit (MMU) 20
1, the first arithmetic processing unit (EPU) 203 and the second
The arithmetic processing unit (EPU) 204 of the system controller (
Furthermore, a service processor (SVP) 205 is connected to each of the above devices 201 to 204 via the system control device 202. Also,
FIG. 3 shows the format of information transferred between the first to fourth hardware logic simulators 1 to 4 and the general-purpose computer 5.

A flowchart of the processing of the simulation execution control program 53 in this embodiment is shown in FIG. 4, and a flowchart of the processing when memory reading is performed from the first arithmetic unit 203 to the main storage device 201 is shown in FIG. is shown. The operation of this embodiment will be explained below.

First, the operating system 54 in the general-purpose computer 5 loads the simulation execution control program 53 into the main storage device 52 and starts the simulation execution control program 53.

The activated simulation execution control program 53 performs the processing shown in FIG. Directly process 4
01), the logic simulation model 6 stored in the magnetic disk device is loaded via the loop connection device 9 to the first to fourth hardware logic simulators 1 to 4 that have been initialized (process 402 ).

Here, the first hardware logic simulator 1 is loaded with a logic simulation model that simulates the main storage device 201 in FIG. 2, the second hardware logic simulator 2 is loaded with the system control device 202, and the third The hardware logic simulator 3 includes a first arithmetic unit 2
03, a logic simulation model for simulating the second arithmetic unit 204 is loaded into the fourth hardware logic simulator 4.

Subsequently, the simulation execution control program 53
The test program 7 stored in the magnetic disk device is loaded via the loop connection device 9 into the first logic simulation unit 11 of the first hardware logic simulator 1 that simulates the main storage device 201 (processing 4).
03) In this way, the simulation execution control program 53 simulates the functions of the 5VP 205.

Now, when the loading of the test program is completed, the start of simulation is sent to the first to fourth simulation control units 12 to 42 of the first to fourth hardware logic simulators 1 to 4 via the loop connection bag r19. Upon receiving the instruction (step 404), each hardware logic simulator enters a state of waiting for activation communication from another device. At this time, processing 40
5, interprocessor communication for starting the test program is transmitted to the third hardware logic simulator 3 simulating the first EPU 203 via the loop connection device 9.

Subsequently, the simulation execution control program 53
Waiting for requests from the first to fourth hardware logic simulators 1 to 4 (processing 406), and accepting requests with the data shown in FIG.
If the destination 301 is checked (process 407), and the destination is not the general-purpose computer 5, the received information is transferred to the hardware logic simulator indicated by the destination 301 (process 408); When it recognizes that it is a general-purpose computer, it instructs the first to fourth hardware logic simulators 1 to 4 to end the simulation (409), and the computer is stored in the first to fourth hardware logic simulators. After reading out the simulation results (process 410), editing the simulation results and outputting them to the printer 8 (process 411), all processes are ended.

Next, in FIG. 2 showing the configuration of the logical system simulated by this embodiment, the first arithmetic transmission 203 communicates with other devices by fetching instructions from the main memory 201 and sending data to operands. Communication is broadly classified into reading and writing, and interprocessor communication for starting and synchronizing the second arithmetic unit 204. Here, the main memory! A simulation method for reading data to 201 will be described with reference to FIG.

First, the third logic simulation unit 31 of the third hardware logic simulator 3 (first EPU) generates a memory read command as a result of the simulation (501), and the third simulation control unit 32 performs the following steps.
The memory read command is the transmission data 303, and the transmission destination 301 is the second hardware logic simulator 2 (
SCU) and notifies the general-purpose computer 5 that the sender 302 is the third hardware logic simulator 3 (first EPU) (process 502), and then in process 503, the simulation execution control program that received the notification 53 transfers the received information to the second hardware logic simulator 2 (SCU) that is the transmission destination, performs simulation based on the received information (process 504), and as a result, the first hardware logic simulator 1 (
A command to the MMU') is generated and sent to the general-purpose computer 5 (processing 505).

Thereafter, the received data is transferred to the first hardware logic simulator 1, which is the destination (process 506), and a simulation is performed based on the received information (process 507).
, generate a command to transfer the read data obtained as the simulation result (process 508), and process 50 to send the command to the general-purpose computer.
9) Transfer the received command to the second hardware logic simulator 2 (SCU), which is the destination (process 510), and perform simulation based on the received information (process 511). As a result of this simulation, the third hardware logic simulator 3 (first EPU
) generates a command to send read data to the general-purpose computer 5 (step 512), and sends the received information to the third hardware logic simulator 3, which is the destination.
(first EPU), and based on the received information, the third EPU
By continuing the simulation with the hardware logic simulator 3 (first EPU) (processing 514), the series of memory read processing ends.

Memory write processing can be simulated in the same way as read processing, and inter-processor communication can also be simulated using the third hardware logic simulator 3 (first EP
U) via a general-purpose computer to a second hardware logic simulator 2 (SCU), and further via a general-purpose computer to a fourth hardware logic simulator 4 (SCU).
This can be simulated by transferring information to the second EPU. In addition, a fourth hardware logic simulator 4 (
Memory access from the second EPU) and interprocessor communication to the third hardware logic simulator 3 (second EPU) can be similarly simulated.

By the way, in this embodiment, there are four hardware logic simulators, but it is clear that any number of hardware logic simulators may be used as long as there are two or more. Furthermore, although the hardware logic simulators communicate via a general-purpose computer, it is clear that they may communicate directly. Further, although a loop connection device is used in this embodiment, it is obvious that any line-based connection device may be used.

(Effects of the Invention) As explained above, the present invention provides the following advantages:
This has the effect of simulating a large-scale logic system consisting of multiple logic devices without developing a large-scale hardware logic simulator.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the logic simulation method according to the present invention, Fig. 2 is a block diagram of a logical system to be simulated in this embodiment, and Fig. 3 is a diagram showing the configuration of a logical system to be simulated in this embodiment. FIG. 4 is a diagram showing the format of information, FIG. 4 is a diagram showing the processing of the simulation execution control program in this embodiment, and FIG. 5 is a diagram showing the simulation procedure of memory read in this embodiment. 1.2, 3.4...first to fourth hardware logic simulators, 11.21, 31.41...first to fourth
Logic simulation section, 12,22゜32.42・
...First to fourth simulation control units, 13.23
．． 33.43...first to fourth channel control circuits, 9
...Loop connection circuit, 5...General-purpose computer, 5
1... Input/output processing device, 52... Main storage device, 53
...Simulation execution IIJ# program, 54
...Operating system, 55...Instruction processing device, 6...Logic simulation model, 7...
Test program, 8... Printer, 201... Main storage device, 202... System control device, 203゜20
4... First and second arithmetic units, 205... Service processor. 2'01 3 masters, 1 victory

Claims (1)

[Claims] a plurality of hardware logic simulators each simulating logic for a device to be simulated;
Execution control that is connected to these logic simulators via a line, has a built-in simulation execution program for simulating the logic, and controls the hardware logic simulator for simulating logic based on the logic simulation model and test program. A logical simulation method characterized by comprising: means.