JP2908337B2 - VHDL simulation execution system for multi-process - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VHDL simulation, and more particularly to a VHDL simulation in which simulation models are operated in parallel.

[0002]

2. Description of the Related Art Conventionally, this type of multi-process compatible VH
The DL simulation execution system performs a simulation by operating a plurality of models (VHDL models such as a bus, a printer, a keyboard, and the like) on a machine such as a WS (workstation) or a PC (personal computer) in LSI development or the like. It is used to generate verification and simulation data. An example of a conventional multi-process compatible VHDL simulation execution system is described in Japanese Patent Application Laid-Open No. 07-281925. Multi-process compatible VH described in this publication
The DL simulation execution system is a multiprocessor simulation system that operates a plurality of simulators independently on a workstation to simultaneously simulate processing of a single processor and simulate communication processing between processors.

[0003]

A first problem of the above-mentioned conventional technique is that maintenance is not easy and portability of a VHDL program in diversion development is poor.

[0004] The reason is that the simulation procedure is shown directly using the description format of VHDL, and the program configuration depends on the external interface specific to the target unit to be inspected in the simulation.

A second problem is that a multi-process (parallel execution of a plurality of models) cannot be easily simulated. The reason for this is that a function related to multi-process management when input data (output signal to an LSI whose function is to be verified) is changed in parallel in model units is not considered.

It is an object of the present invention to provide a VHDL simulation system for easily operating a plurality of simulation models in parallel, to easily create a multi-process simulation scenario, and to provide a VH with high reusability.
It is to provide a DL simulation system.

[0007]

According to a first aspect of the present invention, there is provided a VHDL simulation execution system for a multiprocess.
A means for converting a simulation execution procedure expressed in an intermediate language into object data and executing a VHDL simulation by processing the object data is provided.

A second multi-process compatible VHD of the present invention
The L simulation execution system has a built-in multi-process control kernel that can manage the simulation model to be controlled on a task basis, defines a kernel independent of each simulation model and an interface between the simulation models, and logically parallels multiple simulation models. Means for operating is provided.

A third multi-process compatible VHD of the present invention
The L simulation execution system (a) translates the VHDL source code and executes a simulation.
L code execution means, (b) an input device for giving an execution instruction to the VHDL code execution means, and (c) the VHDL code execution means.
A display device for displaying an execution result of the HDL code execution means, and (d) a VHDL program describing a simulation execution procedure and data, wherein a specific operation of the VHDL code execution means is described based on an object code. VHDL simulation means to be determined; and (e)
An intermediate language program storage device for storing a scenario described in the intermediate language of the simulation,
(F) storing the intermediate language program storage device in the VHDL
An intermediate language analysis unit that converts the data into a data format that can be read by a simulation means and generates the object code, and (g) an object data storage device that stores the object code.

[0010] A fourth multi-process compatible VHD of the present invention.
In the L simulation execution system, the VHDL simulation means may include: (a) a target unit to be simulated; (b) a model library for providing an operation model of a peripheral environment connected to the target unit; S that gives an operation instruction to the model library
A P (simulation provider) unit; (d) an object data table which is a data area for storing object codes; and (e) data are sequentially taken out from the object data table.
SG to be transferred to P (Simulation Provider)
A (simulation generator) section; (f) a model setting register for temporarily storing parameter information for the model library among data from the SG (simulation generator) section; A model execution register for temporarily storing an execution instruction for the model library among the data from the (generator) section; and (h) storing the object data from the object data storage device into the S.
Transfer to G (Simulation Generator) part,
And an SA (Simulation Activator) unit for sending a simulation clock to the SG (Simulation Generator) unit to control the SG (Simulation Generator) unit;
An A (simulation activator) unit and a simulation management unit that manages the SG (simulation generator) unit.

A fifth multi-process compatible VHD of the present invention
In the L simulation execution system, the SA (simulation activator) unit includes: (a) an IPL (initial program loader) unit for reading object data from the object data storage device and delivering the object data to the SG (simulation generator) unit;
(B) an RTM (real-time monitor) for controlling and monitoring the execution state of the SG (simulation generator); and (c) the RTM (real-time monitor).
A CG (clock generator) section for providing a clock serving as a simulation clock to the section, (d) the CG (clock generator) section, and the RTM
A (real-time monitor) section and an RR (reset routine) section for performing initialization processing at startup with respect to the IPL (initial program loader) section.

A fifth multi-process compatible VHD of the present invention
In the L simulation execution system, the model library interprets (a) a model function that provides an operating environment for the target unit and (b) an execution instruction from the SP (simulation provider) unit, and converts the model function. A driving model driver.

[0013]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG.
The multi-process compatible VHDL simulation execution system of the present invention translates a VHDL code and executes the VHDL code.
DL code execution means 11 and VH for performing VHDL simulation by loading object data
DL simulation means 12, an intermediate language analyzing unit 13 for generating object data, a display device 14 such as a display, and an input device 15 such as a keyboard and a mouse.
And an object data storage device 16 for storing object data, and an intermediate language program storage device 17 for storing an intermediate language.

The VHDL code execution means 11 is provided for the input device 1
5, and monitors command input from the user. When detecting "start of simulation", VHDL
The reading and execution of the VHDL simulation means 12 programmed in the step (1) are started.

The VHDL simulation means 12 loads object data from the object data storage device 16 and simulates the object data.
The VHDL code execution means 11 notifies the DL code execution means 11 and displays it on the display device 14.

The object data in the object data storage device 16 is converted from an intermediate language program indicating a simulation scenario stored in the intermediate language program storage device 17 by the intermediate language analysis unit 13 in advance into object data. It was done.

Next, the detailed configuration of the VHDL simulation means 12 will be described. FIG. 2 is a block diagram showing details of the VHDL simulation means 12. Referring to FIG. 2, VHDL simulation means 12
Is a simulation management unit 21 that manages the entire simulation system, an SA (simulation activator) unit 22 that controls multi-processes, and an SP that gives specific instructions to each simulation model in the model library 25. (Simulation provider) unit 24, SA (simulation activator) unit 22, and SP (simulation
An SG (Simulation Generator) unit 23 acting as an arbitrator between providers 24, a model library 25 as a collection of simulation models, a target unit 26 to be verified, and object data converted into internal parameters. It has an object data table 27 for storing, a model setting register 28 for temporarily storing settings to be given to the simulation model, and a model execution register 29 for temporarily storing commands issued to the simulation model.

The simulation management unit 21 is located at the top of the simulation system,
It is started first by the code execution means 11 and issues a start request to the SA (Simulation Activator) unit 22 or the SA (Simulation Activator)
Unit 22 and SG (Simulation Generator)
A fatal error from the unit 23 is detected.

The SA (Simulation Activator) unit 22 reads out object data from the object data storage device 16 and transfers it to an SG (Simulation Generator) unit 23 together with a synchronous clock.

SG (Simulation Generator)
The unit 23 converts all the object data into the object data table 27 after converting them into internal parameters, and stores
When a simulation is permitted from the A (simulation activator) unit 22, the object data is read from the object data table 27 in units of one instruction in synchronization with the clock supplied from the SA (simulation activator) unit 22, and SP (Simulation provider) unit 24.

The SP (simulation provider) unit 24 temporarily stores the received object data in the model setting register 28 if it is a set value, and sets it in the model execution register 29 if it is an execution command. Generate.

The model library 25 is connected to an SP (simulation provider) unit 24 via an asynchronous interface. When an event is detected, the model library 25 reads a set value, executes a command, and communicates with a target unit 26 which is a simulation target. Control or monitor the interface.

Next, the detailed configuration of the SA (Simulation Activator) unit 22 will be described. FIG.
FIG. 3 is a block diagram illustrating details of an SA unit 22. Referring to FIG. 3, the SA (simulation activator) unit 22 includes an RR (reset routine) unit 31 for performing initialization processing of a simulation system, a CG (clock generator) unit 32 for generating an internal clock, and a multiprocessor An RTM (real-time monitor) unit 33 serving as a management kernel and an IPL (initial program loader) unit 34 for taking in object data when the system starts up are provided.

An RR (reset routine) unit 31 monitors a reset signal from the simulation management unit 21. When a reset is detected, another CG (clock generator) unit 32, an RTM (real-time monitor) unit 33,
An IPL (initial program loader) unit 34 is notified.

The RTM (real time monitor) unit 33
Based on the basic clock supplied from the CG (clock generator) unit 32, the internal clock for performing the simulation is output to the SG (simulation generator) unit 23 by multiplying or dividing the frequency. Further, the RTM (real-time monitor) unit 33 and the SG (simulation generator) unit 23 are connected by an execution control interface, and the logical management unit in the SG (simulation generator) unit 23 through this interface. Take control of a task.

The IPL (initial program loader) 34 reads the object data in the object data storage device 16 at the time of initialization, and transfers it to the SG (simulation generator) 23 in synchronization with a clock.

Next, the detailed configuration of the SP (simulation provider) unit 24 will be described. FIG. 4 is a block diagram showing details of the model library 25. Referring to FIG. 4, the model library 25 includes model drivers 411 to 41n for calling the functions of the respective simulation models, and model functions 421 to 42n, which are the simulation model bodies.

Each of the model drivers 411 to 41n includes an SP
It is called by a function call from the (simulation provider) unit 24, and returns an operation result if necessary.

Each of the model functions 421 to 42n
Are connected to the model drivers 411 to 41n by a simulation control interface called an SG-interface, which transmits and receives simulation data and outputs an output signal to the target unit 26 connected through an external interface. The drive of the (model functions 421 to 42n to the target unit 26) or the input signal (the target functions 26 to the model functions 421 to 42n) is checked.

Next, the operation of the present invention will be described with reference to FIGS.

First, the procedure of the VHDL simulation is represented as a program (hereinafter referred to as SG-program) in an intermediate language (SGL = Simulation Generator Script Language), and is given to the intermediate language program storage device 17. This SG-program is supplied to the intermediate language analysis unit 13, converted into object data, and stored in the object data storage device 16.
On the other hand, the VHDL code execution means 11 starts the VHDL simulation means 12 and starts the VHDL simulation according to an instruction from the input device 15. The VHDL simulation means 12 reads object data stored in the object data storage device 16 prepared in advance, and executes a VHDL simulation. The result of the simulation, the error status, and the like are given to the VHDL code execution means 11 and displayed on the display device 14 at an appropriate time.

The detailed processing contents of the VHDL simulation means 12 will be described below. The activation request from the VHDL code execution unit 11 is first given to the simulation management unit 21 and the SA (simulation
An instruction is issued to the (activator) unit 22 to start preparation for simulation. SA (simulation
The (activator) unit 22 initializes each internal function block, and starts reading object data from the object data storage device 16.

The read object data is S
The data is transferred to a G (simulation generator) unit 23, and the SG (simulation generator) unit 23 stores the transferred object data in an object data table 27. When all transfers are completed, SA
(Simulation activator) unit 22 issues a simulation start permission to SG (simulation generator) unit 23.

Then, the SG (Simulation Generator) unit 23 extracts and analyzes the object data in the object data table 27 one by one in synchronization with the clock supplied from the SA (Simulation Activator) unit 22. . The analyzed data is composed of model parameter data and model call data. The model parameter data is stored in the model setting register 28 of the SP (simulation provider) unit 24.
The model call data is written into the model execution register 29, respectively.

The clock supplied from the SA (simulation / activator) unit 22 includes a simulation clock and an instruction clock.
There are different types. The simulation clock is used for analyzing the model call data, and the instruction clock is used for analyzing the model parameter data.

When data is written to the model execution register 29, the SP (simulation provider) unit 24 refers to the contents and instructs the model library 25 to drive the model. And model library 2
Reference numeral 5 sets input conditions (output signals to the target unit 26) and verifies output results (input signals of the model library 25) for the target unit 26 as given.

Note that a plurality of model parameter data and model call data exist corresponding to the models in the model library 25 and are completely independent. Therefore, there is no interdependency between the models in the model library 25, and a parallel operating environment is provided.

If the model library 25 detects an error, the error is transmitted to an SP (simulation provider) unit 24, and further, error information is given to an SG (simulation generator) unit 23. The SG (Simulation Generator) unit 23 transmits an error code to the simulation management unit 21, and the simulation management unit 21 issues a display request to the VHDL code execution unit 11 as necessary.

Next, detailed processing contents in the SA (simulation activator) unit 22 will be described below. A simulation preparation request from the simulation management unit 21 enters an RR (reset routine) unit 31 and a CG (clock generator) unit 32 and an IPL.
(Initial program loader) section 34 is also transmitted.

Then, a CG (clock generator) unit 32 sends a basic clock for determining a simulation execution cycle to an RTM (real-time monitor) unit 33.
Start to put out. Further, the IPL (initial program loader) unit 34 starts loading the object data from the object data storage device 16 and transfers the object data to the SG (simulation generator) unit 23.

If an error occurs at this time, the error is notified to the simulation management section 21.

When the loading operation of the object data is completed, the IPL (initial program loader) unit 34 waits for the initialization of the SG (simulation generator) unit 23 to be completed, and prepares for the simulation of the SG (simulation generator) unit 23. Is completed, the RR (reset routine) unit 31 is notified that the preparation for executing the simulation is completed.

The RR (reset routine) unit 31
An instruction is issued to the M (real-time monitor) unit 33 to start the simulation, and the RTM (real-time monitor) unit 33 takes over and manages the subsequent processing. The RTM (real-time monitor) unit 33 starts supplying a simulation clock and an instruction clock created based on the simulation basic clock to an SG (simulation generator) unit 23,
The execution permission of the object data is issued to the SG (simulation generator) unit 23.

When the simulation starts, the RTM
The (real-time monitor) unit 33 monitors the execution status of the multi-process of the SG (simulation generator) unit 23 in management units called tasks. A task has a one-to-one correspondence with a normal model.

From the RTM (real-time monitor) unit 33 to the SG (simulation generator) unit 23,
The execution state of each task is controlled through a task management interface. Conversely, an SG (simulation generator) unit 23 to an RTM (real-time monitor) unit 3
3 is notified of the task status. An interface called a system call is provided from the SG (simulation generator) unit 23 to the RTM (real-time monitor) unit 33, and each task can arbitrarily enter a sleep state or be activated for another sleeping task. Issue requests.

If a fatal logic error occurs inside the SG (simulation generator) unit 23, or if an abend (fatal error) occurs in the SP (simulation provider) unit 24, the SG If the (simulation generator) unit 23 detects the signal, an SG (simulation generator)
The unit 23 generates a system call called an abend request, and the RTM (real-time monitor) unit 33 sends a signal to stop the simulation to the simulation management unit 21 to notify that the simulation system is unstable.

Next, detailed processing contents in the model library 25 will be described below. The model library 25 usually has a plurality of models corresponding to the target unit 26. Each model includes model drivers 411 to 41n and model functions 421 to 42n, and is connected to each other by an interface called an SG-interface. SP (simulation provider)
When an operation command is issued to a certain model from the unit 24, the model driver 411-41n converts the operation command into an SG-interface and transmits the processing contents to the model functions 421-42n. Is output. Similarly, the data input from the target unit 26 to the model functions 421 to 42n are similarly notified to the model drivers 411 to 41n through the SG-interface and are processed as appropriate.

[0048]

As described above, the first effect of the present invention is that, by simply preparing a simulation scenario as an SG-program, the model can be arbitrarily operated in parallel to realize the function verification of the target. That is, the number of steps for verification can be reduced. The reason is that after the SG-program is converted into object data, the model parameter data and model call data that can be set for each model are set in each register in synchronization with the simulation clock and the instruction clock, and are completely independent. This is because each model is configured to be driven.

The second effect is that, since the simulation scenario can be converted into a text file, it can be easily managed as a document, and the number of steps in diverting can be greatly reduced. The reason for this is that a method is provided in which the operation of each model is determined by the SG-program, and the object data resulting from the analysis is loaded to perform a simulation.

A third effect is that models can be relatively easily incorporated / removed, and various problems occurring in parallel operations such as waiting between models can be easily dealt with. The reason is that by introducing the concept of tasks in the management unit of each model, information specific to the model is hidden, while a kernel for multitask management is provided so that each task can be managed centrally. This is because the processing related to the multi-process control is separated from the inherent processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a VHDL simulation means of FIG. 1;

FIG. 3 is a block diagram showing details of an SA unit in FIG. 2;

FIG. 4 is a block diagram showing details of a model library shown in FIG. 2;

[Explanation of symbols]

 Reference Signs List 11 VHDL code execution means 12 VHDL simulation means 13 Intermediate language analysis unit 14 Display device 15 Input device 16 Object data storage device 17 Intermediate language program storage device 21 Simulation management unit 22 SA (Simulation Activator) unit 23 SG (Simulation generator) ) Unit 24 SP (simulation provider) unit 25 model library 26 target unit 27 object data table 28 model setting register 29 model execution register 31 RR (reset routine) unit 32 CG (clock generator) unit 33 RTM (real-time monitor) unit 34 IPL (Initial Program Loader) Unit 411-41n Model Driver 421-42n Model Function

Continuation of the front page (56) References JP-A-7-281925 (JP, A) JP-A-7-129653 (JP, A) JP-A-7-192034 (JP, A) JP-A-4-115330 (JP) JP-A-8-227367 (JP, A) JP-A-5-258002 (JP, A) R. Cyre, et al., "Gen e-rendering VHDL Models from Natural Language Descriptions", European Design Automation Conference, 1994, p. 474-479 (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 17/50 G06F 11/28 340 JICST file (JOIS)

Claims (6)

(57) [Claims] 1. A multi-process compatible VHDL simulation execution system, comprising: means for converting a simulation execution procedure expressed in an intermediate language into object data and executing a VHDL simulation by processing the object data. 2. A multi-process control kernel capable of managing a simulation model to be controlled in a task unit, and an interface between the simulation model and a kernel independent of each simulation model is defined.
A multi-process compatible V having means for logically operating a plurality of simulation models in parallel.
HDL simulation execution system. 3. VHDL code execution means for translating VHDL source code and executing simulation.
(B) an input device for giving an execution instruction to the VHDL code execution means, (c) a display device for displaying an execution result of the VHDL code execution means, and (d) a description of a simulation execution procedure and data. VHDL
A program, based on the object code,
VHDL that defines the specific operation of the HDL code execution means
Simulation means, (e) an intermediate language program storage device for storing a scenario described in a simulation intermediate language, and (f) converting the intermediate language program storage device into a data format readable by the VHDL simulation means. A multi-process-compatible VHDL simulation execution system, comprising: an intermediate language analysis unit that generates the object code; and (g) an object data storage device that stores the object code. 4. The VHDL simulation means,
(A) a target portion to be simulated;
(B) a model library for providing an operation model of a peripheral environment connected to the target unit, (c) an SP (simulation provider) unit for giving an operation instruction to the model library, and (d) an object code. An object data table, which is a data area for storing the data, and (e) an SG (simulation data) for sequentially extracting data from the object data table and transferring the data to the SP (simulation provider) unit.
(G) a model setting register for temporarily storing parameter information for the model library among data from the SG (simulation generator) unit; and (g) a SG (simulation generator) unit. And (h) transferring the object data from the object data storage device to the SG (Simulation Generator) unit, and An SA (Simulation Activator) unit that sends a simulation clock to an SG (Simulation Generator) unit to control the SG (Simulation Generator) unit; and (i) the SA (Simulation Activator) Multi-process corresponding VHDL simulation system according to claim 3, characterized in that it comprises a simulation management unit for managing the parts and the SG (simulation generator) unit. 5. An SA (Simulation Activator) unit comprising: (a) an IPL (Initial Program Loader) unit for reading object data from the object data storage device and delivering it to the SG (Simulation Generator) unit; b) an RTM (real-time monitor) unit for controlling and monitoring the execution state of the SG (simulation generator) unit; and (c) a CG (CG) for providing a clock serving as a simulation clock to the RTM (real-time monitor) unit. A clock generator) section, (d) the CG (clock generator) section, and the RTM (real-time monitor)
5. The multi-process compatible VHDL simulation execution system according to claim 4, further comprising: a RR (reset routine) section for performing an initialization process at startup with respect to the IPL (initial program loader) section. 6. The model library interprets (a) a model function that provides an operating environment for the target unit, and (b) an execution instruction from the SP (simulation provider) unit, and drives the model function. 6. The multi-process compatible VHDL simulation execution system according to claim 5, further comprising: a model driver that performs the simulation.