JPH07121405A - Simulation system - Google Patents

Abstract

PURPOSE:To reduce the load of a computer and to permit even a complicated system loading plural microprocessors to execute simulation equal to 3 real system by operating an MPU simulator, an I/O model and an I/O monitor by means of a different computer. CONSTITUTION:The MPU simulator 101 simulates the operation of MPU executing a tested program 103 which is read into a memory 104. An input/output simulator 102 simulates the operation of a peripheral equipment as against an input/output signal for the peripheral equipment which is out of the simulated object of the MPU simulator when it exists as the result of the execution/ simulation of the tested program in the MPU simulator. The input/output simulator 102 consists of the I/O model 106 simulating the operation of an input/ output device itself and of the I/O monitor 105 simulating the operation of a bus as against input/output from the MPU simulator and controlling the execution of the I/O model.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation system for simulating software for a device-embedded microcomputer by a general-purpose computer different from a target machine on which the software actually operates to perform a test / debug operation.

[0002]

2. Description of the Related Art In the development of a microcomputer system, hardware and software are developed in parallel after system design. In the development of such device-embedded software, there was a premise that software testing had to be performed before hardware development. Therefore, the software is tested / debugged by using a simulator that simulates the logical equivalent of an actual computer system. For example, MPU of computer and MPU simulating memory part
Testing / debugging is performed by executing computer software using a simulator. Also, M
Input / output instructions in the PU simulator (hereinafter, I / O instructions)
The simulation for was able to test by setting pseudo data, but since it takes time and effort, an input / output model that simulates the control operation of the input / output control unit,
Using an input / output monitor configured to simulate the control of the MPU and the bus line section to control the execution of the input / output model, and an input / output simulator configured to collectively manage the input / output data of each input / output model. , I / O instructions are simulated.

As a conventional technique for supporting the testing / debugging work of such device-embedded software, there is a "simulation system" (Japanese Patent Laid-Open No. 62-274436),
There is a "multiple microprocessor system simulation method" (Japanese Patent Application No. 1-288889).

[0004]

Although the above-mentioned conventional technique can operate independently, the I / O simulator (I / O monitor, I / O model) is attached to the MPU simulator, and M
It was working together with the PU simulator. Therefore, in order to simulate the operation of a system having a plurality of MPUs and a plurality of I / O devices, a plurality of MPU simulators are operated and the synchronization function of the plurality of I / O devices is attached to each I / O simulator. It was necessary to provide the simulators (I / O monitor, I / O model) separately. That is, I / O simulator (I / O monitor, I / O
It is necessary for the modeler to create the synchronization function of a plurality of input / output devices by the number of I / O models attached to each MPU simulator. As the number of simulators increases, the creation work becomes more complicated and difficult. There was a problem.

Further, the above-mentioned conventional technique has a problem that the operation of the simulator is complicated and the efficiency is deteriorated.
Further, although the above-mentioned conventional technique realizes a sequential simulation by calling a function between each of the MPU simulator, the I / O monitor, and the I / O model, the device configuration of the simulation target microcomputer system is changed. There was a problem that the call destination of each function and the calling module had to be modified each time it happened.

An object of the present invention is to provide a simulation method that solves the above problems in the conventional method.

[0007]

In order to achieve the object of the present invention, the simulation method of the present invention is such that a microprocessor unit (hereinafter referred to as MPU) and an MPU simulator for simulating a memory and an input / output device for simulating an input / output device. With an output device simulation unit (hereinafter, I / O model) and an input / output device simulation unit execution control mechanism (hereinafter, I / O monitor) that simulates a signal line group connecting the MPU and one or more input / output devices. It is an input / output simulator (hereinafter, I / O simulator) configured, and includes the above MPU simulator, I / O model,
The means is to perform the simulation by operating the I / O monitor in another computer, connecting these computers through a network, and exchanging data.

Further, in the above method, the MPU simulator, the I / O model, and the I / O monitor are operated in different processes with each other, the processes are connected through a network, and data is transmitted and received to perform a simulation. And In the above method, the I / O monitor is provided with a function of performing synchronization management and interrupt management between the MPU simulator and the I / O model. Further, in the above method, when a plurality of MPU simulators, I / O models, and I / O monitors are operated, a function for performing synchronization management and interrupt management for these is provided for a plurality of MPs.
A means is to have a system bus I / O monitor that simulates a signal line group that connects U and input / output devices.

[0009]

In order to achieve the object of the present invention, the present invention provides MP
By operating the U simulator, I / O model, and I / O monitor on another computer, the load on the computer can be reduced, and even a complex computer system equipped with multiple microprocessors is equivalent to the actual computer system. The goal is to be able to simulate behavior and thus streamline testing / debugging work.

In the above method, the MPU simulator, the I / O model, and the I / O monitor are operated in different processes, so that even a complicated computer system equipped with a plurality of microprocessors is equivalent to an actual computer system. Can be simulated, and in the past, the synchronization function of multiple I / O devices was created by the number of I / O models, but it can be unified into one.
As a result, it is to streamline the test / debug work.

In the above method, the I / O monitor is provided with a function of performing synchronization management and interrupt management between the MPU simulator and the I / O model, so that a complicated computer equipped with a plurality of microprocessors is provided. In the system, it is possible to simulate the same operation as an actual computer system, and in the past, the synchronization function of multiple I / O devices was created by the number of I / O models, but it can be unified into one, and eventually , To improve the efficiency of testing / debugging work.

Further, in the above method, when a plurality of MPU simulators, I / O models, and I / O monitors are operated, a function of performing synchronization management and interrupt management between them is provided between a plurality of MPUs and input / output devices. By providing the system bus I / O monitor that simulates the connected signal line group,
A complex computer system equipped with multiple microprocessors can simulate the same behavior as an actual computer system, and in the past, multiple I / O device synchronization functions were created for each I / O model. Can be unified into one, which in turn makes the testing / debugging work more efficient.

Further, in the above method, the inter-process communication and the inter-computer communication are performed by using socket communication, so that an open system can be realized regardless of the model of the computer, and the device of the simulation target microcomputer system can be realized. Even if the configuration changes, you can dynamically change the simulation call destination simply by changing the data of the other party sent by communication, and you do not need to modify the module, which in turn improves the efficiency of test / debug work. Especially.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a simulator which is a target of the present invention. FIG. 2 is a diagram showing a hardware environment for operating a simulator to which the present invention is applied. For example, referring to FIG. 1, 101 is an MPU simulator, which is an MPU (Micro Processer) for executing the program under test 103 read in the memory 104 in the general-purpose computer.
Unit) to simulate the operation. 10
Reference numeral 2 denotes an input / output simulator. As a result of executing and simulating the program under test 103 in the MPU simulator, if there is an input / output signal to a peripheral device that is not targeted by the MPU simulator, the operation of the peripheral device with respect to the input / output signal. To simulate. The input / output simulator 102 simulates the operation of the input / output device itself and an I / O monitor that simulates the operation of the bus with respect to the input / output signals from the MPU simulator and controls the execution of the I / O model. And 105.

In FIG. 2, reference numeral 206 designates communication paths for connecting a plurality of computers in the development bases, 208, 209 and 210.
Is a general-purpose computer for operating the simulator, and 207 is a storage device connected to the computer. Here, the storage device 207 centrally manages all information such as test data, specifications, programs, etc. created by software development. Further, in the internal configuration of a general-purpose computer connected via a network, the external storage device 205 stores the program under test of the simulation method of the present invention. Memory 2
01 is the external storage device 205 when the system is executed.
An internal storage device for temporarily storing data, programs, etc., such as reading a program under test of a simulation method will be shown. The MPU 203 has a memory 201.
The arithmetic device and the control device for executing the simulation method program read in, the input device 204 is a device such as a keyboard and a mouse for inputting an instruction to be executed by the user, and the display device 202 is a confirmation item for the user. The devices for displaying, etc. are respectively shown.

FIGS. 3, 4 and 5 are diagrams showing respective control flows when an I / O instruction occurs in the MPU simulator according to the embodiment of the present invention. FIG. 3 shows the control flow of the MPU. Shows the control flow of the I / O monitor, and FIG.
The control flow of the / O model is shown respectively. 6 and 7 are views showing the contents of messages exchanged between the MPU simulator and the I / O monitor, and between the I / O monitor and the I / O model.

In this embodiment, an example of what kind of hardware operation is performed when the address value "656" and the register value "28" are set as the I / O instruction in the I / O model "model 1" is used. The present embodiment will be described with reference to FIGS. 3, 4 and 5. However, it is assumed that the computer 208 shown in FIG. 2 is operating an MPU simulator, the computer 209 is operating an I / O monitor, and the computer 210 is operating an I / O model.

When a command is input to the MPU simulator, a reference value is extracted from the input command to indicate how many values of the instruction and the number of clock cycles should be transmitted to the I / O monitor. (Step 3
01, step 302). Next, it is searched whether the extracted instruction is an I / O instruction (steps 303 and 304).

If the input instruction is not an I / O instruction, step 302 is executed. M for I / O command
The PU simulator outputs the bus information corresponding to the I / O instruction to P
It is sent to the I / O monitor as an IO message (step 305). At this time, the MPU simulator does not know the destination, that is, the I / O model for which I / O
Since it is not possible to determine whether it is an O command, nothing is set in the destination in the PIO message and it is transmitted to the I / O monitor. Reference numeral 601 shown in FIG. 6 indicates I / O from the MPU simulator.
It is the content of the PIO message sent to the monitor. For example, 602 indicates the type of message, and here, the message 601 indicates that it is a message regarding an I / O command. “Send” 603 means to send a signal to an external transmission path, and “MPU” 604 means a transmission source. Reference numeral 605 represents a transmission destination, but it is blank here because it is unknown to which I / O model the I / O command is directed. “IO WR” 606 represents the name of the signal line on the actual device, and the signal line is the name of the bus used when register write is performed. “656” 607 represents the address value of the I / O model that executes the I / O instruction, and “28”
Reference numerals 608 respectively indicate address register values.

Next, the I / O which received the PIO message
The monitor determines from within the message whether the PIO message is a transmission or a reply (step 401). If it is transmission, next I / O that manages the contents of the address bus
The map is checked (step 402), the I / O model name of the matching address is set as the destination in the PIO message (step 403), and the PIO message is set to I / O.
It is transmitted to the O model (step 404). FIG. 8 is a diagram showing the contents of the I / O map that manages the contents of the address bus. For example, 609 shown in FIG. 6 is the content of the PIO message transmitted from the I / O monitor to the I / O model. Here, it can be seen from the contents of 801 shown in FIG. 8 that the I / O model that is the target of the input instruction is the corresponding I / O model “model 1” 610.

Next, when the I / O model matching the destination of the PIO message receives the PIO message, I / O model
The O model performs register read / register write processing corresponding to the control line in the PIO message. In the case of register read, the read result is set in the data bus in the PIO message, and the process of step 502 is performed (step 513). In the case of register write, the I / O model performs a hardware operation corresponding to the input / output instruction of the MPU (step 512). If an event occurs while the hardware is operating (step 50)
3), the following processing is performed. The time required for the generated event is generated, and the generated time and the I / O model name are set in the event registration message and transmitted to the I / O monitor (step 504). The time generated here is I / O
It represents the time from when the model receives the PIO message sent from the I / O monitor to when it sends the event registration message to the I / O monitor. Upon receiving the event registration message, the I / O monitor registers the time and I / O model name required for the event set in the event registration message in the event registration table managed by the I / O monitor (step 406). ). When the registration in the event registration table is completed, the event registration message is returned to the I / O model (step 406).

The I / O model that has received the returned event registration message once abandons the processing of the hardware currently operating and returns a PIO message to the I / O monitor (step 502). In the present embodiment, the following will be described on the assumption that an event has occurred in the I / O model "model 1" during the hardware operation. Reference numeral 611 shown in FIG. 6 indicates the content of the event registration message transmitted from the I / O model "model 1" to the I / O monitor, and reference numeral 613 indicates the reply from the I / O monitor to the I / O model "model 1". This is the content of the event registration message. Here, “1” 612 in 611 indicates the time generated in the I / O model “model 1”.

Next, the I / O monitor that has received the returned PIO message determines from the PIO message whether the received PIO message is a transmission or a reply (step 401). If it is a reply, the PIO message is sent. It is returned to the transmission source in the above, that is, the MPU simulator (step 405). Reference numeral 614 shown in FIG. 6 shows the content of the PIO message returned from the I / O monitor “model 1” as an I / O monitor. The content of the PIO message returned from the I / O monitor to the MPU simulator is also the same as 614.

The MPU simulator receiving the returned PIO message counts the number of clock cycles each time one instruction is processed next (step 306) and compares it with the reference value of the number of clock cycles extracted in step 301. (Step 307). If they are not equal as a result of the comparison, the process of step 302 is performed. If they are equal, the periodic message is transmitted to the I / O monitor (step 308). Reference numeral 615 shown in FIG. 6 is the content of the periodic message transmitted from the MPU simulator to the I / O monitor.

The I / O monitor receives the periodic message from the I / O monitor at which an event is currently occurring.
A model exists or an event registration table managed by the same I / O monitor is searched (step 408).
As a result of the search, if there is no I / O model in which an event is currently occurring in the I / O monitor, step 412
Process. If it exists, the number of event occurrence cycles of all the information set in the event registration table is decremented by 1 (step 409).

When the number of event occurrence cycles is subtracted, the number of event occurrence cycles in the event registration table becomes 0 I
The event registration table is searched again for the existence of the / O model (step 410). Number of event occurrence cycles is 0
If there is no I / O model that became
12 processing is performed. The number of event occurrence cycles is 0
If the / O model exists, the I / O model name is set as the destination of the event execution message, and the event execution message is sent to the I / O model (step 41).
1). At this time, the information on the I / O model in the event registration table is deleted. Reference numeral 616 shown in FIG. 6 is the content of the event execution message transmitted from the I / O monitor to the I / O model “model 1”. FIG. 11 is a diagram showing the contents of the event registration table after subtracting 1 from the number of event occurrence cycles. For example, from the contents of 1101 shown in FIG.
The O monitor sets "model 1" 618 as a transmission destination in 616 shown in FIG. 6 and indicates that the event execution message is transmitted to the I / O model "model 1".

I / O that received the event execution message
The model restarts the hardware operation that once abandoned the process in the previous event registration (step 506). I / O
When the hardware operation of the model is completed, an event execution message is returned to the I / O monitor. Here, if an event occurs again in the I / O model during the hardware operation (step 507). ) Similarly sends an event registration message to the I / O monitor,
The time required for the event and the I / O model name are registered in the event registration table in the / O monitor (step 508).
If an interrupt occurs in the I / O model during the hardware operation (step 509), the interrupt registration message is sent to the I
It is sent to the I / O monitor (step 510) and the model name is registered in the interrupt registration table managed by the I / O monitor. When the registration is completed, an interrupt registration message is returned to the I / O model (step 407). In the present embodiment, the following will be described on the assumption that an interrupt occurs in the I / O model "model 1" during the hardware operation. FIG. 10 is a diagram showing the contents of an interrupt registration table managed by the I / O monitor. For example, the content of 1001 shown in FIG. 10 indicates that an interrupt occurs in the I / O model “model 1” during hardware operation. Reference numeral 710 shown in FIG. 7 indicates I / O from the I / O model “model 1”.
The contents of the interrupt registration message sent to the monitor and the contents of the interrupt registration message 711 returned from the I / O monitor to the I / O model "model 1" are shown. Here, the I / O monitor that has received the interrupt registration message 710 has the transmission source “model 1” 712 in the interrupt registration message 710 to “model 1” shown in FIG.
It can be seen that 1002 is set.

When an event occurs in the I / O model, an interrupt occurs, or the hardware operation of the I / O model ends, an event execution message is returned to the I / O monitor (step 511). Reference numeral 617 shown in FIG. 6 is the content of the event execution message returned from the I / O model “model 1” to the I / O monitor. The I / O monitor that has received the event execution message performs transmission / return processing of the event execution message for all the I / O models whose event generation cycle number has become 0 by subtraction.

When the processing is completed, the next I / O model in which an interrupt has occurred is searched or the interrupt registration table managed by the same I / O monitor is searched. Only when there is an I / O model in which an interrupt has occurred, "REQ" indicating that there is an I / O model in which an interrupt request has occurred is set in the control line in the periodic message (step 41).
2).

Next, the MP that is the transmission source of the periodic message
It returns to the U simulator (step 418). Reference numeral 703 shown in FIG. 7 is the content of the periodic message returned from the I / O monitor to the MPU simulator. 1 shown in FIG.
From the contents of 001, the I / O monitor sends a periodic message to M
Before returning to the PU simulator, the control line "R" shown in FIG.
It can be seen that “EQ” 713 is set.

The MPU simulator, which has received the returned periodic message, searches the control line in the periodic message for an interrupt request. If not set, step 302 is performed. When the interrupt request is set, the following processing is performed next.

The MPU simulator is an I which represents an interrupt request.
Send an NT ACK message to the I / O monitor (step 311). At this time, the MPU simulator does not know the destination, that is, the I / O model in which the interrupt has occurred. Therefore, nothing is set to the destination in the INT ACK message, and the I / O monitor sends it. The MPU simulator 704 shown in FIG.
The contents of the INT ACK message transmitted to the / O monitor. Here, it can be seen that nothing is set in the transmission destination 705 in the INT ACK message.

When the I / O monitor receives the INT ACK message, it determines whether it is a transmission or a reply (step 41).
3) If it is transmission, the interrupt registration table managed by the I / O monitor is collated (step 414). As a result of collation, the I / O model in which the interrupt occurred is set as the destination
The I / O model name is set to the destination in the NT ACK message (step 415), and the INT ACK message is transmitted to the I / O model (step 416). Reference numeral 706 shown in FIG. 7 is the contents of the INT ACK message transmitted from the I / O monitor to the I / O model “model 1”. Here, 10 in the interrupt registration table shown in FIG.
01 to the destination “model 1” 7 in 706 shown in FIG.
It can be seen that 07 is set.

When the I / O model receives the INT ACK message, it sends an interrupt withdraw message to the I / O monitor in order to withdraw the interrupt generated in the I / O model (step 505). The I / O monitor 714 shown in FIG. 7 receives the interrupt withdrawal message, which is the content of the interrupt withdrawal message transmitted from the I / O model “Model 1” to the I / O monitor, and manages the interrupt registration table. Delete the information about the I / O model set as the sender of the interrupt withdrawal message from the
Reply to the model. Reference numeral 715 shown in FIG. 7 is the content of the interrupt withdrawal message returned from the I / O monitor to the I / O model “model 1”.

The I / O model receiving the returned interrupt withdrawal message extracts the vector number, sets the vector number in the data bus in the INT ACK message, and returns the INT ACK message to the I / O monitor. (Step 505). I / O monitor is INT AC
When the reply of the K message is received, the transmission / reply is confirmed, and if it is a reply, it is returned to the MPU simulator which is the transmission source. Reference numeral 708 shown in FIG. 7 is the content of the INT ACK message returned from the I / O model to the I / O monitor and from the I / O monitor to the MPU simulator that is the transmission source. For example, from 716 in 708, the I / O model “model 1” extracts “8” as the vector number and
It can be seen that the TACK message is set.

The MPU simulator which has received the returned INT ACK message
The interrupt processing routine corresponding to the vector number set in the data bus in the message is started (step 3
12). After the interrupt processing routine ends, step 3
02 processing is performed.

As described above, in the actual system, the MPU and the I / O device are operating in parallel and are synchronized with each other by the system clock or the like. It works just like the system, but with too fine a period, it adds overhead. In the present embodiment, when the MPU simulator issues a request, other programs cannot be executed until a reply to the request is returned, so that the program under test execution system and the I / O model are operated sequentially and alternately. Synchronize by operating up to the synchronization time.

As described above, by accurately simulating the transition of the internal logic state and replacing the input / output operation with time, the control operation of the computer such as the interrupt control and the bus line control is realized equivalent to the actual environment. be able to.

[0039]

Since the present invention has the processing procedure described above, it has the following effects. MPU
By operating the simulator, I / O model, and I / O monitor on another computer, the load on the computer can be reduced, and even a complex computer system equipped with multiple microprocessors can operate in the same way as an actual computer system. Can be simulated and thus the test / debug work can be streamlined.

In the above method, the MPU simulator, the I / O model, and the I / O monitor are operated in different processes, so that even a complicated computer system equipped with a plurality of microprocessors is equivalent to an actual computer system. Can be simulated, and in the past, the synchronization function of multiple I / O devices was created by the number of I / O models, but it can be unified into one.
As a result, the test / debug work can be made efficient.

Further, in the above method, the I / O monitor is provided with a function of performing synchronization management and interrupt management between the MPU simulator and the I / O model, so that a complicated computer equipped with a plurality of microprocessors is provided. In the system, it is possible to simulate the same operation as an actual computer system, and in the past, the synchronization function of multiple I / O devices was created by the number of I / O models, but it can be unified into one, and eventually , It is possible to streamline the test / debug work.

Further, in the above method, when a plurality of MPU simulators, I / O models, and I / O monitors are operated, the function of performing synchronization management and interrupt management between them is provided between the plurality of MPUs and input / output devices. By providing the system bus I / O monitor that simulates the connected signal line group,
A complex computer system equipped with multiple microprocessors can simulate the same behavior as an actual computer system, and in the past, multiple I / O device synchronization functions were created for each I / O model. Can be unified into one, which in turn makes the test / debugging work more efficient.

Further, in the above method, the inter-process communication and the inter-computer communication are carried out by using the socket communication, so that an open system can be realized regardless of the model of the computer, and the device of the simulation target microcomputer system can be realized. Even if the configuration changes, you can dynamically change the simulation call destination simply by changing the data of the other party sent by communication, and you do not need to modify the module, which in turn improves the efficiency of test / debug work. be able to.

From the above, according to the present invention, a test /
Since the debugging work can be made efficient and the development period can be shortened, the productivity of the embedded microcomputer software can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a simulator to which the present invention is applied.

FIG. 2 is a diagram showing a configuration of a general-purpose computer that operates the present invention.

FIG. 3 is a diagram showing a control flow of an MPU simulator.

FIG. 4 is a diagram showing a control flow of an I / O monitor.

FIG. 5 is a diagram showing a control flow of an I / O model.

FIG. 6 is a diagram showing a format of a message sent / replied between an MPU simulator, an I / O monitor, and an I / O model.

FIG. 7 is a diagram showing a format of a message sent / replied between the MPU simulator, the I / O monitor, and the I / O model.

FIG. 8 is a diagram showing the contents of an I / O map.

FIG. 9 is a diagram showing the contents of an event registration table.

FIG. 10 is a diagram showing the contents of an interrupt registration table.

FIG. 11 is a diagram showing the contents of an event registration table.

[Explanation of symbols]

101; MPU simulator, 102; Input / output simulator, 103; Program under test, 104; Memory,
105; I / O monitor, 106; I / O model, 20
1; memory, 202; display device, 203; CPU, 20
4; input device, 205; external storage device, 301; command input wait, 302; instruction fetch, 303; instruction analysis, 305; I / O instruction simulation, 306; clock cycle number count, 308, cycle generation, 30
9: clock cycle number reset, 311; interrupt acceptance processing, 312: interrupt vector number, 402; collation with I / O map, 404; transmission format transfer, 405; reply format transfer, 406; event registration, 407;
Interrupt registration, 411; Execution of event generation model, 41
2; Interrupt registration acquisition, 414; Collation with interrupt registration table, 416; Transmission format transfer, 417; Reply format transfer, 418; Reply format transfer, 50
2; reply format transfer, 504; event occurrence time registration, 505; interrupt withdrawal, 506; event execution hardware operation execution, 508; event occurrence time registration, 510; interrupt request, 511; reply format transfer, 512; register write processing 513; register read processing, 602; PIO, 603; transmission, 604; M
PU, 606; IO WR.

Front page continuation (72) Inventor Yuji Nagamatsu 1099, Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Incorporated company Hitachi, Ltd. System Development Laboratory

Claims (5)

[Claims] 1. A microprocessor unit (hereinafter referred to as MP
U), and an MPU simulator that simulates a memory, an input / output device simulation unit that simulates an input / output device (hereinafter, I / O model), and a signal line group that connects the MPU and one or more input / output devices. It is an input / output simulator (hereinafter, I / O simulator) composed of an input / output device simulation unit execution control mechanism (hereinafter, I / O monitor), which includes the above MPU simulator, I / O model, and I / O monitor. A simulation method characterized in that a simulation is performed by operating in another computer, connecting those computers through a network, and exchanging data. 2. The simulation method according to claim 1, wherein the MPU simulator, I / O model, and I / O are used.
A simulation method characterized in that monitors are operated in separate processes, and those processes are connected by a network and data is exchanged to perform a simulation. 3. The simulation method according to claim 1, wherein the I / O monitor has a function of performing synchronous management and interrupt management between the MPU simulator and the I / O model. . 4. The simulation system according to claim 1, 2, or 3, wherein when a plurality of MPU simulators, I / O models, and I / O monitors are operated, a plurality of functions for performing synchronization management and interrupt management of these are provided. System bus I / that simulates a signal line group connecting between the MPU and the input / output device
A simulation method characterized by having an O monitor. 5. The simulation method according to claim 1, 2, 3, or 4, wherein socket communication is used for interprocess communication and intercomputer communication.