JP3137094B2 - Simulation method, simulation device, and recording medium therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (CPU) which is different from a target computer and is designed to operate on a target computer.
More particularly, the present invention relates to a simulation method and apparatus capable of simulating process switching (context switch) on a target computer.

[0002]

2. Description of the Related Art A simulation device (hereinafter, also referred to as a simulator) executes a simulation of the operation of a target computer by a host computer having a central processing unit different from the target computer. In a simulator constructed by a host computer, generally, a computer to be simulated, that is, an instruction sequence of a target program operating on the target computer is held as data, and the host computer interprets and executes the instruction sequence of the target program one instruction at a time. Thus, a simulation of the operation of the target computer is executed. That is, since the target computer and the host computer have different execution environments including a CPU and a storage device (memory), the simulator stores a storage area (target memory) simulating the execution environment of the target computer and a CPU register on the host computer. Of the target CPU (CPU of the target computer) at the time of executing the simulation after the area (target register) is secured, and the operation corresponding to each instruction of the target computer is executed in the target memory and the target register during the execution of the simulation. By doing so, the operation of the target computer is realized in a pseudo manner.

However, such a simulation method takes a long time in the process of interpreting the instructions of the target computer by the software of the host computer, so that the execution speed is much slower than the original operation of the target computer. have. Various simulation methods have been proposed to solve such problems and enable high-speed simulation.

For example, Japanese Patent Application Laid-Open No. 6-250874 discloses a simulation function for simulating each instruction of a target computer by a native code of a host computer. Replace each instruction in the instruction sequence with the instruction by the native code of the host computer that calls the corresponding simulation function,
Thereafter, a method of performing a simulation is disclosed. In this method, the simulation itself is executed by the native code of the host computer, and it is not necessary to interpret the target instruction at the time of executing the simulation, so that the simulation can be sped up.

However, Japanese Patent Application Laid-Open No. Hei 6-25087 discloses
In the method disclosed in Japanese Patent Laid-Open No. 4 (1999) -1994, a simulation function corresponding to each instruction of the target computer is called, so that the overhead associated with the call cannot be ignored.
If one instruction in the target computer is converted to the native code of the host computer, the number of instructions may be as large as ten or more in some cases, so that the number of instruction steps as a whole on the host computer increases, and simulation can always be performed efficiently. Do not mean.

Therefore, the present inventor has already disclosed in Japanese Patent Laid-Open No. 10-03 / 1998.
Japanese Patent Application Publication No. 1595 discloses a routine process (a routine process) such as a system call of an OS (operating system) or a runtime library of a compiler which is commonly used by a plurality of programs and is not changed among target programs. Proposed a method of preparing a program (native code version routine processing) corresponding to the routine processing and described in native code of the host computer in advance, and executing the program to simulate the routine processing part. Non-standard processing in the target program (ad-hoc processing)
Is interpreted one instruction at a time by simulation.
Execute. The native code version of the standard processing does not replace each instruction in the target program with one instruction in the native code, but rewrites it in the native code of the host computer to perform the same function as the standard processing in the target computer. It simulates routine processing in the target computer as a whole. Since the program block with a certain number of steps is newly rewritten with native code, the number of steps of instructions in the routine processing of the target program and the routine processing of the native code version is expected to be not much different. At least for the routine processing part, the speed of the simulation can be further increased.

[0007]

In order to speed up the simulation, it is not only necessary to avoid interpreting each instruction of the target program at the time of executing the simulation, but also one of the instructions of the target program. It is effective to make the number of steps of the instruction in the native code of the host computer corresponding to the step as small as possible. From this point of view, a block of the target program is completely replaced by the native code of the host computer so that the routine processing in the target program is replaced with the native code version routine processing in the host computer in the above-mentioned Japanese Patent Application Laid-Open No. 10-031595. It is effective to replace with written blocks. At that time, the block by the native code,
The description can be based on the native architecture (register set or memory model) of the CPU of the host computer without assuming the CPU architecture of the target computer, for example, a register set.

When task switching (context switch) is performed in the target computer, this context switch must be simulated in the simulation of the target computer.
In addition, the host computer that executes the simulation is generally controlled by a multitasking OS, and other processes that are not directly related to the simulation of the target computer also execute in parallel with the process for simulating the target computer. I do.

Here, consider a case where there is a task switch in the target program. As described above, from the viewpoint of speeding up the simulation, it is effective to describe, for example, the routine processing portion of the target program in a native code program based on the register set and the memory model of the host computer. Even if a native code program of the host computer is used, task switching cannot depend on the OS of the host computer. That is, each task in the target program is
Each part of the code depends on the register set and the memory model of the target computer (the target program itself may be used assuming that the instructions are interpreted and executed one instruction at a time, or the host computer as described in JP-A-6-250874). And the part written in the native code of the host computer depending on the register set and the memory model of the host computer. This is because the context switch must be performed, and the context switch cannot be performed synchronously when the OS depends on the OS of the host computer. Hereinafter, the part of the code that depends on the register set and the memory model of the target computer is called a target task, and the part that is written in the native code of the host computer and that depends on the register set and the memory model of the host computer is called a host task.

[0010] It is an object of the present invention to provide a simulation method and apparatus capable of performing a context switch by synchronizing a target task and a host task and thereby performing a simulation including task switching at a high speed. is there.

Another object of the present invention is to provide the above-mentioned simulation method and apparatus, wherein the execution result of the target task is reflected on the output of the host computer, or the input from the host computer is given to the target task. It is in.

[0012]

According to the present invention, there is provided a simulation method for simulating the operation of a target program created to operate on a target computer on a host computer having a central processing unit different from the target computer. In the above, the target program is divided into a target task, which is a part based on a register set specific to the target computer, and a host task, which is a part based on a register set specific to the host computer. A target task and a host task, and a virtual target register portion for virtually realizing a register of the target computer on the host computer, a target memory portion for virtually realizing a memory of the target computer, and a target task. Set a target stack that is a stack area corresponding to and a host stack that is a stack area corresponding to the host task, and execute a simulation using the virtual target register portion, the target memory portion, and the target stack for the target task, For the host task, a simulation is performed using the host stack and real registers of the host computer.

In the simulation method of the present invention, the target program can be a multitask type program including a plurality of tasks.
A target stack and a host stack are provided for each task. When the task is switched from the first task to the second task, the target task and the host task of the first task are saved, and then the first task is synchronized by synchronizing the target stack and the host stack. To switch in synchronization with the second task,
The target task and the host task of the second task may be restored.

Further, in the simulation method of the present invention, the address of the target memory portion is converted into the address of the host memory so that the host task or the OS of the host computer can refer to the memory contents of the target memory portion by specifying the address of the target CPU. By doing so, it becomes possible to output the processing result of the target task to the host computer, or to provide input data from the host computer to the target task.

The simulation apparatus of the present invention simulates the operation of a target program created to operate on a target computer on a host computer having a central processing unit different from the target computer.
It is divided into a target task that assumes a register set unique to the target computer and a host task that assumes a register set unique to the host computer.The target task and the host task are read and simulated on the host computer. In the simulation means, and virtually realizes a target stack which is a stack area corresponding to the target task, a host stack which is a stack area corresponding to the host stack, and a register of the target computer in the simulation means. It has a virtual target register part and a virtual target memory part that virtually realizes the memory of the target computer. For the target task, the virtual target register part, the target memory part and the target stack are There was run the simulation, the host task executes simulation using the actual registers of the host stack and the host computer.

In the simulation apparatus of the present invention, when the target program is composed of a plurality of tasks, a target task and a host task are provided for each task, and a target stack and a host task are provided for each task in the simulation means. A host stack is provided, and a target stack switching means for switching a target stack and a host stack switching means for switching a host stack are provided in the simulation means, and task switching from the first task to the second task is performed. When performing the task, save the target task and the host task of the first task,
Thereafter, the target stack and the host stack may be synchronized to switch from the first task to the second task in synchronization, and the target task and the host task of the second task may be restored.

Further, in the simulation apparatus of the present invention, there is provided an address conversion means for converting the address of the virtual target memory portion into the address of the host memory.
By making it possible to refer to the memory contents of the virtual target memory unit by specifying the address of the PU, it is possible to output the processing result of the target task to the host computer or to provide input data from the host computer to the target task. Become.

<< Operation >> In the present invention, a target task to be simulated is a target task which is a part based on a register set unique to the target computer, and a host is a part which is based on a register set unique to the host computer. In the simulation process, which is a process for performing this simulation on the host computer, in addition to a portion that virtually realizes the target computer (virtual target register portion and target memory portion), A target stack, which is a stack area corresponding to the target task, and a host stack corresponding to the host task are provided.The target task is processed by the part that virtually realizes the target computer, and the host task is processed by the real registers of the host computer. It is as to be. With this configuration, even when both the target task and the host task are described in the native code of the host computer, it is possible to avoid the problem related to the context switch.

In particular, when the target task is composed of a plurality of tasks, a target stack and a host stack are provided for each task, and when the tasks are switched, the target stack and the host stack are switched synchronously. Accordingly, a context switch can be performed by synchronizing the target task and the host task, and thereby a simulation including task switching can be performed at a high speed.

Further, by enabling the host task or the OS of the host computer to refer to the memory by specifying the address of the target CPU, data can be mutually input / output.

[0021]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the simulation device according to the first embodiment of the present invention.

This simulation device is built on a host computer and simulates a program (target program) on a target computer. Here, it is assumed that a simulation of a target OS in which a plurality of tasks operate simultaneously is executed as a target program. The host computer itself is managed by a host OS that operates a plurality of processes including a process for simulating the target computer in parallel. FIG. 1 shows, in its entirety,
This represents a host computer that executes a simulation. A general computer system is used as the host computer. In the following description, what is managed by the host OS in the host computer is called a process, and what is managed by the target OS to be simulated is called a task, so that the two are distinguished from each other.

The host CPU 10 is a central processing unit (CP) configured as hardware in the host computer.
U), a host register 11 is provided inside the host CPU 10, and the host register 11
The host CPU 10 includes a plurality of registers according to a register set. One of the registers constituting the host register 11 is a host stack pointer (HSP) 12 which holds the position of the host stack. As a matter of course, the host register 11 is also configured by hardware and is an actual register.

As described above, the simulation process 21 and other processes (external processes 14) are operating in parallel on the host computer.
The host OS 13 allocates the CPU usage right during the period 21. The simulation process 21 is a process for simulating the operation of the target computer as a simulation means. The simulation process 21 is under the control of the host OS 13 and is usually stored on a main memory (main memory) of the host computer or an external storage device such as a hard disk device. It is resident and executed by the host CPU 10.
Inside the simulation process 21, there is provided a virtual target unit 22 that virtually realizes the target computer by virtually expressing the environment of the target CPU on the host computer.

As described above, the program to be simulated by this simulation apparatus is a multitask OS application that switches between a plurality of tasks and executes the tasks. Here, each task is converted to the native code of the host computer, but depends on the memory model and register set of the target computer (target task 28), as in the case of the above-described conventional technology. ) And a part (host task 33) written in the native code of the host computer and based on the native memory model and register set of the host computer. 33 constitute a single task. These target tasks 28
And the host task 33 execute the simulation process 2
1 allows it to be read inside.
When switching tasks, target task 2
8 and the host task 33 must be switched synchronously.

The target task 28 includes a target CP
The code is generated by changing the instruction written in the assembly language of U into an instruction in the native code of the host computer, for example, one instruction at a time. The target task 28 may be an instruction sequence itself in the target computer, and may be interpreted one instruction at a time during simulation execution and converted into an instruction in the host computer. On the other hand, the host task 33 generates the code by compiling, for example, a source code described in a high-level language and converting the source code into a machine language instruction of the host CPU.
It is assumed that the corresponding target task 28 is called from the host task 33. In FIG. 1, a plurality of tasks are numbered, and host tasks HT1 to HTn,
Target tasks TT1 to TTn are shown.

By the way, task switching (context switch) is generally performed by saving the context of the task currently being executed and setting the context of the task to be executed next in the CPU. Here, the context is information sufficient to restart the execution of the task, and is, for example, a value of each internal register of the CPU, a value of a program counter, or the like. At the time of context switching, the context of each task is stored in the stack, so that a stack area is provided for each task. In the case of the present embodiment, each task includes a target task 28 depending on the configuration of the target CPU (memory model and register set) and a host task 33 depending on the configuration of the host CPU 10. There are two types of stack areas provided for each task, the target stack 27 and the host stack 34. That is, the host task HT1 to the host task HT
n, host stacks HS1 to HSn are provided corresponding to the target tasks TT1 to TTn, respectively.
TSn is provided. Then, a target stack switching means 26 is provided for switching the target stack 27, and a host stack switching means 31 is provided for switching the host stack 34.

The simulation process 21 includes storage areas for each target stack 27, each target task 28, each host task 33, and each host stack 34, target stack switching means 26, and host stack switching means 31. However, since the target stack switching means 26, the target stack 27, and the target task 28 are based on the memory model and the register set of the target CPU, they are arranged in the virtual target unit 22 described above. The virtual target unit 22 simulates a target register 23 (virtual target register portion) corresponding to a register set of the target CPU, and a main memory of the target CPU, in addition to the target stack switching unit 26, the target stack 27, and the target task 28. And a target memory 25 (virtual target memory portion) into which the target task 28 executed by the context switch is to be loaded. The target register 23 holds the position of the stack pointer of the target CPU. A target stack pointer (TSP) 24 is provided. The target register 23, unlike the host register 11, is realized by software in a work area thereof as a part of the simulation process 21.

In the case where the target task 28 directly retains the instruction sequence in the target computer, the instruction of the target computer is interpreted in the virtual target section 22 and converted into native code in the host CPU. It is sufficient to provide a part to be executed.

The host stack switching means 31, the host task 33 and the host stack 34
2 are arranged outside the virtual target unit 22 in the simulation process 22. Here, the host memory 32 is an area in which the host task 33 which is being executed by the context switch is to be loaded, and in the memory area to be used by the simulation process 21 in the main memory of the host computer. Is secured.

Next, a description will be given of a process of performing a context switch (task switching) in a target OS program to be simulated in the simulation apparatus. FIG. 2 is a flowchart for explaining the processing of the context switch. Here, it is assumed that the first task is switched to the second task.

Before the context switch, the contents of the host register 11 and the target register 23 relate to the first task, and the host stack pointer 12 points in the host stack 34 corresponding to the first task. The target stack pointer 24 points in the target stack 27 corresponding to the first task.
Therefore, when performing a context switch, first, the target register is saved (step 101), the host register is saved (step 102), and then the host stack 34 is switched from the first task to the second task ( (Step 103), the host registers for the second task are restored (Step 104), and similarly, the target stack 27 is switched from the first task to the second task (Step 105), and the target for the second task is changed. The register is restored (step 106). By the above operation, the contents of the host register 11 and the target register 23 are related to the second task, and the stack pointers 12 and 24 are pointed in the target stacks 34 and 27 corresponding to the second task. And the context switch is completed.

FIG. 3 is a diagram showing a stack operation at the time of context switching. Here, there are two tasks, task 1 and task 2, and task 1 is a host task ta.
sk1 and target tasks func11 and func12. Task 2 is a host task task2 and target tasks func21 and func.
Consists of 22. And in task 1, the host task
In task 1, target tasks func11 and func12 are called, and in task 2, target tasks func21 and func22 are called from host task task2.

Here, as shown in (1) of FIG.
Assume that a context switch to task2 occurs when returning from func11. At this time, the host frame of task 1 has a stack frame frame1h of task1 and the target stack has a stack frame frame11t of func11. However, when returning from func11, frame11t is released.

On the other hand, in the task 2, t is taken to the position (2) in FIG.
Assuming that ask2 has advanced, the host frame of task 2 holds the stack frame frame2h of task2, and the target stack holds the stack frame frame22t of func22. Therefore, by switching both stacks and restoring the host register and the virtual target register, the context of the entire task can be switched from task 1 to task 2.

The simulation apparatus described above reads a computer program corresponding to the simulation process 21 into a computer system corresponding to a host computer, and executes the computer program.
realizable. FIG. 4 is a block diagram showing a configuration of a computer system for realizing the simulation device by software.

The operation of this computer system is controlled by the host OS 13.
And a hard disk device 52 for storing programs and data.
A main memory 53, an input device 54 such as a keyboard and a mouse, a display device 55 such as a CRT, and a reading device 56 that reads a recording medium 57 such as a magnetic tape or a CD-ROM. Hard disk drive 52,
The main memory 53, the input device 54, the display device 55, and the reading device 56 are all connected to the central processing unit 51. The recording medium 57 storing the program corresponding to the simulation process 21 is attached to the reading device 56, the program is read from the recording medium 57 and stored in the hard disk device 52, and the program stored in the hard disk device 52 is read by the central processing unit 51. By executing, the simulation described above is executed. That is, by executing this program, the above-described simulation process 21 is generated on the host computer, and the initialization process in the simulation process 21 causes the stacks 27 and 33 and the target task 28,
Areas for the host memory 32 and the host task 33 are secured, and the target register 23 and the target memory 2 are allocated.
5, generated by the target stack switching means 26 and the host stack switching means 31. Then, after the initialization processing, the simulation of the target computer is executed by the simulation process 21 and the task switching according to the above-described procedure is executed.

Next, a second embodiment of the present invention will be described. FIG. 5 shows a simulation device according to the second embodiment of the present invention. In the simulation apparatus according to the second embodiment, in the simulation process 21, the point that the target memory 25 is included in the host memory 32 and the address conversion for converting the address in the target memory 25 to the address in the host computer. The point that the means 60 is provided is different from the simulation apparatus of the first embodiment shown in FIG.

FIG. 6 shows a target CPU and a host CPU.
Is an example of the configuration of the target memory 25 and the host memory 32 in the address space of FIG. The target CPU takes the address range from 0 to x as the target memory space 70, and the host CPU takes the address range from 0 to y as the host memory space 71. x and y values are C
Although they differ depending on the PU, they may or may not match. Also, the target memory space 7
Numeral 0 is a space provided by the target CPU to be simulated, and is virtually handled on the simulation apparatus.

Now, as described in the first embodiment,
In the simulation process 21, the simulation target program is divided into two parts, a target task 28 and a host task 33, and accesses the target memory 25 and the host memory 32, respectively. At this time, the addresses are specified by assuming the target memory space 70 and the host memory space 71, respectively. Therefore, address exchange is necessary to exchange memory contents with each other. However, since the target task 28 originally operates on the target computer, it cannot be changed for simulation. Therefore, the address translation must be performed outside the target task 28.

Here, the target task 28 determines whether the area (1) (T _{1 to} T ₂ ) and the area (2) (T
_{3 to} T ₄ ), and the host task 33 uses the host area (H _{1 to} H ₂ ) of the host memory space 71. At this time, in the region (1) and region (2) the entity of the target area on the host memory space (1) (T ₁ 'through T _2') and the target area _{(2) (T 3 '~T} 4') placing, for example, access to the address a of the area (1) will correspond to access to the address on the target area (1) a '(= a + T 1' -T 1).

The address conversion means 60 is a host task 3
When a request for access to the target memory 25 is issued from the server 3, the requested address is converted as described above and associated with the host memory space 71. With this address conversion means 60, the host task 33 can access the target memory space 70 by specifying the address of the target CPU, and can exchange memory contents with the target task 28.

Next, the operation of the simulation apparatus according to the present embodiment will be described.

The operation relating to the context switching of the tasks shown in FIGS. 2 and 3 is the same as that of the first embodiment in this embodiment, and therefore the description thereof is omitted. This will be described with reference to FIG.

First, the host task 33 requests access to address a in the target memory space 70 (step 110). Upon receiving the request, the address conversion means 60 performs the above-described address conversion to obtain an access address a 'in the host memory space 71 (step 1).
11). Next, in step 112, data is read from the address a 'and transferred to the requesting host task 33 (step 113). With this operation, the host task 33 can acquire data from an arbitrary address in the target memory space 70.

For example, when the area (1) of the target memory space 70 shown in FIG. 6 is allocated to the image storage area in the program to be simulated, the host task 33 uses the above-described method to execute the target area (1). And the contents can be displayed on the display device 55 in the computer system via the host OS 13. That is, the change made by the target task to the area (1) of the target memory space 70 appears on the display output of the host computer system as a simulation result.

Here, it is assumed that the host OS 13 acquires display contents from the target memory space 70 via the host task 33. However, the host OS 13 directly calls the address conversion means 60 to specify the specific contents of the target memory space 70. The contents of the area may be read and displayed. Also, here, the operation result of the target task is output to the display device of the host computer system.On the contrary, some input is given from the host computer system, and this is reflected in the operation of the target task, that is, from the host computer system, A form in which input data is provided to the target task is also possible.

In the simulation device of the second embodiment, similarly to the simulation device of the first embodiment, a computer program corresponding to the simulation process 21 is converted into a computer system corresponding to a host computer (for example, see FIG. 4). And executing the computer program.

[0049]

As described above, according to the present invention, a part (virtual target register part and target memory part) that virtually realizes a target computer is included in a simulation process for performing a simulation on a host computer. In addition, by providing a target stack that is a stack area corresponding to the target task and a host stack corresponding to the host task, both the target task and the host task are described in the native code of the host computer. However, there is an effect that a problem related to a context switch can be avoided. In particular, when the target task is composed of a plurality of tasks, a target stack and a host stack are provided for each task, and when the tasks are switched, the target stack and the host stack are switched synchronously.
The context switch can be performed by synchronizing the target task and the host task, which has the effect that simulation including task switching can be performed at high speed.

Further, when address translation means for translating the address of the virtual target memory portion into an address in the host computer is provided, in addition to the effect of enabling high-speed simulation including the task switching, the target The host task or the host OS can access the memory area arranged in the CPU-specific memory space, and the target task and the host task or the host OS can exchange memory contents in the target memory space. An effect also occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a simulation device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing of a context switch in the simulation apparatus of FIG. 1;

FIG. 3 is a diagram schematically illustrating a stack operation at the time of a context switch.

FIG. 4 is a block diagram showing an example of a configuration of a computer system used to execute a simulation method of the present invention.

FIG. 5 is a block diagram showing a configuration of a simulation device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a relationship between a target memory space and a host memory space in the simulation device of FIG. 5;

FIG. 7 is a flowchart illustrating a process of an address translation unit in the simulation device of FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Host CPU 11 Host register 12 Host stack pointer 13 Host OS 14 External process 21 Simulation process 22 Virtual target part 23 Target register 24 Target stack pointer 25 Target memory 26 Target stack switching means 27 Target stack 28 Target task 31 Host stack switching means 32 Host memory 33 Host task 34 Host stack 51 Central processing unit (CPU) 52 Hard disk device 53 Main memory 54 Input device 55 Display device 56 Reading device 57 Recording medium 60 Address conversion means 70 Target memory space 71 Host memory space 101 to 106, 110 ~ 113 steps

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/455 G06F 9/46

Claims (10)

(57) [Claims] 1. A simulation method for simulating an operation of a target program created to operate on a target computer on a host computer having a central processing unit different from the target computer, wherein the target program is executed by the target computer. Are divided into a target task, which is a part based on a register set specific to the host computer, and a host task, which is a part based on a register set specific to the host computer. A virtual target register portion that arranges the host task and virtually realizes a register of the target computer on the host computer;
Setting a virtual target memory portion that virtually realizes the memory of the target computer, a target stack that is a stack area corresponding to the target task, and a host stack that is a stack area corresponding to the host task; For the task, execute a simulation using the virtual target register portion, the virtual target memory portion and the target stack,
A simulation method for the host task, wherein a simulation is performed using the host stack and real registers of the host computer. 2. The simulation method according to claim 1, wherein the target program includes a plurality of tasks each including the target task and the host task, and the target stack and the host stack are provided for each of the tasks. . 3. When a task is switched from a first task to a second task, a target task and a host task of the first task are saved, and then the target stack and the host stack are synchronized. Switching from the first task to the second task
3. The simulation method according to claim 2, wherein the target task and the host task of the first task are returned. 4. The simulation according to claim 1, wherein an address of said virtual target memory portion is converted into an address in a host computer, so that a host task can access said virtual target memory portion. Method. 5. The target task is a program in which an instruction sequence based on an instruction system of the target computer is converted into an instruction sequence based on a native code of the host computer.
5. The host task, wherein a source code written in a high-level language commonly used by the host computer and the target computer is converted into a native code of the host computer by compilation. 6. The simulation method according to claim 1. 6. A simulation apparatus for simulating the operation of a target program created to operate on a target computer on a host computer having a central processing unit different from the target computer, wherein the target program is configured to execute the target computer. Are divided into a target task that assumes a register set unique to the host computer and a host task that assumes a register set unique to the host computer.The target task and the host task are read on the host computer. A simulation unit that executes the simulation in the simulation unit, and a target stack that is a stack area corresponding to the target task in the simulation unit;
A host stack that is a stack area corresponding to the host stack; a virtual target register portion that virtually realizes a register of the target computer; and a virtual target memory portion that virtually realizes a memory of the target computer. Performing a simulation using the virtual target register portion, the virtual target memory portion, and the target stack for the target task;
The simulation apparatus according to claim 1, wherein the host task performs a simulation using the host stack and real registers of the host computer. 7. The target program is composed of a plurality of tasks, the target task and the host task are provided for each task, and the target stack and the host provided for each task in the simulation means. A stack, a target stack switching unit for switching the target stack, and a host stack switching unit for switching the host stack, wherein when the task switching from the first task to the second task is performed, the first Save the target task and the host task of the task, and then synchronize the target stack and the host stack to switch from the first task to the second task and return the target task and the host task of the second task Claim
A simulation device according to claim 1. 8. The simulation means further comprises an address conversion means for converting an address of the virtual target memory portion into an address in a host computer, so that a host task can access the virtual target memory portion. The simulation device according to claim 6 or 7, wherein: 9. A program for simulating the operation of a target program created to operate on a target computer on a host computer having a central processing unit different from the target computer, and read by the host computer. In a possible recording medium, the target program is divided into a target task which is a part based on a register set specific to the target computer, and a host task which is a part based on a register set specific to the host computer. The host computer corresponds to a virtual target register portion that virtually realizes a register of the target computer, a virtual target memory portion that virtually realizes a memory of the target computer, and corresponds to the target task. Stack area Setting a target stack that is an area and a host stack that is a stack area corresponding to the host task; and simulating the target task using the virtual target register portion, the virtual target memory portion, and the target stack. Run
A storage medium storing a program for executing, for the host task, a simulation using the real registers of the host stack and the host computer; 10. A program for simulating the operation of a target program created to operate on a target computer on a host computer having a central processing unit different from the target computer, and read by the host computer. In a possible recording medium, the target program is composed of a plurality of tasks, each of the tasks being a part assuming a register set unique to the target computer, and a register set unique to the host computer. The host computer is divided into a host task, a virtual target register portion that virtually realizes the register of the target computer, and a virtual target portion that virtually realizes the memory of the target computer. Target memory A target stack, which is a stack area corresponding to the target task for each of the target tasks,
Setting a host stack that is a stack area corresponding to the host task for each of the host tasks; and executing a simulation using the virtual target register portion, the virtual target memory portion, and the target stack for the target task. And
For the host task, a step of executing a simulation using the host stack and real registers of the host computer; saving a target task and a host task of a first task; Switching from the first task to the second task by synchronously switching from the first task to the second task and restoring the target task and the host task of the second task And a program for executing the following.