JPH05274385A - Logic verification environment controlling device - Google Patents

Abstract

PURPOSE:To provide the logic verification environment controlling device realizing accurate logic verification by setting environment equivalent to the real use environment and readily analyzing a fault in case of occurring a fault. CONSTITUTION:The system consists of an information processor 1 for logic verification, system console 2, verification program file 3, model information file 4, and trace information file 5. The information processor 1 is provided with an environment state controlling device 11, random data generating device 12 for an entry embeding random number data, entry random number data setting device 13, interrupt controlling device 14 performing a back trace at the run away of a program, memory 15, cache 16, register 17, and TLB 18. Before executing the logic verification program, the resource in the information processor 1 is initialized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic verification technique for a logic circuit which constitutes a logic simulation device or an information processing device, and particularly to a logic verification environment control suitable for highly accurate verification of a complicated and large scale logic circuit. The present invention relates to a technique effectively applied to a device.

[0002]

2. Description of the Related Art For example, in a conventional logic verification method, an information processing device has a memory, a cache, a register, a TLB (Table Look-asi) in the information processing device after a power-on reset.
de Buffer) is initialized (zero-cleared) or similar state, and the logic verification program is loaded into the memory, or the verification program data is set in the corresponding memory, cache, register, etc. and executed. It was

As a related conventional technique of this kind,
For example, the technique described in JP-A-3-250225 can be cited.

[0004]

However, in the conventional technology as described above, in the actual usage environment of the information processing apparatus, a plurality of jobs including the user application job including the operating system are asynchronously executed. Under such circumstances, random data is arranged as the contents of the memory, cache, register, TLB, etc. in the information processing device when viewed from the target program.

In this case, from the state after the power-on reset of the information processing device, or a state similar thereto, random data is arranged in the resources in the information processing device such as the usage environment, and a plurality of conditions overlap. It is known that if a logic defect is inherent in the information processing device, a malfunction occurs and the logic defect is easily detected.

Therefore, the conventional logic verification technique has a problem that the verification accuracy is low because the logic verification is not performed in the information processing apparatus environment equivalent to the actual use environment.

Therefore, an object of the present invention is to construct an environment equivalent to the execution of an actual user program under an operating system, and to enable logic verification in an environment equivalent to this actual use environment. Is to provide a logic verification environment control device capable of realizing highly accurate logic verification.

Another object of the present invention is to provide a logic verification environment control device which, when a failure occurs, backtraces from the interrupt address of the failure occurrence and can easily realize the failure analysis by this trace information. To provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the logic verification environment control device of the present invention is a logic simulation device for performing a gate-level circuit simulation or a logic verification environment control device for an information processing device, and is random number data for creating random random number data. A generator is generated in the logic simulation device or the information processing device, and a random number data setting device for setting the random number data in a data storage means in the logic simulation device or the information processing device, such as a memory, a cache, a TLB, or a register. An interrupt control device for controlling an interrupt, an operator interface control, a control of a logic simulation device or an information processing device, and an environmental state control device for carrying out edit output of trace information are provided.

In this case, when creating the entry data of the data storage means, the entry data, such as a parity bit and a Hamming code (ECC: Error Corr) are used.
ecting code) is created so as to match the logical format of the logic simulation device or the information processing device, and random number data is embedded in the entry data.

Further, the random number data generating device is adapted to generate an instruction and address data operating on a specific logic simulation device or information processing device, such as a machine language instruction code and operand address data.

Further, when the random number data generator creates random number data to be set in the data storage means, it generates an interrupt generation instruction operand code at a pitch of several tens to several hundreds of bytes.

Further, the interrupt processing device checks an interrupt generation address and an interrupt type, performs a back trace within a traceable range from the interrupt generation address, and saves the trace information.

[0016]

According to the above-described logic verification environment control device, the random number data generator, the random number data setting device, the interrupt controller and the environmental condition controller are provided so that the entry data such as the parity bit and the Hamming code can be logically processed. Created to match the format,
Random data generated by the random number data generator is embedded in this entry data, this entry data is set in the data storage means by the random number data setting device, and the logic simulation device or resources in the information processing device are actually used before the execution of the logic verification program. Can be set to an environment equivalent to the environment.

Further, due to the generation of a specific machine language instruction code and operand address data, it can be operated only on a specific logic simulation device or information processing device.

Further, an interrupt generation instruction operand code is generated at a pitch of several tens to several hundred bytes, and the interrupt generation address and the interrupt type are checked,
Backtrace can be performed within the traceable range from the interrupt generation address, and this trace information can be saved.

As a result, a device environment equivalent to that in which an actual user program is executed under the operating system is constructed, and logic verification under this environment is made possible to realize highly accurate logic verification. The failure analysis can be easily realized when a failure occurs.

[0020]

FIG. 1 is a block diagram showing a logic verification environment control device according to an embodiment of the present invention, and FIG. 2 shows processing of a random number data generator and a random number data setting device in the logic verification environment control device of this embodiment. FIG. 3 is a flow chart showing the cache data creation process of the random number data generator in this embodiment, and FIG. 4 shows the data creation / setting process of the hardware registers of the random number data generator and the random number data setting device. FIG. 5 is a flowchart showing a logic verification process using the logic verification environment control device of this embodiment.

First, the configuration of the logic verification environment control apparatus of this embodiment will be described with reference to FIG.

The logical verification environment control device of the present embodiment is, for example, a logical verification environment control device for an information processing device, and stores the target information processing device 1, system console 2, and execution form logical verification program. It comprises a verification program file 3, a model information file 4 in which the sizes and entries of each RAM are stored, a trace information file 5 for storing back trace information, and the like.

The target information processing apparatus 1 includes an operator interface control, an environmental state control apparatus 11 for controlling each apparatus and a trace information edit output process, and a random number data is embedded in a target RAM of the information processing apparatus to make an entry. Random number data generator 12 for creating a random number data setting device 1 for setting the created entry in the target RAM
3. When the logic verification program executed under the set environment runs out of control due to a logic failure and an interrupt occurs due to an interrupt generation instruction, the interrupt control device 14 for executing the recovery process and back trace, the target of the data storage means RAM
A memory 15, a cache 16, a register 17, a TLB 18, and the like.

Next, the operation of this embodiment will be described.

First, referring to FIG. 2, a random number data generator 1
2 and the processing of the random number data setting device 13 will be described.

When the random number data generator 12 is activated by the environmental condition controller 11, first, the model information file 4 is generated.
The size of the memory 15, the cache 16, the register 17, the TLB 18, etc. of each RAM in the information processing apparatus 1, the format of the entry, the block / line size, etc. are read from it and the entry data of each RAM is generated according to the instruction.

At this time, parity bits such as the TLB 18 and the cache address array and a Hamming code (EC
When the entry data having C) or the like is generated, data matching the logical format of the information processing device 1 is generated at a predetermined bit position according to the instruction of the model information file 4.

The data in the memory 15 and the cache 16 generate random number data in a designated block / line size unit. In this case, the machine code of a dedicated interrupt instruction for generating an interrupt for transferring control to the interrupt controller 14 is embedded in the last few bytes of each block / line. After generating the entry data, the random number data generator 12 transfers control to the random number data setting device 13.

Further, the random number data setting device 13 sets the entry data generated by the random number data generating device 12 in a predetermined RAM as much as the entry data for the size (the number of entries) registered in the model information file 4. ..

Next, the code cache data creation process of the random number data generator 12 will be described with reference to the flow of FIG.

The random number data generator 12 first reads the code cache entry information from the model information file 4 (step 301) and creates a Hamming code (ECC) portion according to this entry information (step 30).
2) Next, random number data is created by generating random numbers from the actual code data (step 303).

Further, the interrupt generation instruction code is embedded at the end of the block of the code cache entry (step 304), and the random number data setting device 13 is activated (step 305).

Next, the data creation / setting process of the hardware (H / W) register will be described with reference to the flow of FIG.

If a wait occurs in the advance control processing of the information processing apparatus 1, that is, the contents of the register determined by the LD (memory-to-register data transfer) instruction are transferred to the next MVC (memory-to-memory data). Transfer) command
When it is used as a memory address, the address calculation processing of the MVC instruction cannot be performed until the processing of this LD instruction is completed, so that the processing waits and the register temporarily becomes empty.

When such a condition occurs, the environmental condition control device 11 senses that a bubble has occurred due to a lock at the A stage register (step 40).
1) Issue a data generation instruction to the random number data generator 12.

Further, the random number data generator 12 creates data of the A stage register (step 402),
A data setting instruction is issued to the random number data setting device 13.

Then, the random number data setting device 13 embeds the generated random number value data in the A stage register (step 403).

Next, the processing flow of logic verification using the logic verification environment control device of this embodiment will be described with reference to FIG.

First, the environmental condition control device 11 activates the random number data generation device 12 according to an instruction from the operator (step 501). Then, the random number data generator 12
The generation information of the entry data of each RAM is read from the model information file 4 (step 502), and the entry data of each RAM is created according to this model information (step 503).

Further, the random number data generator 12 activates the random number data setting device 13 (step 504), and the random number data setting device 13 creates entry data according to the size of each RAM registered in the model information file 4. Is initialized in each RAM (step 505).

After the initialization, the control is returned to the environmental condition control device 11 (step 506), and the environmental condition control device 11 loads the corresponding logic verification program in the memory 15 according to the instruction of the operator (step 50).
7), start this logic verification program (step 5)
08).

Further, when the execution of the logic verification program ends normally, the environmental condition control device 11 repeats the process of requesting the operator for the next process.

If the logic verification program runs out of control (step 509), control is transferred to the interrupt controller 14 by an interrupt generation instruction (step 510), trace information is collected retroactively to a backtraceable address, and trace information is collected. Register in file 5 (step 51)
1).

Then, the control returns to the environmental condition control device 11 (step 512), the environmental condition control device 11 edits the trace information and outputs the trace information to the system console 2 (step 513), which causes the runaway. Is analyzed.

Therefore, according to the logic verification environment control device of the present embodiment, the environment condition control device 11, the random number data generation device 12, the random number data setting device 13 and the interrupt control device 1 are provided.
4 is provided, random number data is embedded in the entry data, and the entry data is stored in each RAM in the information processing device 1.
Memory 15, cache 16, register 17 and T
By initializing in the LB 18 or the like, the data storage means in the information report processing device 1 to be subjected to the logic verification can be set in an environment equivalent to that in which an actual user program is executed, whereby the actual use Logical verification under the environment is possible.

Further, even when the logic verification program runs out of control, the back trace can be performed from the interrupt generation address by the interrupt generation instruction, so that the trace information facilitates the failure analysis when the failure occurs.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, with respect to the logic verification environment control apparatus of this embodiment, the case where the target of logic verification is the information processing apparatus 1 has been described, but the present invention is not limited to the above embodiment, and the gate level is used. The present invention can be widely applied to a logic simulation device that executes the circuit simulation of 1.

Further, as the random number data generator 12,
For example, a machine language instruction code and operand address data that operate on a specific information processing device may be generated.

[0050]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1). By providing a random number data generator, a random number data setting device, an interrupt controller and an environmental condition controller, the entry data is created so as to match the logical format, and the random data is added to this entry data. Since the data can be embedded and set in the data storage means, the logic simulation device or the resources in the information processing device can be constructed in an environment equivalent to the actual use environment before the execution of the logic verification program.

(2). Since the random number data generator generates a specific instruction and address data, it can be operated only on a specific logic simulation device or information processing device.

(3). The random number data generator generates an interrupt generation instruction operand code at a pitch of several tens to several hundreds of bytes, and the interrupt processing unit performs back trace from the interrupt generation address of this interrupt generation instruction operand code. Since the trace information can be saved, failure analysis can be easily performed when a failure occurs.

(4) According to the above (1) to (3), the logic simulation device or the information processing device to be the logic verification target can be logically verified under the actual use environment, thereby achieving high accuracy. It is possible to obtain a logic verification environment control device that realizes logic verification and facilitates failure analysis when a failure occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a logical verification environment control device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a process of a random number data generation device and a random number data setting device in the logic verification environment control device of the present embodiment.

FIG. 3 is a flowchart showing a cache data creation process of the random number data generation device in the present embodiment.

FIG. 4 is a flowchart showing a data creation / setting process of hardware registers of the random number data generator and the random number data setting device in the present embodiment.

FIG. 5 is a flowchart showing a logic verification process using the logic verification environment control device of the present embodiment.

[Explanation of symbols]

 1 Information Processing Device 2 System Console 3 Verification Program File 4 Model Information File 5 Trace Information File 11 Environmental Status Control Device 12 Random Data Generator 13 Random Data Setting Device 14 Interrupt Control Device 15 Memory 16 Cache 17 Register 18 TLB

Claims (5)

[Claims] 1. A logic simulation device for performing gate-level circuit simulation, or a logic verification environment control device for an information processing device, wherein a random number data generator for creating random random number data, and the random number data for the logic. A random number data setting device to be set in the data storage means in the simulation device or the information processing device, an interrupt control device for controlling an interrupt generated in the logic simulation device or the information processing device, an operator interface control, the logic simulation device or An environment state control device for controlling the information processing device and for editing and outputting the trace information is provided, and before the execution of the logic verification program, the logic simulation device or the resources in the information processing device are converted into an environment equivalent to the actual use environment. Special to set Logical verification environment control device. 2. When the entry data of the data storage means is created, the entry data is created so as to match the logical format of the logic simulation device or the information processing device, and the random number data is embedded in the entry data. The logical verification environment control device according to claim 1, wherein: 3. The logic verification environment control device according to claim 1, wherein the random number data generation device generates an instruction and address data which operate on a specific logic simulation device or information processing device. 4. The random number data generating device generates an interrupt generation instruction operand code at a pitch of several tens to several hundreds of bytes when generating the random number data to be set in the data storage means. The described logic verification environment control device. 5. The interrupt processing device checks the interrupt generation address and interrupt type, backtraces within a traceable range from the interrupt generation address, and saves the trace information. Logical verification environment control device.