CN1794244B - Data conversion unit and its implementing method and data receiving module - Google Patents
Data conversion unit and its implementing method and data receiving module Download PDFInfo
- Publication number
- CN1794244B CN1794244B CN 200510023083 CN200510023083A CN1794244B CN 1794244 B CN1794244 B CN 1794244B CN 200510023083 CN200510023083 CN 200510023083 CN 200510023083 A CN200510023083 A CN 200510023083A CN 1794244 B CN1794244 B CN 1794244B
- Authority
- CN
- China
- Prior art keywords
- data
- conversion unit
- date conversion
- output
- input signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000006243 chemical reaction Methods 0.000 title claims description 91
- 238000012545 processing Methods 0.000 description 12
- 238000013461 design Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Landscapes
- Communication Control (AREA)
Abstract
This invention discloses a data converting unit including a converter used in a package algorithm process and receiving input and output signals from outside and receiving data from the data receiving module to process the algorithm and output it when the input signal is valid and the output signal is invalid, a data receiving module used in receiving input signals from outside, recording the effective data length of its buffer storage and receiving data to buffer-store them and output them to said converter when its own buffer stored effective length is zero and the input signal is valid.
Description
Technical field
The present invention relates to the chip emulation technology, particularly be applied to a kind of Date Conversion Unit and its implementation in the chip emulation platform.
Background technology
At present, chip is being brought into play important effect at electronic technology field, and the operation of most of electronic equipment all depends on the realization of its inside chip.The realization of chip comprises two stages: chip design and chip manufacturing.
So-called chip design comprises: algorithm is realized and the peripheral logical circuit design.Wherein, algorithm is the soul of chip, and it is used to describe the function that chip is realized, so-called algorithm is realized comprising: algorithm research, realize algorithm that research obtains or the like in chip; So-called peripheral logical circuit refers to be the auxiliary circuit of realizing that chip functions designs, such as: the shaking hands etc. of the connection of power supply, internal module.Afterwards, carry out chip manufacturing on the basis of chip design, and the cost of chip manufacturing is very high, the cost of at every turn throwing sheet is usually about the hundreds of thousands dollar.The key step of chip manufacturing will be carried out flow according to the chip design result exactly.But chip is once flow, and its inner logic just can not be changed again, if chip design goes wrong, and just flow again, this will bring massive losses to company.
Because the cost of chip flow is very high, this has just proposed very high request to chip design, how to guarantee the correctness of chip design, is the important topic that all chip companies all will be faced.In the process of chip design, need to make up the chip emulation software platform usually and come the correctness of chip functions is verified.At present, the hardware description language that the chip emulation software platform mainly uses has VHDL, Verilog etc., there have been some chip emulation platforms based on main flow hardware description languages such as VHDL, Verilog in industry, can process chip algorithm simulating and the emulation of chip periphery logical circuit.
Wherein, the key of chip emulation is algorithm simulating, and reason is: the core of chip will directly determine the function that chip is realized for the algorithm that it carried, algorithm.So in the chip accuracy verification, most important is exactly the checking checking of chip algorithm just of chip functions.Though at present based on the chip emulation platform of hardware description language can proofing chip algorithm, also have following shortcoming:
1, simulation velocity is slow
Because hardware description language is used to describe the function of hardware, the parallel processing structure that its support hardware is required, this structure is different with the characteristic of computing machine, as carrying out emulation to the hardware description statement on computers, can only realize by interpretive routine.That is to say that all emulation platforms based on hardware description language all are that its execution speed is very slow to the execution that makes an explanation of these hardware description statements at present.For instance, carry out emulation as the chip statement to V568 in the V568 chip, then the image of a width of cloth VGA is that resolution is that 640 * 480 image data format needs the time more than one day to handle at least.
2, take more resource
Because these chip emulation platforms are very complicated, and are therefore also very high to the requirement of computing machine, often need to operate on the workstation, even need many workstations to move simultaneously, this will expend a large amount of processing resources, make the chip emulation cost higher.
3, realize complexity
Because these chip emulation platform functions are very powerful, so use very complexity, set up test environment or the like such as needs, and the built-in function of every kind of chip all may be different, will set up a simulated environment for every kind of chip so, it is quite big to implement difficulty like this.
Shortcoming in view of above-mentioned chip emulation platform based on hardware description language, recently, industry has also proposed a kind of chip emulation platform based on language such as C/C++, this kind chip emulation platform is consistent with the characteristic of computing machine, may operate on the computing machine, therefore, the travelling speed nature is more a lot of soon than the emulation platform based on hardware description language, be easy to debugging (debug), and can not take too many processing resource, have stronger exploitativeness.
In addition, this kind can provide such as functions such as dynamic creation algorithm simulated model, operation algorithm simulated models for the user based on the chip emulation platform of language such as C/C++, make the user can need to set up flexibly the chip algorithm combination of the emulation of wanting by emulation, thereby be easy to the array mode that the user adjusts chip algorithm, obtain the best of breed of chip algorithm with emulation.Here, the combination of corresponding one or more chip algorithms of each algorithm simulated model, the user may select one or more algorithm simulated models to carry out simulation process in a chip algorithm simulating process.
Wherein, this chip emulation platform each algorithm process that can provide will be packaged into respectively in each Date Conversion Unit.When will be by the algorithm simulated model deal with data, to connect corresponding each Date Conversion Unit of each algorithm process in this algorithm simulated model by the array mode of each algorithm process in the current algorithm realistic model, and the Date Conversion Unit of the initial algorithm process correspondence in current algorithm realistic model input data; The data that each Date Conversion Unit receives self are carried out corresponding algorithm processing and output, by the Date Conversion Unit output result data of algorithm process correspondence last in the current algorithm realistic model.
Because this kind chip emulation platform runs on the computing machine, therefore, the CPU (central processing unit) of computing machine (CPU) constantly can only be a data converting unit Resources allocation at each.So, constituting in each Date Conversion Unit of current algorithm realistic model, each can only have a data converting unit constantly in operation.Like this, when a certain Date Conversion Unit output data can not be moved but this another Date Conversion Unit does not obtain cpu resource again to another Date Conversion Unit, problems such as data processing is made mistakes, loss of data will appear.And for Date Conversion Unit, its speed that receives data and himself conversion also speed of output data are different usually, so just are easy to generate problems such as loss of data and drain process.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of Date Conversion Unit and its implementation, can guarantee the data processing accuracy at chip algorithm simulating platform.
For achieving the above object, technical scheme of the present invention is achieved in that
The invention discloses a kind of Date Conversion Unit, this Date Conversion Unit comprises:
Converter wherein is packaged with algorithm process, be used for from outside receiving inputted signal and output signal, input signal effectively and output signal receive data from data reception module when invalid and carry out algorithm process and output;
Data reception module is used for from outside receiving inputted signal, writes down the valid data length of self buffer memory, when the valid data length of self buffer memory be zero and input signal receive data from the outside when effective, buffer memory and output data are to described converter.
Wherein, described data reception module comprises:
Storer, be used for receiving described input signal from the outside, receive the valid data length of self buffer memory from address counter, when the valid data length of self buffer memory be zero and input signal receive data from the outside when effective, buffer memory and output data are to described converter;
Address counter is used to monitor the read-write operation of described storer, writes down the valid data length of this memory buffer and exports this storer to.
Wherein, described input signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit input end, and described input signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit input end is sky;
Described output signal is the store status of the data buffer storage unit output of this Date Conversion Unit output terminal connection, described output signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit output terminal, and described output signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit output terminal is sky.
The invention also discloses a kind of implementation method of Date Conversion Unit, this method comprises: be packaged with algorithm process in the described Date Conversion Unit, the data that receive are carried out packaged algorithm process and output;
Further receiving inputted signal of described Date Conversion Unit and output signal;
This Date Conversion Unit further data of receiving of buffer memory before data are carried out algorithm process, and write down the valid data length of self buffer memory;
The method that described Date Conversion Unit receives data is: when the valid data length of self buffer memory be zero and input signal receive data when effective;
The method that described Date Conversion Unit carries out algorithm process to the data that receive is: when input signal effectively and output signal when invalid, self data in buffer is carried out algorithm process.
Wherein, described input signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit input end, and described input signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit input end is sky;
Described output signal is the store status of the data buffer storage unit output of this Date Conversion Unit output terminal connection, described output signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit output terminal, and described output signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit output terminal is sky.
By such scheme as can be seen, key of the present invention is: Date Conversion Unit can judge that automatically self whether can receive data carries out buffer memory according to external input signal and output signal, and data in buffer is carried out algorithm process.
Therefore, Date Conversion Unit provided by the present invention and its implementation and data reception module, can guarantee the data processing correctness of the Date Conversion Unit of chip emulation platform, avoid the appearance of problems such as loss of data, mistake processing, thereby solved the existing key issue that exists based on the chip emulation platform of language such as C/C++.
Description of drawings
Fig. 1 is the composition structural representation of Date Conversion Unit of the present invention;
Fig. 2 is the inventive method one preferred embodiment treatment scheme synoptic diagram.
Embodiment
The present invention is further described in more detail below in conjunction with drawings and the specific embodiments.
The invention provides a kind of Date Conversion Unit, this Date Conversion Unit is mainly used among the chip emulation platform.By background technology as can be known, existing Date Conversion Unit is mainly used in the encapsulation algorithm process and the data that receive is carried out this algorithm process.For guaranteeing the accuracy of algorithm process, avoid loss of data and mistake to handle, Date Conversion Unit of the present invention mainly comprises two parts: data reception module and converter.
Wherein, converter is used to encapsulate algorithm process, receives the input signal and the output signal of self place Date Conversion Unit from the outside, input signal effectively and output signal receive data from described data reception module when invalid and carry out algorithm process and output; Data reception module, be used for from the input signal of outside reception self place Date Conversion Unit, write down the valid data length of self buffer memory, when the valid data length of self buffer memory be zero and input signal receive data from the outside when effective, buffer memory and output data are to described converter.
Fig. 1 forms structural representation for Date Conversion Unit one preferred embodiment of the present invention.As shown in Figure 1, this Date Conversion Unit comprises: converter and data reception module, this data reception module further comprises: storer and address counter.Here, data reception module of the present invention is also referred to as the input port (PORT) of Date Conversion Unit usually.
Wherein, converter is used to encapsulate algorithm process, input data entity and output data entity difference receiving inputted signal and output signal from the Date Conversion Unit outside, when input signal effectively and output signal receives data from storer when invalid, these data are carried out algorithm process after output data to this output data entity; Storer is used for from described input data entity receiving inputted signal, valid data length from address counter reception self buffer memory, when the valid data length of self buffer memory be zero and input signal receive data from the outside when effective, buffer memory and output data are to described converter; Address counter is used to monitor the read-write operation of the storer that self connects, and writes down the valid data length of this memory buffer and exports this storer to.
Wherein, input data entity that Date Conversion Unit connects and output data entity have multiple, relatively typically the data buffer storage unit that connects between the Date Conversion Unit in chip emulation platform exactly.Therefore, the store status of the data buffer storage unit output that described input signal can connect for this Date Conversion Unit input end, described input signal be described store status non-NULL effectively, described input signal is invalid be that described store status is a sky; The store status of the data buffer storage unit output that described output signal can connect for this Date Conversion Unit output terminal, described input signal be described store status non-NULL effectively, described input signal is invalid be that described store status is a sky.Here, the problem that solves about the non-the present invention of the specific implementation of data buffer storage unit and in another piece of the applicant patent, having had a detailed description, therefore, this paper is not described in further detail this.
On the basis of the invention described above Date Conversion Unit, the present invention also provides a kind of implementation method of Date Conversion Unit, and Fig. 2 is the inventive method one preferred embodiment treatment scheme synoptic diagram.As shown in Figure 2, the concrete processing comprises:
Step 201: in Date Conversion Unit, encapsulate algorithm process in advance.
Step 202: after this Date Conversion Unit starts, will read input signal and output signal respectively from the input data entity and the output data entity of outside.
Step 203: when and valid data length that self preserve effective when input signal was zero, this Date Conversion Unit began to receive data and buffer memory from the input data entity of outside; When input signal effectively and output signal when invalid, this Date Conversion Unit carries out packaged algorithm process to self data in buffer, the data after output algorithm is handled are again given the output data entity.
Here, described input data entity and output data entity can be the data buffer storage unit that connects between each Date Conversion Unit in the chip emulation platform, therefore, described input signal can be the store status of the data buffer storage unit output that this Date Conversion Unit input end connects, described input signal is described store status non-NULL effectively, and described input signal is invalid to be that described store status is for empty; Described output signal can be the store status of the data buffer storage unit output that this Date Conversion Unit output terminal connects, and described input signal be described store status non-NULL effectively, and described input signal is invalid be that described store status is a sky.
The Date Conversion Unit of realizing according to the described method of above Fig. 2 can adopt container to realize, therefore, also Date Conversion Unit of the present invention is called system container usually.
In addition, the present invention also provides a kind of data reception module, and this data reception module is identical with the composition structure of data reception module shown in Figure 1, comprising: storer and address counter.
Wherein, storer is used for the input data entity receiving inputted signal from the outside, valid data length from described address counter reception self buffer memory, when the valid data length of self buffer memory be zero and input signal when effective input data entity from the outside receive data, data cached and export the Date Conversion Unit that self connects to; Address counter is used to monitor the read-write operation of the storer that self connects, and writes down the valid data length of this memory buffer and exports this storer to.
Equally, described input data entity can be the data buffer storage unit that connects between the Date Conversion Unit in the chip emulation platform, the store status of the data buffer storage unit output that then described input signal can connect for described Date Conversion Unit input end, described input signal is described store status non-NULL effectively, and described input signal is invalid to be that described store status is for empty.
Data reception module of the present invention can independently be arranged at outside the described Date Conversion Unit; Perhaps, be integrated among the described Date Conversion Unit.
In sum, use the data processing correctness that Date Conversion Unit of the present invention and its implementation and data reception module can guarantee the Date Conversion Unit of chip emulation platform, avoid the appearance of problems such as loss of data, mistake processing.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.All any modifications of being done within the spirit and principles in the present invention, be equal to replacement, improvement etc., all be included in protection scope of the present invention.
Claims (5)
1. a Date Conversion Unit is characterized in that, this Date Conversion Unit comprises:
Converter wherein is packaged with algorithm process, be used for from outside receiving inputted signal and output signal, input signal effectively and output signal receive data from data reception module when invalid and carry out algorithm process and output;
Data reception module is used for from outside receiving inputted signal, writes down the valid data length of self buffer memory, when the valid data length of self buffer memory be zero and input signal receive data from the outside when effective, buffer memory and output data are to described converter.
2. Date Conversion Unit according to claim 1 is characterized in that, described data reception module comprises:
Storer, be used for receiving described input signal from the outside, receive the valid data length of self buffer memory from address counter, when the valid data length of self buffer memory be zero and input signal receive data from the outside when effective, buffer memory and output data are to described converter;
Address counter is used to monitor the read-write operation of described storer, writes down the valid data length of this memory buffer and exports this storer to.
3. Date Conversion Unit according to claim 1 and 2, it is characterized in that, described input signal is the store status of the data buffer storage unit output of this Date Conversion Unit input end connection, described input signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit input end, and described input signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit input end is sky;
Described output signal is the store status of the data buffer storage unit output of this Date Conversion Unit output terminal connection, described output signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit output terminal, and described output signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit output terminal is sky.
4. the implementation method of a Date Conversion Unit, this method comprises: be packaged with algorithm process in the described Date Conversion Unit, the data that receive are carried out packaged algorithm process and output; It is characterized in that:
Further receiving inputted signal of described Date Conversion Unit and output signal;
This Date Conversion Unit further data of receiving of buffer memory before data are carried out algorithm process, and write down the valid data length of self buffer memory;
The method that described Date Conversion Unit receives data is: when the valid data length of self buffer memory be zero and input signal receive data when effective;
The method that described Date Conversion Unit carries out algorithm process to the data that receive is: when input signal effectively and output signal when invalid, self data in buffer is carried out algorithm process.
5. method according to claim 4, it is characterized in that, described input signal is the store status of the data buffer storage unit output of this Date Conversion Unit input end connection, the store status non-NULL that the data buffer storage unit that described input signal effectively connects for the Date Conversion Unit input end is exported, the invalid store status of exporting for the data buffer storage unit of Date Conversion Unit input end connection of described input signal is empty;
Described output signal is the store status of the data buffer storage unit output of this Date Conversion Unit output terminal connection, described input signal effectively is the store status non-NULL of the data buffer storage unit output that connects of this Date Conversion Unit output terminal, and described input signal is invalid be that the store status of the data buffer storage unit output that connects of this Date Conversion Unit output terminal is sky.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510023083 CN1794244B (en) | 2005-12-26 | 2005-12-26 | Data conversion unit and its implementing method and data receiving module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510023083 CN1794244B (en) | 2005-12-26 | 2005-12-26 | Data conversion unit and its implementing method and data receiving module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1794244A CN1794244A (en) | 2006-06-28 |
| CN1794244B true CN1794244B (en) | 2010-09-15 |
Family
ID=36805678
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510023083 Expired - Fee Related CN1794244B (en) | 2005-12-26 | 2005-12-26 | Data conversion unit and its implementing method and data receiving module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1794244B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191420A (en) * | 1997-01-31 | 1998-08-26 | 冲电气工业株式会社 | Serial-to-parallel converter |
-
2005
- 2005-12-26 CN CN 200510023083 patent/CN1794244B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1191420A (en) * | 1997-01-31 | 1998-08-26 | 冲电气工业株式会社 | Serial-to-parallel converter |
Non-Patent Citations (2)
| Title |
|---|
| 容晓峰，周利华，钟联炯.网络接口控制器(NIC)的缓冲区管理技术研究.计算机工程与应用 19.2001,(19),正文第70页右栏第18行-第72页左栏第20行. |
| 容晓峰,周利华,钟联炯.网络接口控制器(NIC)的缓冲区管理技术研究.计算机工程与应用 19.2001,(19),正文第70页右栏第18行-第72页左栏第20行. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1794244A (en) | 2006-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110603528B (en) | Debugging system and method | |
| CN100565472C (en) | A kind of adjustment method that is applicable to multiprocessor karyonide system chip | |
| US8234624B2 (en) | System and method for developing embedded software in-situ | |
| CN102480467B (en) | A kind of SOC software and hardware cooperating simulation verification method of communications protocol Network Based | |
| CN101504692B (en) | System and method for validating and testing on-chip system | |
| US10180850B1 (en) | Emulating applications that use hardware acceleration | |
| CN109741774B (en) | Controller and method for realizing DDR3 burst based on FPGA on-chip RAM simulation | |
| CN115146568B (en) | Chip verification system and verification method based on UVM | |
| CN114818599A (en) | Chip simulation verification system | |
| CN115688676B (en) | TLM-based GPU joint simulation system | |
| CN115686655B (en) | Combined simulation system for GPU IP verification | |
| US7437282B2 (en) | Method and apparatus to provide alternative stimulus to signals internal to a model actively running on a logic simulation hardware emulator | |
| US7478027B2 (en) | Systems, methods, and media for simulation of integrated hardware and software designs | |
| US10705993B2 (en) | Programming and controlling compute units in an integrated circuit | |
| CN112434478B (en) | Method for simulating virtual interface of logic system design and related equipment | |
| US7131099B2 (en) | Method, apparatus, and computer program product for RTL power sequencing simulation of voltage islands | |
| CN102054088A (en) | Virtual platform for prototyping system-on-chip designs | |
| CN100524323C (en) | Data buffer storage unit and its implementing method | |
| CN111176926A (en) | IP (Internet protocol) core simulation system and simulation method based on double-port SRAM (static random Access memory) | |
| CN101281507A (en) | USB interface type DSP real-time simulation development system | |
| CN1794244B (en) | Data conversion unit and its implementing method and data receiving module | |
| CN101950276B (en) | Memory access unit and program performing method thereof | |
| CN109243650B (en) | Nuclear power station safety level instrument control system and method with configuration function based on FPGA | |
| CN103345377A (en) | FIFO storer control method and device | |
| US11106846B1 (en) | Systems and methods for emulation data array compaction |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100915 Termination date: 20111226 |