JP2001318123A - Fail data log writing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To write a required fail data log into a fail memory, to store even such data as not stored in a fail memory while counting the number of failures, and to write data effective for analysis of a failed device into a fail memory. SOLUTION: At the time of IC test by means of an IC tester, a counter 3 counts the number of failures included in each I/O data outputted from each I/O (PASS/FAIL) data output line of a device being measured. When a predetermined count is reached, a select FAIL number mask circuit 4 outputs a signal for masking I/O data and based on that signal, an address pointer control circuit 8 writes a fail data log, corresponding to a test pattern inputted to an I/O terminal, into the memory region of an address inputted to the address terminal ADD of a fail memory 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fail data log writing circuit for writing a fail data log into a fail memory used for analyzing a defective device.

[0002]

2. Description of the Related Art Generally, an analysis of a defective device is performed using a fail memory storing data obtained from a device under test tested by an IC tester. A fail memory used for analyzing a defective device is written with data by a fail data log writing circuit or the like, and stores address data, other data, expected value data, and I / O data from a device under test for each test pattern. are doing.

A conventional fail data log write circuit is:
The above-described data obtained for each test pattern is sequentially written to the fail memory.

[0004]

However, in the conventional fail data log writing circuit, data is sequentially written to the fail memory without discriminating whether or not the data to be written is necessary. When the capacity of the data became insufficient, necessary data could not be stored.

An object of the present invention is to write a fail data log required in a fail memory, count and store the number of failures even for data that is not stored in the fail memory, and store data effective for analyzing a defective device in the fail memory. Is to write.

[0006]

The present invention has the following features in order to achieve the above object. In the following description of the means, a configuration corresponding to the embodiment will be exemplified by parentheses as an example. Reference numerals and the like are reference numerals and the like in the drawings described later.

A first aspect of the present invention is a fail data log write circuit for writing a fail data log corresponding to a test pattern into a fail data log memory at the time of a test by an IC tester (for example, a fail data log write circuit shown in FIG. 1). In 1), each I / O of the device under test is
A real-time fail counter (for example, the counter 3 shown in FIG. 1) corresponding to each I / O (PASS / FAIL) data output from the (PASS / FAIL) data output line, and a fail count number of the real-time fail counter is constant. A mask circuit (for example, a select FAIL number mask circuit 4 shown in FIG. 1) for masking the I / O (PASS / FAIL) data of a certain number or more when the number reaches the predetermined number.

According to the first aspect of the present invention, in a fail data log writing circuit for writing a fail data log corresponding to a test pattern into a fail data log memory at the time of a test by an IC tester, the real-time fail counter includes a device to be measured. I / O (PASS / F)
AIL) Each I / O (P) output from the data output line
The mask circuit counts the number of FAILs corresponding to the ASS / FAIL) data, and when the number of fail counts of the real-time fail counter reaches a certain number, the mask circuit outputs the I / O (PASS / FAIL) data of the certain number or more. Mask it.

Therefore, when the number of fail counts counted by the real-time fail counter reaches a certain number, the I / O (PASS / FAIL) data can be masked by the mask circuit. Can be restricted.

According to a second aspect of the present invention, in the fail data log writing circuit according to the first aspect, the mask circuit is capable of arbitrarily selecting a constant for masking I / O (PASS / FAIL) data. A circuit (for example, the selector 41 shown in FIG. 3) is further provided, and a specific I / O
Focusing on O (PASS / FAIL) data, a fail data log is written in a fail data log memory.

According to the second aspect of the present invention, the constant number for masking the I / O (PASS / FAIL) data can be arbitrarily selected by the selector circuit, so that the specific I / O (PASS / FAIL) can be selected. Focusing on the data, a fail data log that is considered effective for analyzing a defective device can be written to the fail data log memory.

According to a third aspect of the present invention, in the fail data log writing circuit according to the first aspect, the real-time counter includes a first counting means for counting a high fail of I / O (PASS / FAIL) data (for example, , HIGH-FAIL counter 31) and I /
Second counting means (for example, LOW-FA) for counting LOW failures of O (PASS / FAIL) data
IL counter 32), and the mask circuit masks I / O (PASS / FAIL) data for each of the first counting means and the second counting means, and outputs fail data for HIGH / LOW. It is characterized in that the number of log writes is limited.

According to the third aspect of the present invention, the first counting means of the real-time counter includes an I / O (PA
SS / FAIL) data is counted as a HIGH fail, and the second counting means is an I / O (PASS / FAI).
L) Counting a LOW fail of data, the mask circuit masks I / O (PASS / FAIL) data for each of the first counting means and the second counting means, and outputs a fail data log for HIGH / LOW. The number of writes can be limited.

According to a fourth aspect of the present invention, in the fail data log writing circuit according to the first aspect, the real-time fail counter is provided for each I-to-I test for all test patterns.
It is characterized in that the number of failures of / O (PASS / FAIL) data is counted.

According to the fourth aspect of the present invention, the real-time fail counter can count the number of failures of each I / O (PASS / FAIL) data for all test patterns. The number of failures in the fail data log that is not included can be displayed on an external display device or the like, and it is also possible to perform an arbitrary detailed failure analysis on the device under test.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a fail data log writing circuit 1 according to the present invention will be described below in detail with reference to FIGS. First, the configuration will be described.

FIG. 1 is a block diagram showing a circuit configuration of a fail data log writing circuit 1 according to the present embodiment.

In FIG. 1, a fail data log writing circuit 1 includes a plurality of H-FAIL / Ls for separating each I / O data into H-FAIL and L-FAIL.
A FAIL separation circuit 2, a plurality of counters 3, a plurality of select FAIL number mask circuits 4, and a plurality of AND gates 5;
And an OR gate 6, an AND gate 7, an address pointer control circuit 8, and a fail memory 9.

A plurality of H-FAIL / L-FAIL separation circuits 2 are connected to an I / O (PASS / FAIL) data output line and an expected value data output line of a device under test of an IC tester (not shown), respectively. H-FAI
Each L / L-FAIL separation circuit 2 includes an AND gate 21 and an AND gate 22 shown in FIG.

The plurality of AND gates 21 are connected to the I / O (PASS / FA) of the device under test inputted from the IC tester.
The logical product of the (IL) data and the corresponding expected value data is calculated, and the calculation result is output to the H-FAIL counter 31.

The plurality of AND gates 22 are connected to the I / O (PASS / FA) of the device under test inputted from the IC tester.
IL) The logical product of the data and the inverted corresponding expected value data is calculated, and the calculation result is output to the L-FAIL counter 32.
Output to

The counter 3, as shown in FIG.
An AIL counter 31 and an L-FAIL counter 32 are provided.

The H-FAIL counter 31 synchronizes with a clock signal CLK input from a clock generation circuit (not shown) to output the signal A of the H-FAIL / L-FAIL separation circuit 2.
The H-FAIL signal (H-FAIL signal) input from the ND gate 21
FAIL number), and outputs the count value to the selected FAIL number mask circuit 4.

The L-FAIL counter 32 synchronizes with a clock signal CLK input from a clock generation circuit (not shown) to output the signal A of the H-FAIL / L-FAIL separation circuit 2.
The L-FAIL signal (L-FAIL signal) input from the ND gate 22
FAIL number), and outputs the count value to the selected FAIL number mask circuit 4.

By outputting the count value of each counter 3 to an external personal computer or the like via an interface (not shown), the number of failures of each I / O data can be added and displayed. The count value of each counter 3 is
You may make it display by LCD, LED, etc. via a data bus etc.

A plurality of select FAIL number mask circuits 4
Are connected to an I / O (PASS / FAIL) data output line of a device under test of an IC tester (not shown), and are connected by a selector 41, an AND gate 42, a flip-flop circuit 43, and a NOT circuit 44, as shown in FIG. Be composed.

The selector 41 has an H-FAIL counter 3
1 and the count value input from the L-FAIL counter 32 is a preset value (for example, when the number of fail data logs to be written to the fail memory 9 is 4 patterns for each I / O pin, At 3), an instruction signal “H” is output to the AND gate 42. When the count value is other than the set value, an instruction signal “L” is output.

The AND gate 42 calculates the logical product of the instruction signal input from the selector 41 and the I / O data of the device under test input from the IC tester, and outputs the operation result to the flip-flop circuit 43. I do.

The flip-flop circuit 43 includes a logical product signal input from the AND gate 42 and an enable signal E.
N (inverted output signal) is used as an input signal, and the AND signal input from the AND gate 42 is latched and output to the NOT circuit 44 in synchronization with the clock signal CLK. Further, the flip-flop circuit 43 has a reset signal terminal R, and can reset the flip-flop circuit 43 to an initial state in response to a reset signal input instruction.

The NOT circuit 44 inverts the latch signal input from the flip-flop circuit 43 and outputs the inverted signal to the AND gate 5.

A plurality of AND gates 5 are connected to I / Os (PASS / PASS /
FAIL) connected to the data output line, and the NOT circuit 4
The logical product of the inversion signal input from 4 and the I / O (PASS / FAIL) data of the device under test input from the IC tester is calculated, and the calculation result is output to the OR gate 6.

The OR gate 6 calculates the logical sum of the logical product signals input from the plurality of AND gates 5 and outputs the operation result to the AND gate 7.

The AND gate 7 calculates the logical product of the logical sum signal input from the OR gate 6 and the clock signal CLK, and outputs the calculation result to the address pointer control circuit 8 and the write enable terminal WE of the fail memory 9. Output.

The address pointer control circuit 8 is a circuit for designating a data write address of the fail memory 9 in accordance with the logical product signal input from the AND gate 7.
The address is output to the address terminal ADD of the fail memory 9.

The fail memory 9 has an I / O terminal, a write enable terminal WE, and an address terminal ADD, and is a memory for storing a fail data log.

An I / O terminal is an I / O (PASS / FAIL) of a device under test of an IC tester (not shown).
A data output line, an expected value data output line, an address data output line, and other data output lines are connected, and data is transmitted in synchronization with the clock signal CLK.

The write enable terminal WE responds to a logical product signal to which a signal from the AND gate 7 has been input.
The data connected to the O terminal is set in a writable state.

Further, the address terminal ADD stores a fail data log (address data, test pattern number, expected I / O data, I / O of the device under test) in the memory area of the input address by the address pointer control circuit 8. O (PASS / FAIL) data).

Next, the operation will be described. FIG. 4 shows the operation of each unit in the fail data log writing circuit 1 of FIG.
This will be described with reference to the timing chart shown in FIG.

In the case of measuring (testing) two devices to be measured having four I / O pins, each pin of the device to be measured is numbered from 0 to 7 and an IC tester (not shown). I / O of device under test (PASS / FAIL)
The data output line uses I / O0 data to I / O7 data.

In this embodiment, I / O1 data to I / O1
The / O3 data is an example where no FAIL occurs. Therefore, the data shown in the timing chart of FIG. 4 includes I / O0 data and I / O4 in which FAIL has occurred.
Data to I / O7 data, showing only operations corresponding to the I / O data. In addition, since the expected value data of each I / O is fixed at HIGH, H-FAIL / L-FA
The AND gate 21 and the L-FAIL counter 32 of the IL separation circuit 2 are not used. For this reason, the output data of the L-FAIL counter 32 is not shown in the timing chart of FIG.

In the timing chart of FIG.
Is I / O0 (PASS / FAIL) data, S2 to S5
Is I / O4-7 (PASS / FAIL) data, S6 is I / O0H-FAIL counter 31 output data, S7-
S10 is the output data of the I / O4-7H FAIL counter 31; S11 is the output data of the I / O0 select FAIL number mask circuit 4; S12-S15 is the output data of the I / O4-7 select FAIL number mask circuit 4; O0
AND gate 5 output data, S17 to S20 are I / O4
7 to 7 AND gate 5 output data. Also, the pulses of the clock signal CLK are numbered from 1 to 24, and the respective pulses are denoted by clock signals CLK'1 'to C
This will be described hereinafter as LK'24 '.

In FIG. 4, S1 indicates the FAIL signal as "H" and the PASS signal as "L". Also, S1
The initial state of the output data shown in S5, S7 to S11, and S17 to S22 is "L: low", and the initial state of the output data shown in S12 to S16 is "H: high".

In FIG. 1, when an IC test is started by an IC tester (not shown), the I
Test patterns 1 to 24 are transmitted to the / O terminal in synchronization with clock signals CLK'1 'to CLK'24' shown in FIG. Also, address data,
Other data, I / O expected value data,
/ O (PASS / FAIL) data is transmitted.

First, the operation at the time of the IC test in the test patterns 1 and 2, that is, when the clock signals CLK'1 'and CLK'2' are input to the fail data log writing circuit 1, will be described. At this time, all of the I / O (PASS / FAIL) data of the device under test shown in S1 to S5 output “L” indicating PASS because no FAIL occurs. Therefore, H-FAIL / LF
The FAIL signal is not output from the AIL separation circuit 2, and each part of the fail data log writing circuit 1 keeps the initial state. Therefore, the fail data logs of the test patterns 1 and 2 are not written in the fail memory 9.

Next, the IC in the test patterns 3 to 6
During the test, that is, when the clock signals CLK'3 'to CLK
The operation when “6” is input to the fail data log writing circuit 1 will be described. At this time, the I /
For O (PASS / FAIL) data, S1 is "H", S1
2 to S5 are “L”. Therefore, an “H” signal is input from S1 to the H-FAIL / L-FAIL separation circuit 2 corresponding to I / O0. This H-FAIL / L-FAI
The AND gate 21 of the L separation circuit 2 calculates the logical product of the I / O0 data S1 and the expected value data, and inputs an “H” signal to the H-FAIL counter 31. H-FAI
The L counter 31 outputs the “H” signal to the H-FAIL signal (H
-FAIL number), and count values (for example, count value for I / O0: 1 to 4, count value for I / O4: 0, count value for I / O5:
0, the count value for I / O6: 0, and the count value for I / O7: 0) are input to each selector 41.

The selector 41 for I / O0 is HF
The count value (1 to 1) input from the AIL counter 31
When 4) becomes a set value (for example, 3 when the number of fail data logs to be written to the fail memory 9 is 4 patterns for each I / O pin), the selector 41 outputs a predetermined instruction signal “H”. The AND gate 42 calculates the logical product of the instruction signal “H” from the selector 41 and the fourth count I / O 0 FAIL data S 1, and outputs the result to the flip-flop circuit 43. Since the flip-flop circuit 43 holds the initial state until the fourth count clock signal CLK'6 'is input, the output of the select FAIL number mask circuit 4 is
It outputs "H" which is the initial state. Further, CLK'6 '
Is input, the output of the select FAIL number mask circuit 4 is held at "L".

When the output of the selected FAIL number mask circuit 4 is "H", the AND gate 5 shown in FIG. 1 calculates the logical product of S1 and the output "H" of the selected FAIL number mask circuit 4 to obtain " H ”signal to the OR gate 6,
The logical sum is calculated by the gate 6, and the "H" signal is ANDed.
Output to gate 7. AND gate 7 is OR gate 6
Of the logical sum signal and the clock signal CLK which are input from the memory and outputs the "H" signal to the write enable terminal WE of the address pointer control circuit 8 and the fail memory 9.
Output to

When the "H" signal is input to the write enable terminal WE, the fail memory 9 becomes ready for writing data. Then, the fail data logs of the test patterns 3 to 6 inputted to the I / O terminals are sequentially written in the memory area of the address inputted to the address terminal ADD of the fail memory 9 by the address pointer control circuit 8.

When the output of the select FAIL number mask circuit 4 is "L", the AND gate 5 shown in FIG.
The logical AND of 1 and the output “L” of the select FAIL number mask circuit 4 is calculated, the “L” signal is output to the OR gate 6, the OR gate 6 calculates the logical sum, and the “L” signal is calculated. Output to AND gate 7. AND gate 7 is OR
The OR signal input from the gate 6 and the clock signal CL
An AND operation with K is performed to output an “L” signal to the address pointer control circuit 8 and the write enable terminal WE of the fail memory 9. Therefore, no data is written to the fail memory 9.

Next, I in test patterns 7 and 8
At the time of the C test, that is, the clock signals CLK'7 'and C
The operation when LK'8 'is input to the fail data log writing circuit 1 will be described. At this time, in the I / O (PASS / FAIL) data of the device under test, S1 is “H” and S2 to S5 are “L”. Therefore, the "H" signal from S1 changes to H-FAIL / L- corresponding to I / O0.
It is input to the FAIL separation circuit 2. H-FAIL / L-
In the AND gate 21 of the FAIL separation circuit 2, I /
The logical product of the O0 data S1 and the expected value data is calculated,
The “H” signal is input to the H-FAIL counter 31. H
-The FAIL counter 31 outputs the "H" signal to the H-FAIL
The signal is counted as a signal (the number of H-FAILs), and the count value (for example, a count value for I / O0: 5 to 6,
Count value for O4: 0, count value for I / O5: 0, count value for I / O6: 0, I / O7
Is input to each selector 41.

At this time, the selector 41 for I / O0
When a count value (for example, 5, 6) is input from the H-FAIL counter 31, a predetermined instruction signal is ANDed.
The signal is output to the gate 42, and the instruction signal “L” from the selector 41 and the I / O0 data S1 “H” are output by the AND gate 42.
And outputs "L" to the flip-flop circuit 43. Then, the flip-flop circuit 43
When the clock signal CLK'7 'is input, CLK
Since the output state when '6' is input is retained,
“H” is output to the NOT circuit 44. NOT circuit 44 inverts the input latch signal and outputs “L” to AND gate 5.

Therefore, similarly to the operation after the input of CLK'6 '(that is, when the output of mask circuit for selecting FAIL number 4 is "L"), AND gate 5 sets I / O
The logical product of the / O0 data S1 and the output “L” signal of the select FAIL number mask circuit 4 is calculated, and the “L” signal is output
The signal is output to the R gate 6, the OR is calculated by the OR gate 6, and the “L” signal is output to the AND gate 7. AND
The gate 7 calculates the logical product of the logical sum signal input from the OR gate 6 and the clock signal CLK, and outputs an “L” signal to the address pointer control circuit 8 and the write enable terminal WE of the fail memory 9. Therefore, the fail data logs of the test patterns 7 and 8 are not written in the fail memory 9.

Next, the operation at the time of the IC test in the test pattern 9, that is, when the clock signal CLK'9 'is input to the fail data log writing circuit 1, will be described. At this time, the I / O (PASS / FA)
IL) data is “H” for S1, S4, S5, S6, S
7 is “L”. For this reason, the "H" signals from S1, S4, and S5 change the H-FAIL / L-FA corresponding to the I / O.
Input to the IL separation circuit 2. In the AND gate 21 of the H-FAIL / L-FAIL separation circuit 2 corresponding to S1, S4, and S5, the logical product of each I / O data and expected value data is calculated, and the "H" signal is output to the H-FAIL counter. 3
Enter 1 The H-FAIL counter 31 counts the “H” signal as an H-FAIL signal (H-FAIL number), and counts (eg, a count value for I / O0: 7, a count value for I / O4: 1, I). Count value for / O5: 1, count value for I / O6:
0, the count value for the I / O 7: 0) is input to each selector 41.

When the count value is input, the selector 41 of the select FAIL number mask circuit 4 for I / O0
Outputs a predetermined instruction signal to an AND gate 42,
In the AND gate 42 to the NOT circuit 44 for O0, the same operation as the above-mentioned CLK'7 'is performed, and the "L" signal is output to the AND gate 5.

When the count value is input to the selector 41 of the select FAIL number mask circuit 4 for the I / O 4 and I / O 5, the count value input from the H-FAIL counter 31 is set to the set value (for example, 4 ) Hold the output data until it becomes greater than or equal to. Therefore, select FAI
The NOT circuit 44 of the L number mask circuit 4 outputs an “H” signal similar to the initial state to the AND gate 5.

In the AND gate 5, the logical product of the I / O0 data S1 and the output "L" signal of the select FAIL number mask circuit 4 is calculated, and the "L" signal is output to the OR gate 6. Also, I / O4 data S2 and select FAI
The logical AND with the output “H” signal of the L number mask circuit 4 is calculated, and the “H” signal is output to the OR gate 6. Also, I /
The logical product of the O5 data S3 and the output “H” signal of the select FAIL number mask circuit 4 is calculated, and the “H” signal is ORed.
Output to gate 6.

The OR gate 6 calculates the logical sum from the AND gate 5 described above and outputs an "H" signal to the AND gate 7. The AND gate 7 calculates the logical product of the logical sum signal input from the OR gate 6 and the clock signal CLK, and outputs an “H” signal to the address pointer control circuit 8 and the write enable terminal WE of the fail memory 9. .

When the "H" signal is input to the write enable terminal WE, the fail memory 9 enters a state in which data can be written. Then, the fail data log of the test pattern 9 inputted to the I / O terminal is written into the memory area of the address inputted to the address terminal ADD of the fail memory 9 by the address pointer control circuit 8.

Similarly, the operation at the time of the IC test in the test pattern 9, that is, the operation when the clock signal CLK'10 'is input to the fail data log write circuit 1 will be described. At this time, the I / O (PASS /
FAIL) data is “H” for S1, S6 and S7, S
4. S5 is "L". Therefore, S1, S6, S7
From the H-FAIL / L- corresponding to the I / O
It is input to the FAIL separation circuit 2. AN of H-FAIL / L-FAIL separation circuit 2 corresponding to S1, S6, S7
In the D gate 21, the logical product of each I / O data and the expected value data is calculated, and an “H” signal is input to the H-FAIL counter 31. The H-FAIL counter 31
The “H” signal is counted as an H-FAIL signal (H-FAIL number), and the count value (for example, the count value for I / O0: 8, the count value for I / O4: 1, I
The count value for / O5: 1, the count value for I / O6: 1, and the count value for I / O7: 1) are input to each selector 41.

When the count value is input, the selector 41 of the select FAIL number mask circuit 4 for I / O0
Outputs a predetermined instruction signal to an AND gate 42,
In the AND gate 42 to the NOT circuit 44 for O0, the same operation as the above-mentioned CLK'7 'is performed, and the "L" signal is output to the AND gate 5.

When the count value is input to the selector 41 of the select FAIL number mask circuit 4 for the I / O 6 and I / O 7, the count value input from the H-FAIL counter 31 is set to the set value (for example, 4 ) Hold the output data until it becomes greater than or equal to. Therefore, select FAI
The NOT circuit 44 of the L number mask circuit 4 outputs an “H” signal similar to the initial state to the AND gate 5.

In the AND gate 5, the logical product of the I / O0 data S1 and the output "L" signal of the select FAIL number mask circuit 4 is calculated, and the "L" signal is output to the OR gate 6. Also, I / O6 data S4 and select FAI
The logical AND with the output “H” signal of the L number mask circuit 4 is calculated, and the “H” signal is output to the OR gate 6. Also, I /
The logical product of the O7 data S5 and the output “H” signal of the select FAIL number mask circuit 4 is calculated, and the “H” signal is ORed.
Output to gate 6.

Then, in the OR gate 6 to the address pointer control circuit 8, the same operation as the above-mentioned CLK'9 'is performed, and the memory area of the address input to the address terminal ADD of the fail memory 9 by the address pointer control circuit 8 is The test pattern 1 input to the I / O terminal
Write a fail data log of 0.

Further, at the time of the IC test in the test patterns 11 to 20, that is, the clock signals CLK'11 'to
The operation when CLK'20 'is input to the fail data log write circuit 1 will be described. At this time, in the I / O (PASS / FAIL) data of the device under test, S1 is “H” and S4, S5, S6, and S7 are “L”. Therefore, an “H” signal is input from S1, S6, and S7 to the H-FAIL / L-FAIL separation circuit 2 corresponding to the I / O. The AN of the H-FAIL / L-FAIL separation circuit 2
In the D gate 21, the logical product of the I / O0 data S1 and the expected value data is calculated, and an “H” signal is input to the H-FAIL counter 31. The H-FAIL counter 31
The "H" signal is counted as an H-FAIL signal (H-FAIL number), and the count value (for example, the count value for I / O0: 9 to 18, the count value for I / O4:
1, count value for I / O5: 1, count value for I / O6: 1, count value for I / O7: 1)
Is input to each selector 41.

At this time, the selector 4 corresponding to I / O0
When a count value (for example, 9 to 18) is input from the H-FAIL counter 31, a predetermined instruction signal is set to AN.
Output to the D gate 42.

Then, similarly to the operation of CLK '7' and '8', AND gate 5 to address pointer control circuit 8
The operation up to is performed. Therefore, the test patterns 11 to
The fail data log 20 is not written in the fail memory 9.

Similarly, the IC in the test pattern 21
The operation at the time of the test, that is, when the clock signal CLK'21 'is input to the fail data log write circuit 1 will be described. At this time, the I / O (PASS
/ FAIL) data is “H” for S1, S4, S5, S
6, S7 is "L". For this reason, the "H" signal from S1 and S4 changes to H-FAIL / L-FA corresponding to I / O.
Input to the IL separation circuit 2. H corresponding to S1, S4
-AND gate 2 of FAIL / L-FAIL separation circuit 2
At 1, the logical product of each I / O data and expected value data is calculated, and an “H” signal is input to the H-FAIL counter 31. The H-FAIL counter 31 outputs the “H” signal to H
Counting as a FAIL signal (H-FAIL number),
Count value (for example, count value for I / O0: 1
9, count value for I / O4: 2, count value for I / O5: 1, count value for I / O6: 1,
The count value for I / O 7: 1) is input to each selector 41.

When the count value is input, the selector 41 of the select FAIL number mask circuit 4 for I / O0
Outputs a predetermined instruction signal to an AND gate 42,
In the AND gate 42 to the NOT circuit 44 for O0, the same operation as the above-mentioned CLK'7 'is performed, and the "L" signal is output to the AND gate 5.

Select FAIL for I / O4
When the count value is input, the selector 41 of the number mask circuit 4 holds the output data until the count value input from the H-FAIL counter 31 exceeds a set value (for example, 4). Therefore, the NOT circuit 44 of the select FAIL number mask circuit 4 outputs an “H” signal similar to the initial state to the AND gate 5.

In the AND gate 5, the logical product of the I / O 0 data S 1 and the output “L” signal of the select FAIL number mask circuit 4 is calculated, and the “L” signal is output to the OR gate 6. Also, I / O4 data S2 and select FAI
The logical AND with the output “H” signal of the L number mask circuit 4 is calculated, and the “H” signal is output to the OR gate 6. Also, I /
The logical product of the O5 data S3 and the output “H” signal of the select FAIL number mask circuit 4 is calculated, and the “H” signal is ORed.
Output to gate 6.

In the OR gate 6 to the address pointer control circuit 8, the same operation as the above-mentioned CLK ′ 9 ′ is performed, and the memory area of the address input to the address terminal ADD of the fail memory 9 by the address pointer control circuit 8 is stored. The fail data log of the test pattern 21 input to the I / O terminal is written.

Similarly, at the time of IC test in test patterns 22 to 24, that is, clock signal CLK'21 '
To CLK'24 'are input to the fail data log write circuit 1 in the same manner as the above-described operation.
The “H” signal is counted as an H-FAIL signal (the number of H-FAIL) by the AIL counter 31, and the count value (for example, the count value for I / O0: 19 to 22,
Count value for I / O4: 2, count value for I / O5: 2, count value for I / O6: 1-2,
The count value for I / O7: 1) to 2) is assigned to each selector 4
Enter 1 Therefore, similarly to the operation described above, I / O
Since a predetermined instruction signal is output from the selector 41 for 0 and no signal is output from the selector 41 for I / Os 4 to 7, the output signal of the select FAIL number mask circuit 4 for I / O 0 is “L”, I / O The output signal of the select FAIL number mask circuit 4 for O4 to O7 is "H".
Is output, and “H” is output from the AND gate 5 to the I / Os 4 to 7 to the OR gate 6. Then, a signal synchronized with the clock signals CLK'22 'to CLK'24' is input to the write enable terminal WE, so that the fail memory 9 is in a state where data can be written. Then, CLK'22 'to CLK'2 input to the I / O terminal are stored in the memory area of the address input to the address terminal ADD of the fail memory 9 by the address pointer control circuit 8.
When 4 'is input, fail data logs of the test patterns 22 to 24 are sequentially written.

As described above, in the fail data log writing circuit 1 of this embodiment, the test patterns 1 to
24, when FAIL data is generated as a result of the IC test, the I / O from the device I / O (PASS / FAIL) output line is output.
(PASS / FAIL) data is input to the fail log writing circuit 1 and input to the H-FAIL / L-FAIL separation circuit 2. And H-FAIL / L-FAIL
By the separation circuit 2, F-FAIL and L-FAIL
AIL signals are separated, and the separated signals are respectively converted into H-FA signals.
Output to the IL counter 31 and the L-FAIL counter 32. Each counter has test patterns 1 to 24
Clock signals CLK'1 'to CLK'24' synchronized with
The count value is output to the selector 41 every time the
1 keeps the initial state until the count value reaches the set value based on the set value and outputs the instruction signal “L”. Then, when the count value reaches the set value, an instruction signal “H” is output. Each part of the select FAIL number mask circuit operates according to this instruction signal, and outputs a signal for limiting the number of FAILs to the AND gate 5. And OR gate 6
Calculates the logical sum of the output signals from the AND gate 5 and outputs the result to the AND gate 7. The AND gate 7 calculates the logical product of the clock signal CLK and the logical sum signal from the OR gate 6, and outputs a signal to the address pointer control circuit and the write enable terminal WE of the fail memory 9.

FIG. 5 shows an I / O (PASS) of pins 0 to 7 corresponding to the device under test of test patterns 1 to 24.
FIG. 14 is a diagram showing the result of (/ FAIL) data.

FIG. 6 shows a fail data log stored in the fail memory 9 in this embodiment. Of the test patterns 1 to 24, 10 patterns (3 to 6,
9/10, 21/24) (PASS / F)
AIL) data is stored. Comparing the results of FIG. 5 with those of FIG. 6, it can be seen that the number of fail data logs shown in FIG. 6 is limited.

FIG. 7 is a diagram showing an output example when the count value of the counter 3 is output from an external personal computer or the like via an interface (not shown). FIG. 7 shows the number of FAILs of each pin of the device under test. I / O0 (P
ASS / FAIL) data indicates that the number of failures is 22,
O1-3 (PASS / FAIL) data has 0 failures, and I / O4-7 (PASS / FAIL) data has
This indicates that there are two failures.

Therefore, the number of pieces of FAIL data based on the set value of the selector can be written into the fail memory 9, so that data effective for analyzing a defective device can be written into the fail memory 9. In addition, since data that is not written to the fail memory 9 can be displayed by an external display device, it is possible to perform an arbitrarily detailed fail analysis on the device under test.

In the above embodiment, the setting value of the selector 41 is set to 3, but the present invention is not limited to this, and an arbitrary setting value may be used.

The select FAIL number mask circuit 4
Is provided for each I / O (PASS / FAIL) data, but is provided for each of the H-FAIL counter 31 and the L-FAIL counter 32.
The write restriction for each L may be enabled.

[0081]

According to the first aspect of the present invention, when the number of fail counts counted by the real-time fail counter reaches a certain number, I / O (PASS / FAI) is performed.
L) Since the data can be masked by the mask circuit, the number of data to be written to the fail data log memory can be limited.

According to the second aspect of the present invention, a certain constant for masking I / O (PASS / FAIL) data can be arbitrarily selected by the selector circuit.
Paying attention to / O (PASS / FAIL) data, a fail data log considered effective for analyzing a defective device can be written to the fail data log memory.

According to the third aspect of the present invention, the HIGH fail can be counted by the first counting means of the real-time counter, and the LO failure can be counted by the second counting means.
W failures can be counted, and the mask circuit allows the I / O for each of the first counting means and the second counting means.
O (PASS / FAIL) data is masked and HIGH
The number of failed data log writes can be limited for each LOW.

According to the fourth aspect of the present invention, the real-time fail counter is provided for each I pattern for all test patterns.
Since the number of fail of / O (PASS / FAIL) data can be counted, the number of fail of the fail data log which is not written in the fail data log memory can be displayed by an external display device or the like, and the number of failed devices to be measured can be measured. Arbitrarily detailed failure analysis can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a fail data log writing circuit 1.

FIG. 2 is a diagram showing a circuit configuration of an H-FAIL / L-FAIL separation circuit 2 and a counter 3;

FIG. 3 is a diagram showing a circuit configuration of a select FAIL number mask circuit 4;

FIG. 4 is a timing chart showing an operation of each unit of the fail data log writing circuit 1;

FIG. 5 is a diagram showing results of I / Os 0 to 7 data of pins 0 to 7 corresponding to devices under test of test patterns 1 to 24;

FIG. 6 is a fail data log stored in a fail memory 9 in the embodiment.

FIG. 7 is a display example in which the number of FAILs is displayed on an external display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Fail data log write circuit 2 Separation circuit 21 AND gate 22 AND gate 3 Counter 31 H-FAIL counter 32 L-FAIL counter 4 Select fail number mask circuit 41 Selector 42 AND gate 43 Flip-flop circuit 44 NOT circuit 5 AND gate 6 OR Gate 7 AND gate 8 Address pointer control circuit 9 Fail memory

Claims (4)

[Claims] In a fail data log writing circuit for writing a fail data log corresponding to a test pattern into a fail data log memory at the time of a test by an IC tester, each I / O (PASS / FAIL) data output line of a device under test is provided. I / O (PASS / FA) output from
IL) a real-time fail counter corresponding to the data; and, when the number of fail counts of the real-time fail counter reaches a certain number, the I / O of the certain number or more.
And a mask circuit for masking (PASS / FAIL) data. 2. The method according to claim 1, wherein the mask circuit includes an I / O (PASS / F).
And a selector circuit that can arbitrarily select a constant for masking AIL (AIL) data.
2. A fail data log writing circuit according to claim 1, wherein a fail data log is written into a fail data log memory paying attention to (S / FAIL) data. 3. The real-time counter includes an I / O (P
First counting means for counting a HIGH fail of ASS / FAIL data, and I / O (PASS / FAIL)
IL) data, and a second counting means for counting a LOW fail of the data, and the mask circuit further comprises an I / O (PASS / FAIL) data for each of the first counting means and the second counting means. 2. The fail data log writing circuit according to claim 1, wherein the number of failed data log writes is limited for each of HIGH and LOW. 4. The real-time fail counter is provided for each I / O (PASS / FAI) for all test patterns.
2. The fail data log write circuit according to claim 1, wherein the number of data failures is counted.