JPH10336253A - Signal line monitor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal line monitor by which the validity of a relative time of two optional signal lines is measured among pluralities of signal lines. SOLUTION: A minimum value counter 4 and a maximum value counter 5 monitor a valid time of two optional signal lines among pluralities of signal lines a-n, and a relative signal error discrimination section 9 compares the counts with a specified value of the valid time between the signals set in advance so as to discriminate whether or not the measured values are within a specified value. In the case that the measured value is at the outside of the specified value, a red LED 11 is lighted to inform the error for the operator and an error information register 10 stores a name of the compared signal and error information as to whether or not the time is less than the specified time or in excess of the specified time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal line monitoring device, and more particularly, to a signal line monitoring device for monitoring a relative effective time of any two signal lines.

[0002]

2. Description of the Related Art In a conventional signal line monitoring apparatus of this type, the state of a signal line is latched at a specific sampling period or at a specific timing, and the state is stored in a memory or the like, and a failure state occurs. There is a signal line monitoring device like a flight recorder, which aims to collect fault information later when it occurs. Apart from this, there is also a signal line monitoring device that displays the status on an external display when the value on the address bus becomes a preset value. In a device that monitors the valid time of a signal line in the device, the valid time of one signal line is monitored, and when the time is less than a predetermined time or exceeds a predetermined time. Alarm is output to and detected.

[0003]

As described above, the conventional signal line monitoring apparatus latches the state of a plurality of signal lines at a certain timing and records the state in a temporary storage device such as a memory. Instantaneous signal line status monitoring,
This is intended to be used as a means of searching for a failure when a failure state is entered.

Further, there is a device for detecting an analog delay of a single signal line as disclosed in Japanese Patent Application No. 5-180555. However, when a bus master communicates with a bus slave, a plurality of devices are usually used. The definition of the relative time of the signal is problematic. Each signal line from the bus master passes through another TTL element or LSI on the way, and its line length is not constant. It is affected by the pattern condition on the board and the presence or absence of pull-up. It depends on each signal line.

Therefore, even if a plurality of signals are transmitted with a prescribed effective time, if a signal is received by a bus slave, it may not always be possible to receive the signal at the prescribed time. . Therefore, even if the device operates without any problem in the operation in the normal environment, the variation in the drive elements, the increase in the bus load due to the increase in the number of bus slaves,
The effective time of the signal line may be extended due to an analog factor such as a temperature condition, and a failure may occur at the time of a competitive operation or the like.

[0006] Since such a failure is not a digital factor, it takes a lot of effort and time to find a bug.
You have to do very inefficient debugging.

It is an object of the present invention to provide a signal line monitoring device which enables effective measurement of the relative time of any two signal lines out of a plurality of signal lines.

[0008]

SUMMARY OF THE INVENTION A signal line monitoring apparatus according to the present invention comprises a selecting means for selecting a basic signal line and a comparison signal line from a plurality of signal lines, respectively, and a selected basic signal line and a comparison signal line. The maximum value register and the minimum value register for setting the maximum value and the minimum value of the relative valid specified time respectively, and the value time set in the maximum value register and the minimum value register when the validity of the basic signal line is used as a trigger. A maximum value counter and a minimum value counter to count, a crystal oscillator that supplies a basic clock pulse to the maximum value counter and the minimum value counter, and a value outside the specified time from the results of the maximum value counter and the minimum value counter and the value of the comparison signal line. A relative signal error determination unit for determining an error when the error has occurred, and error information for storing error information from the relative signal error determination unit And having a register, a LED for displaying the error determined in the relative signal error determining unit.

[0009] The selecting means includes a first selector for selecting a basic signal line from a plurality of signal lines, a second selector for selecting a comparison signal line from a plurality of signal lines, and Each of the first and second selectors includes a selector control unit for selecting the basic signal line and the comparison signal line.

In addition, the maximum value and the minimum value to be set in the maximum value register and the minimum value register, and control to the selector control unit for selecting a basic signal line and a comparison signal line from a plurality of signal lines. It is preferable that the writing of the setting value is performed by either writing by a control order from the outside or writing by reading from a ROM connected to the outside.

[0011]

According to the present invention, the valid time of any two signal lines between the bus master and the bus slave is monitored and compared with a predetermined specified value of the valid time between each signal, so that the value is within the specified value. Judge whether the error is out of the specified range, notify the operator of the error by LED, and hold the signal name compared with the error information register and the error information indicating whether the time is less than the specified time or exceeded the specified time. At the time of system design, it is possible to find a non-digital bug of a device at an early stage, and at the time of actual operation, it is possible to construct a system with high reliability.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the signal line monitoring device of the present invention. The signal line monitoring device includes a first selector 1 for selecting a basic signal line from a plurality of arbitrary signal lines a to n, and a second selector for selecting a comparison signal line for comparison with a basic signal line. Selector 2,
A selector control unit 3 for controlling the first and second selectors 1 and 2; a minimum value counter 4 and a maximum value counter 5 which start counting when the basic signal line is effectively changed; a basic cycle of the signal line A crystal oscillator 6 for generating a counter clock pulse for operating the counter earlier and providing a fundamental frequency to each counter, a minimum value register 7 for setting the counter value of the minimum value counter 4, and a counter for the maximum value counter 5 A maximum value register 8 for setting a value, a relative signal error determination unit 9 for determining an error based on the value of the comparison signal line at the time when the count of the minimum value counter 4 is completed and at the time of completion of the count of the maximum value counter 5, and stores error information. An error information register 10, a red LED 11 for displaying a red lamp when an error occurs, and a green for displaying a green lamp when normal. It consists of ED12.

First, an error determination operation in the relative signal error determination section 9 for the basic signal line a selected by the first selector 1 and the comparison signal line b selected by the second selector 2 will be described. FIG. 2 shows a time chart of the two signal lines a and b. In FIG. 2, these two signal lines a and b are valid when they are at L (low level).

FIG. 3 shows an algorithm for error determination in the relative signal error determination section 9. First, when the basic signal line a becomes valid in step S1, the minimum value counter 4 and the maximum value counter 5 start counting up to the counter values set in the preset minimum value register 7 and maximum value register 8 (step S2). . When the minimum value counter 4 stops at step S3, the relative signal error determination unit 9 checks the value of the comparison signal line b (step S4). If the value is valid, it is determined that the value has become valid earlier than the specified time. In step S5, it is determined that an error has occurred, the red LED 11 is turned on, and error information indicating that the compared signal line name is shorter than the specified time is written in the error information register 10.

If the comparison signal line b is not valid in step S4, the relative signal error determination unit 9 stops the comparison signal line b when the maximum value counter 5 stops in step S6.
(Step S7), if it is not valid, it is determined that it has not become valid within the specified time and an error is determined (Step S8). Then, in step S8, the red LED 11 is turned on, and the compared signal name and error information indicating that the specified time is exceeded are written in the error information register 10. If the comparison signal line b is not valid in step S7, it is determined that the signal is normally valid at the specified time, and the green LED 12 is turned on in step S9.

The writing of the respective values of the minimum value register 7 and the maximum value register 8 in the signal line monitoring device is performed as follows.
The data may be written from a personal computer or the like using an interface such as RS232C, or data may be written in a ROM or the like in advance and automatically read therefrom. Similarly, the selector control unit 3 for selecting the basic signal line and the comparison signal line may be externally controlled by a personal computer, or may be selected according to information described in advance in a ROM or the like. good. In any case, when the information of the basic signal line to be selected and the comparison signal line is given to the selector control unit 3, the set values of the minimum value register 7 and the maximum value register 8 are simultaneously written according to the selected signal line. Can be replaced. The minimum value counter 4 and the maximum value counter 5 are reset by the relative signal error determination unit 9.

FIG. 4 shows a specific example of a device configuration using the present signal line monitoring device. FIG. 4 shows a general microprocessor 13 (hereinafter referred to as μP), a decoder 14, and a RAM 1
This is an example in which the signal line monitoring device 16 is applied to a RAM access circuit composed of a RAM 5.

The bus master and the bus slave described so far correspond to the μP 13 and the bus slave corresponds to the RAM 15 in this example. Signal lines are an AS (address strobe) signal line, a DS (data strobe) signal line, a R / W (read / write) signal line,
General signal lines such as a CK (acknowledge) signal line, a CS (chip select) signal line, and a WE (write enable) signal line correspond thereto.

When the system is started, the signal line monitoring device 16 receives the selector control unit 3, the maximum value register 8,
The initial data (the signal line to be selected, the counter value of the minimum value counter 4 and the counter value of the maximum value counter 5 of the specified value) are written in the minimum value register 7. In this configuration example, the data is written by a personal computer or the like using an externally connected RS232C or the like.
It is also possible to use a method in which the signal line monitoring device 16 automatically writes the data in the OM or the like and then automatically reads it.

In this example, the operation will be described with the signal from the AS signal line transmitted by the bus master μP 13 as a basic signal and the signal from the CS signal received by the RAM 15 as a bus slave as a comparison signal.

Normally, when designing a circuit, a time chart is created and the timing regulation between signals is defined. As shown in FIG. 5, the signal timing of the CS signal line becomes 1 CL after the AS signal line becomes valid (in this case, L).
Suppose that it must become valid within 3 CLK after K (clock). The crystal oscillator 6 in the signal line monitoring device 16 is set to a CLK that is sufficiently faster than the basic CLK. In this example, the speed is five times faster than the basic CLK.

In this case, an instruction from the outside to the selector control unit 3 is made up of a basic signal line: an AS signal line and a comparison signal line: CS.
Signal line, minimum value register setting value: 5, maximum value register setting value: 15

The minimum value counter 4 in the signal line monitoring device 16
The maximum value counter 5 starts counting when the AS signal line becomes valid (L). When the count value of the minimum value counter 4 becomes “5”, the relative signal error determination unit 9 is notified. The relative signal error determination unit 9 looks at the value of the CS signal line, and if it is valid, it starts from the specified time. The red LED 11 is turned on and the error information indicating that the compared signal names AS and CS are shorter than the specified time is written in the error information register 10. If it is not valid, the relative signal error determination unit 9 is notified when the count value of the maximum value counter 5 becomes “15”, and the relative signal error determination unit 9 is enabled by checking the value of the CS signal line. If not, it is determined that it has not become valid within the specified time, the red LED 11 is ignited, and the compared signal names AS and CS and error information indicating that the specified time has been exceeded are written in the error information register 10. If it is not valid, the green LED 12 is turned on assuming that the signal is valid at the specified time.

[0024]

As described above, according to the present invention, the relative time of any two signal lines out of a plurality of signal lines can be effectively measured, and the relative time due to analog factors which cannot be found by simulation or the like at the time of designing the device. Circuit bugs can be found early. Further, the signal line sequence of the entire apparatus is clarified by measuring the effective time of the signal line, and a system configuration that maintains high reliability during actual operation becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a signal line monitoring device according to the present invention.

FIG. 2 is a waveform chart for explaining the definition of a relative time between two signals in the present invention.

FIG. 3 is a flowchart showing an algorithm for determining an error relating to the effective time of two signal lines according to the present invention.

FIG. 4 is a configuration diagram showing an application example of the signal line monitoring device according to the present invention.

FIG. 5 is a waveform chart for explaining the definition of the relative time between the AS signal line and the CS signal line in FIG. 4;

[Explanation of symbols]

 1, 2 First and second selector 3 Selector control unit 4 Minimum value counter 5 Maximum value counter 6 Crystal oscillator 7 Minimum value register 8 Maximum value register 9 Relative signal error determination unit 10 Error information register 11 Red LED 12 Green LED 13 Microprocessor (μP) 14 Decoder 15 RAM 16 Signal line monitoring device

Claims (3)

[Claims] 1. A selecting means for selecting a basic signal line and a comparison signal line from a plurality of signal lines, respectively, and setting a maximum value and a minimum value of a relative effective specified time of the selected basic signal line and the comparison signal line, respectively. A maximum value register and a minimum value register for setting; a maximum value counter and a minimum value counter for counting a value time set in the maximum value register and the minimum value register when the validity of the basic signal line is used as a trigger; A crystal oscillator that supplies a basic clock pulse to the value counter and the minimum value counter; and a relative signal error determination unit that determines an error when the result of the maximum value counter and the minimum value counter and the value of the comparison signal line fall outside a specified time. An error information register for storing error information from the relative signal error determination unit; and a determination by the relative signal error determination unit. A signal line monitoring device comprising an LED for displaying a detected error. A first selector for selecting a basic signal line from a plurality of signal lines; a second selector for selecting a comparison signal line from a plurality of signal lines;
2. The signal line monitoring device according to claim 1, further comprising a selector control unit for causing each of the first and second selectors to select the basic signal line and the comparison signal line. 3. A control to the selector control section for selecting a basic signal line and a comparison signal line from a plurality of signal lines and an initial set value of the maximum value and the minimum value to the maximum value register and the minimum value register. The setting value can be written by an external control order or by an externally connected RO.
3. The signal line monitoring device according to claim 2, wherein the writing is performed by reading from M or by writing.