JP2003077300A - Test circuit and semiconductor memory using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a test circuit which detects the number of clocks between signals of an operation instruction during measurement, can judge whether an operation specification is satisfied or not, and can detect easily contravention to the operation specification, and a semiconductor memory using the circuit. SOLUTION: In a semiconductor memory performing read/write of data conforming to an operation instruction successively inputted, when a first operation instruction is inputted, a reference clock is supplied to a counter, the reference clock is counted up by the counter, when a second operation instruction is inputted, a count value of the counter is compared with a number of a numerical value decided by an operation specification or less, as it is judged whether the count value reaches the numerical value decided by the operation specification or not in accordance with the compared result, when defective operation of the device is detected, it can be judged easily whether it is caused by trouble of the device or it is caused by contravention to the specification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention determines the number of clock signals between operation instructions sequentially input in a test circuit, for example, a functional circuit such as a DRAM which operates according to an operation instruction input in synchronization with a system clock signal. Detect and
The present invention relates to a test circuit for making a pass / fail judgment based on a result of comparison with a predetermined reference value, and a semiconductor memory device configured by using such a test circuit.

[0002]

2. Description of the Related Art A semiconductor memory device such as a synchronous DRA
In M (Synchronous DRAM), operations such as writing and reading are performed according to an operation command input from the outside. Normally, multiple operation commands are continuously input, and DRA
M sequentially performs designated processing according to these operation commands. Normally, in order to guarantee a normal operation in accordance with an input operation command, it is necessary to keep the time interval from one operation command to the input of the next operation command at a predetermined reference value or more.

A measurement pattern program (Pattern Program) designed to measure the operation of a semiconductor memory device.
In the above, the constraint of the minimum number of clocks for guaranteeing the operation is preset for each operation instruction between the time when one operation instruction is issued and the time when the next operation instruction is issued. This constraint is also referred to as (AC Spec), and is hereinafter referred to as operation spec. For example, in a synchronous DRAM, since there are a plurality of operation instructions set in synchronization with the system clock,
Operation specifications are also set according to each operation instruction. For example, there are an ACT command and an RD command as operation commands for controlling reading of data from a memory cell.

In the measurement pattern program, ACT
The command is used to activate the word line of the DRAM, and the RD command is used to start reading the information in the memory cell. Usually, in the measurement pattern program, as the operation specifications between the ACT command and the RD command, three cycles of the system clock are required. When this constraint is violated, a read error may occur. For example, if the RD command is output when the system clock signal has passed for two cycles after the ACT command is output, the data is read in the state where the bit line potential is not yet fully determined in the DRAM memory cell. There is a possibility that a read error may occur.

[0005]

Conventionally, when a DRAM operation test is performed according to a measurement pattern program, even if there is a violation of an operation specification, a desired operation instructed by an operation command is normally performed due to variation in process parameters. There are cases where it can be done, and cases where it cannot be done normally. Therefore, when a malfunction is found, it is difficult to determine whether this malfunction is due to a malfunction of the device itself or a violation of the operation specifications in the design of the measurement pattern program. In order to determine whether or not there is a violation of operation specifications, it is necessary to examine the measurement pattern program step by step, which is disadvantageous in that it takes time and effort.

The present invention has been made in view of the above circumstances, and an object thereof is to detect whether or not an operation specification is satisfied by detecting the number of clocks between signals of an operation command during operation of a measurement pattern program. It is an object of the present invention to provide a test circuit that can judge whether or not a device malfunctions or an operation specification violation during measurement and a semiconductor memory device using the test circuit.

[0007]

In order to achieve the above object, the test circuit of the present invention is a functional circuit which operates in accordance with operation commands that are sequentially input. In the functional circuit, the second operation is performed after the first operation command is input. A test circuit for determining whether or not a time interval until an instruction is input satisfies a predetermined number of reference clocks, and a counter for counting the reference clock according to the first operation instruction. And a judgment circuit for judging whether or not the count value of the counter has reached the predetermined number of clocks when the second operation command is input.

Further, the semiconductor memory device of the present invention reads / writes data according to the operation commands sequentially input, and the time from the input of the first operation command to the input of the second operation command. A semiconductor memory device comprising a test circuit for judging whether or not an interval satisfies a predetermined number of reference clocks and judging whether the interval is good or bad according to the judgment result, wherein the test circuit comprises: A counter that counts the reference clock in accordance with the operation command 1;
And a judgment circuit for judging whether or not the count value of the counter has reached the predetermined number of clocks when the second operation command is input, and judging whether the result is good or bad according to the judgment result.

Further, the present invention preferably has a counter start circuit for starting the counter in response to the first operation command.

In the present invention, it is preferable that the counter start circuit outputs a counter start signal in response to the first operation command, and the counter start signal in response to the counter start signal. A clock supply circuit for supplying a reference clock signal to the counter.

Further, in the present invention, preferably, when the count value of the counter reaches the predetermined number of clocks,
It has a counter reset circuit that outputs a reset signal.

Further, in the present invention, it is preferable that the counter reset the count value according to the reset signal.

Further, in the present invention, preferably, at least one comparison circuit for comparing the count value of the counter with a number smaller than the predetermined number of clocks and outputting a coincidence signal when they coincide, The determination circuit is the second
Is input, and when a matching comparison result is obtained from any of the comparison circuits, it is determined that the interval between the first and second operation instructions does not satisfy the predetermined number of clocks. .

[0014]

First Embodiment FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device using a test circuit according to the present invention. As shown in the figure, the semiconductor memory device includes a memory cell array 100, its peripheral circuits, a system clock generation circuit 110, and a test circuit 120. The peripheral circuits include, for example, a row address buffer 10, a row decoder (row decoder) 20,
Sense amplifier circuit 30, column decoder (column decoder)
40, a column address buffer 50, an input circuit 60, an output circuit 70, and a control circuit 80 are included. The memory cell array 100 is composed of, for example, DRAM memory cells.

Each component of the semiconductor memory device will be described below. The memory cell array 100 is composed of a plurality of memory cells arranged in a matrix.
The memory cells arranged in each row are connected to a common word line, and the memory cells arranged in each column are connected to a common bit line.

Row address buffer 10 holds an input address signal in accordance with a row address strobe signal / RAS and outputs the held address signal to row decoder 20 as a row address. Here, the symbol "/" attached to the signal name indicates an active state at a low level. The row decoder 20 selects a word line designated by a row address from a plurality of word lines according to an input row address, and a high level voltage, for example, to activate the selected word line,
The power supply voltage V _DD or a voltage slightly higher than the power supply voltage V _DD is applied. Therefore, one row of memory cells connected to the selected word line is held in the conductive state while the activation voltage is applied.

The column address buffer 50 holds an input address signal according to a column address strobe signal / CAS, and outputs the held address signal as a column address to the column decoder 40.
The column decoder 40 selects a bit line designated by the column address from the plurality of bit lines according to the input column address. The selection of the bit line is realized by controlling a bit line selection circuit (not shown) connected between the bit line and the sense amplifier. The bit line selection circuit
For example, it is constituted by a switching transistor provided between each bit line and a sense amplifier provided corresponding to each bit line. Column decoder 4
0 controls the transistor connected to the bit line selected according to the column address to the conductive state.

The sense amplifier circuit 30 detects the potential of the selected bit line to read the stored data of the selected memory cell connected to the selected bit line.

The input circuit 60 holds write data D _IN input from an external data bus at the time of writing, and the memory cell array 1 via the sense amplifier circuit 30.
Output to the 00 bit line. When reading, the output circuit 70 outputs the data read by the sense amplifier circuit 30 to an external data bus.

The control circuit 80 controls each part of the peripheral circuit such as the input circuit 60 and the output circuit 70 according to the write enable signal / WE and the chip enable signal / CS (or the column address strobe signal / CAS).

The system clock generation circuit 110 generates a system clock signal CLK having a stable frequency and supplies it to the test circuit 120 and each part of the peripheral circuit.
Although the system clock signal CLK is supplied only to the test circuit 120 in FIG. 1, it is actually supplied to the other components of the peripheral circuit.

When measuring the operation of the semiconductor memory device, the test circuit 120 detects the number of system clocks between the signals of the operation command during the operation of the measurement pattern program, and the operation specifications are maintained according to the detection result. It is determined whether or not it is present, and the spec NG signal SPNG indicating the determination result is output. For example, in the measurement parameter program, when the operation command interval satisfies an operation specification that meets a predetermined reference value, the specification NG signal SPNG is held at a low level, and conversely when the operation specification does not meet the predetermined reference value. , Spec NG signal SPNG is held at a high level. Therefore, the external circuit can determine whether or not the operation command set according to the measurement pattern program violates the operation specification by monitoring the specification NG signal SPNG output by the test circuit 120. The mistakes in the pattern program can be easily identified.

FIG. 2 shows the test circuit 12 in this embodiment.
2 is a circuit diagram showing a configuration example of 0. FIG. Hereinafter, the configuration and operation of the test circuit 120 will be described with reference to FIG. As illustrated, the test circuit 120 includes a counter start signal generation circuit 121, a counter circuit 122, a counter reset circuit 123, a decoder 124, and a register circuit 125.

The counter start signal generation circuit 121 includes
A counter start signal CNST is generated according to the ACT set signal and the reset signal RST. The counter circuit 122 is reset according to the output of the counter reset circuit 123, performs a counting operation according to the counter start signal CNST and the clock signal CLK, and outputs the count values Q2, Q1, Q0.

The counter reset circuit 123 receives the counter reset signal CR according to the count values Q2, Q1 and Q0.
Output ST. As shown in the figure, the counter reset circuit 123 outputs the counter reset signal CRST in accordance with the logically inverted value of the count value Q2 and the inverted logical product of the count values Q1 and Q0. That is, the counter circuit 1
22, the count values Q2, Q1, Q0 are "01".
1 ", that is, when the count value reaches 3, the counter reset signal CRST is held at the low level. At other times, the counter reset signal CRST is held at the high level.

The counter reset signal CRST and the power-on reset signal PON are input to the NAND gate 134. The power-on reset signal PON is a signal that is held at a low level after the power is turned on and is held at a high level after a lapse of a predetermined time. When the counter reset signal CRST is held at high level, N
The output signal of the AND gate 134 is held at low level. The output signal of the NAND gate 134 is the reset signal R
As ST, it is output to the counter start signal generation circuit 121 and the counter circuit 122. Counter circuit 122
Are reset by the reset signal RST, and the count values Q2, Q1, Q0 become zero.

The decoder 124 has count values Q2 and Q2.
1, Q0 is decoded, and when the count value reaches a predetermined value, the spec NG set signal SPST is output. Figure 2
In the configuration of the decoder 124 shown in FIG.
When 2, Q1 and Q0 are "001" and "010", that is, when the count value is equal to 1 or 2 and the read signal XRE is at low level, the output of the inverter 135 is held at high level. At this time, since the output signal of the NAND gate 136 or 137 is held at the low level, the output of the NAND gate 138 is held at the high level. That is, at this time, the high-level spec NG set signal SPST is output from the decoder 124.
At other times, the spec NG set signal SPST is held at the low level.

In the example shown in FIG. 2, the decoder 1
The number 24 is set to detect the count values "001" and "010", but the present invention is not limited to this configuration. The test circuit 120 of this embodiment is designed to detect the case where the operation specification is 3 or less. That is,
The counter circuit 1 counts the system clock to which the ACT command is input, and when the read command RD is input.
When the count value of 22 is 1 or 2, it is determined that the operation specification has not reached the predetermined reference value. Therefore, in the decoder 124, the count value of the counter circuit 122 is 1
Or it is designed to detect 2. In the measurement pattern program, a predetermined operation specification is set in advance for each operation instruction. Therefore, in order to inspect the operation specification of each operation instruction, the configuration of the decoder 124 has a predetermined operation of the operation instruction to be inspected. It is designed according to the specifications.

The register circuit 125 outputs the spec NG signal SPNG in response to the spec NG set signal SPST and the power-on reset signal PON. For example,
In the reset state, the spec NG signal SPN
When G is held at the low level and the high level spec NG set signal SPST is output from the decoder 124, the register 125 responds to the spec NG set signal SPST.
Set PNG to high level.

The configurations of the counter start signal generating circuit 121, the counter circuit 122, and the register circuit 125 which form the test circuit 120 of this embodiment will be described below with reference to FIGS.

Structure of the counter start signal generation circuit 121
Configuration and Operation FIG. 3 is a circuit diagram showing a configuration example of the counter start signal generation circuit 121. As shown, the counter start signal generation circuit 121 includes inverters 151, 155,
Transfer gates 152 and 153 and NOR gate 1
It is constituted by 54.

The counter start signal generating circuit 121
Counter start signal CNS according to ACT set signal
Output T. The ACT set signal is sent to the inverter 151.
Is input to the inverter 151 and the logically inverted signal thereof is output from the inverter 151. The transfer gates 152 and 153 are
Depending on the ACT set signal and its logic inversion signal, it is held in a conductive or cutoff state. For example, when the ACT set signal is held at the low level, the transfer gate 152 is held in the cutoff state and the transfer gate 153 is held in the conductive state. On the contrary, when the ACT set signal is held at the high level, the transfer gate 152 is held in the conductive state and the transfer gate 153 is held in the cutoff state.

The reset signal RST is the NOR gate 154.
Is input to one of the input terminals. The other input terminals of the NOR gate 154 have transfer gates 152 and 153.
Is connected to the output terminal of.

The output signal of the NOR gate 154 is output as the counter start signal CNST. The input terminal of the inverter 155 is connected to the output terminal of the NOR gate 154. The output signal of the inverter 155 is applied to the other input terminal of the NOR gate 154 via the transfer gate 153.

In the counter start signal generating circuit 121 having the above-mentioned structure, when the ACT set signal is at the low level, the transfer gate 153 is in the conductive state, so that the NOR gate 154 and the inverter 155 form a latch circuit. . The latch circuit holds the output signal of the NOR gate 154, that is, the counter set signal CNST.

As described above, when the count values Q2, Q1, Q0 of the counter circuit 122 are "011", the output signal of the counter reset circuit 123, that is, the counter reset signal CRST is held at the low level. In response to this, the reset signal RST output from the NAND gate 134 is held at the high level. Reset signal RS
When T is at high level, the output signal of NOR gate 154 is held at low level. At this time, if the transfer gate 153 is in a conducting state, the NOR gate 1
Since the output signal of 54 is latched, the reset signal RS
NOR gate 154 even after T returns to low level
Output signal, that is, the counter start signal CNST is held at the low level.

When the ACT set signal is set to the high level, the transfer gate 152 is turned on and the transfer gate 153 is turned off. Therefore, the output terminal of the transfer gate 152 is held at the low level. If the reset signal RST is also held at the low level at this time, the output of the NOR gate 154 is held at the high level. Then, after the ACT set signal returns to the low level, the output signal of the NOR gate 154 is held at the high level.

As described above, in the counter start signal generating circuit 121, in response to the reset signal RST,
The output signal of the NOR gate 154, that is, the counter start signal CNST is reset to the low level. ACT
When the set signal is low level, the output signal of the NOR gate 154 is held by the latch circuit. When the ACT set signal becomes high level, the output signal of the NOR gate 154 is held at high level, and after the ACT set signal returns to low level, the output signal of the NOR gate 154 is held at high level by the latch circuit. To be done.

Configuration and Operation of Counter Circuit 122 FIG. 4 is a circuit diagram showing a configuration example of the counter circuit 122. As shown in FIG. 4A, the counter circuit 122
Are D flip-flops 122-1, 122-2 and 1
22-3. FIG. 4B shows a D flip-flop 122- that constitutes the counter circuit 122.
2 is a circuit diagram showing the internal configuration of FIG. It should be noted that the D flip-flops 122-1 and 12-12 forming the counter circuit 122 are
Since 2-2 and 122-3 have the same configuration, FIG.
(B) shows only one of them.

As shown in FIG. 4A, D flip-flops 122-1, 122-2 and 122-3 are connected in series, and an inverting output terminal / Q is provided in each D flip-flop.
Are connected to respective data input terminals D. Further, the output signal Q0 of the D flip-flop 122-1 is D
It is input to the clock input terminal IN of the flip-flop 122-2, and the output signal Q of the D flip-flop 122-2.
1 is input to the clock input terminal IN of the D flip-flop 122-3.

The counter circuit 122 having the above configuration
In, the clock signal input to the clock input terminal IN of the first-stage D flip-flop 122-1 is counted. Further, the counter circuit 122 is reset according to the reset signal RST input to the reset terminal R of each D flip-flop.

As shown in FIG. 2, the clock input terminal in of the counter circuit 122 is connected to the output terminal of the inverter 133. Counter start signal generation circuit 12
High level counter start signal CNST by 1
Is output, the logical inversion signal of the clock signal CLK is output to the output terminal of the inverter 133 and supplied to the clock input terminal in of the counter circuit 122. In response to this, the counter circuit 122 counts, generates count values Q2, Q1, Q0, and outputs them to the counter reset circuit 123 and the decoder 124. When the count values Q2, Q1, Q0 become 011, the counter reset circuit 123 outputs the counter reset signal CRST, and the NAND gate 134 outputs the reset signal RST accordingly. Therefore, the counter circuit 122
Is reset.

Configuration and Operation of Register Circuit 125 FIG. 5 is a circuit diagram showing one configuration example of the register circuit 125. As shown, the register circuit 125 includes inverters 161, 165, 166, a transfer gate 16
2, 163 and NOR gate 164.

The register circuit 125 generates the spec NG signal SPNG in response to the spec NG set signal SPST output from the decoder 124. As shown in the figure, the spec NG set signal SPST is
61, and its logic inversion signal is input to the inverter 161.
Is output from. Transfer gates 162 and 163
Are held in a conductive or cutoff state in accordance with the spec NG set signal SPST and its logic inversion signal. For example, when the spec NG set signal SPST is held at the low level, the transfer gate 162 is held in the cutoff state and the transfer gate 163 is held in the conductive state. Conversely, when the spec NG set signal SPST is held at the high level, the transfer gate 162 is held in the conductive state and the transfer gate 16 is held.
3 is kept in the shut-off state.

The power-on reset signal PON is input to the inverter 166, and the output signal of the inverter 166, that is, the logic inversion signal of the power-on reset signal PON is N.
It is input to one input terminal of the OR gate 164. NO
The other input terminal of the R gate 164 is connected to the output terminals of the transfer gates 162 and 163.

The output signal of the NOR gate 164 is output as the spec NG signal SPNG. Inverter 16
The input terminal of 5 is connected to the output terminal of the NOR gate 164. The output signal of the inverter 165 is applied to the other input terminal of the NOR gate 164 via the transfer gate 163.

Register generating circuit 12 having the above-mentioned configuration
5, when the spec NG set signal SPST is at the low level, the transfer gate 163 is in the conductive state, so that the NOR gate 164 and the inverter 165 form a latch circuit. This latch circuit holds the output signal of the NOR gate 164, that is, the level of the spec NG signal SPNG.

As described above, the power-on reset signal PON is held at the low level for a predetermined time after the power supply voltage is turned on, and then switched to the high level. Therefore, while the power-on reset signal PON is at low level, the output signal of the inverter 166 is held at high level and the output signal of the NOR gate 164 is held at low level. After that, power-on reset signal PON
Is held at a high level, the output of the inverter 164 is held at a low level. At this time, for example, if the spec NG set signal SPST is held at the low level, the transfer gate 163 is in the conductive state and the output signal of the NOR gate 164 is latched. That is, even after the power-on reset signal PON is switched to the high level, the output signal of the NOR gate 164, that is, the spec NG signal SPNG is held at the low level.

When the spec NG set signal SPST is set to the high level, the transfer gate 162
Is turned on and the transfer gate 163 is turned off. Therefore, the output terminal of the transfer gate 162 is held at the low level. Further, since this and the output of the inverter 166 are held at the low level, the NOR gate 16
The output of 4 is set to high level. Then, after the spec NG set signal SPST returns to the low level, N
The output signal of the OR gate 164 is maintained at the high level.

As described above, in the register circuit 125, after the power is introduced, the output signal of the NOR gate 164, that is, the spec NG signal SPNG is reset to the low level in response to the power-on reset signal PON. When the spec NG set signal SPST is low level, NO
The output signal of the R gate 164 is held by the latch circuit. When the spec NG set signal SPST becomes high level, the output signal of the NOR gate 164 is set to high level, and the spec NG set signal SPST is set.
Is returned to the low level, the NOR circuit is activated by the latch circuit.
The output signal of the gate 164 is held at the high level.

Operation of Test Circuit 120 Next, the overall operation of the test circuit 120 of the present embodiment will be described based on the configuration and operation of each of the partial circuits described above. In the test circuit 120 of the present embodiment, according to the ACT operation command and the read command RD of the measurement pattern program, the operation specifications of these operation commands are predetermined reference values,
Here, for example, it is inspected whether or not three cycles of the system clock are satisfied, and the inspection result is represented by the spec NG signal. For example, when the operation specifications satisfy a predetermined reference value, that is, when the interval between the two operation commands is three or more cycles of the system clock, the specification NG signal SPNG is held at a low level, and conversely, the operation specifications are When the predetermined reference value is not satisfied, that is, when the interval between the two operation commands is less than 3 cycles of the system clock, the spec NG signal SPNG is held at the high level. Therefore, the external circuit monitors the level of the spec NG signal SPNG output from the test circuit 120,
It is possible to determine whether or not a predetermined operation command violates the operation specification, and it is possible to easily find an error in the measurement pattern program.

First, after the power supply voltage is turned on, the counter circuit 122 responds to the power-on reset signal PON.
And the register circuit 125 is reset. That is, the count values Q2, Q1, Q0 are held at 0, and the spec NG signal SPNG is held at low level.

When the measurement pattern program is executed,
Various operation commands incorporated in the program are sequentially executed. For example, when reading from the memory cell array, the ACT instruction and the read instruction RD are sequentially executed. When the ACT instruction is executed, the ACT set signal is first kept in the active state, that is, at the high level. In response to this, the counter start signal generation circuit 121 outputs a high level counter start signal CNST. Therefore, the system clock signal CLK is transmitted to the inverter 131, the NAND gate 132, and the inverter 133.
Is input to the clock input terminal IN of the counter circuit 122 via.

The counter circuit 122 is in a standby state when reset by the power-on reset signal PON, and performs a counter when a clock signal is input to the clock input terminal IN. The count values Q2, Q1, Q0 of the counter circuit 122 are output to the counter reset circuit 123 and the decoder 124. The count value is "011"
At this time, the counter reset circuit 123 outputs the counter reset signal CRST, and accordingly, the counter circuit 122 is reset.

When the read command RD is input, XRE
The signal is held at the low level in the active state, and the output signal of the inverter 135 is held at the high level. At this time, in the decoder 124, the count values Q2, Q1,
When Q0 is "001" or "010", the output signal of the NAND gate 136 or 137 is held at the low level, so that the output of the NAND gate 138 is held at the high level. That is, at this time, the high-level spec NG set signal SPST is output from the decoder 124. The register circuit 125 is reset by the power-on reset signal PON, and the output signal is held at the low level. When the high level spec NG set signal SPST is input from the decoder 124,
According to this, the spec NG signal SPNG which is an output signal
Is held high.

As described above, the test circuit 1 of this embodiment
20. The system clock is used for counting from the input of the ACT command by 20 to the input of the read command RD, and the ACT command and the RD are counted according to the count value.
It is possible to judge whether or not the operation specification between the command and the instruction satisfies a predetermined reference value, and the specification N is determined according to the judgment result.
Since the level of the G signal SPNG is set, the external circuit monitors the level of the spec NG signal SPNG,
You can see whether the operation specifications violate the standard value,
In the case of malfunction, it is possible to easily determine whether it is a problem of the device itself or a problem caused by the measurement pattern program.

6 and 7 show the test circuit 1 of this embodiment.
20 is a timing chart showing signal waveforms during operation of 20. Hereinafter, the operation of the test circuit 120 of this embodiment will be described in more detail with reference to these drawings.

FIG. 6 is a timing chart when there is no operation specification violation. As shown, the time interval tRCD between the input timings of the ACT command and the read command RD
However, in the case of three system clock cycles, there is no operation specification violation and the specification NG signal is held at a low level.

When the ACT instruction is not input, the counter circuit 122, the register circuit 125, etc. are in the reset state. Also, when the ACT command is not input,
The ACT set signal is at the low level, the counter start signal generation circuit 121 is reset according to the reset signal RST, and the counter start signal CNS of the output signal
T is held at low level. Therefore, the clock input terminal IN of the counter circuit 122 is always held at the low level, and the counter circuit 122 does not operate. The count values Q2, Q1, Q0 are the power-on reset signal P
It is reset to 0 by turning it on.

When the ACT command is input in this state, the ACT set signal is held at the high level in one cycle of the clock signal CLK at the rising edge of the system clock signal CLK. In response to this, in the counter start signal generation circuit 121, the counter start signal CNST of the output signal switches to the high level. Since the level of the counter start signal CNST is latched by the latch circuit inside the counter start signal generation circuit 121, the level is held until the reset signal RST is input.

Therefore, the system clock signal CLK
Signal is input to the clock input terminal IN of the counter circuit 122, and the counter circuit 122 starts to operate. When the count starts, the count values Q2, Q1, Q
0 is updated at each falling edge of the clock signal CLK and is incremented to binary numbers “001”, “010”, and “011”.

Here, since the operation specifications of the ACT command and the read command RD are 3 clock cycles, the reference value of this operation specification is satisfied in the timing chart shown in FIG. 6, so that the specification is not violated. When the count value of the counter circuit 122 becomes “011”, the counter reset signal CRST is output by the counter reset circuit 123, and accordingly, both the counter start signal generation circuit 121 and the counter circuit 122 are reset. , The clock signal is not supplied to the counter circuit 122, and the count value of the counter circuit 122 is reset to “000”. Therefore, ACT
Clock signal CLK 3 after the set signal rises
Even if the XRE signal becomes active after the first cycle,
Since the output signal of the decoder 124 is maintained at the low level, the register circuit 125 outputs the low-level spec NG signal SPNG.

Next, with reference to FIG. 7, the operation of the test circuit 120 when the operation specification does not satisfy the reference value, ie, three cycles of the system clock signal CLK, will be described. As shown in FIG. 7, here, for example, AC
System clock signal CLK after T command is input
The read command RD is input in the second cycle of.

Test circuit 12 when ACT command is input
The operation of 0 is almost the same as the timing chart of FIG. 6 described above. That is, the counter start signal CNST output from the counter start signal generation circuit 121 according to the ACT set signal is held at the high level. In response to this, an inverted signal of the system clock signal CLK is input to the clock input terminal IN of the counter circuit 122, and the counter circuit 122 counts up according to the input clock signal.

As shown in FIG. 7, the operation specification is not satisfied here, and the read command RD is input in the second cycle of the clock signal CLK after the ACT command is input. That is, the count values Q2, Q of the counter circuit 122
When 1 and Q0 are "010", the XRE signal is held at the active low level. Therefore, the output of the NAND gate 137 becomes low level, and the output signal of the NAND gate 138, that is, the spec NG set signal SP.
ST is held at high level.

The timing chart shown in FIG.
After inputting the ACT command, 2 of the clock signal CLK
Although the example in which the read command RD is input in the cycle is shown, when the read command RD is input in the first cycle of the clock signal CLK after the ACT command is input, the decoder 124 similarly sets the high level. Specifications N
The G set signal SPST is output, and in response to this, the register circuit 125 outputs the high-level spec NG signal SP.
NG is output.

As described above, in the test circuit of this embodiment, it is detected whether or not the time tRCD from the input of the ACT command to the input of the RD command satisfies a predetermined operation specification, When the predetermined operation specification is satisfied, the test circuit 120 outputs the low-level specification NG signal SPNG. Conversely, when the predetermined operation specification is not satisfied, the test circuit outputs the high-level specification NG signal SPNG. Is output. Therefore, it is possible to determine whether or not there is a violation of the operating specifications of the measurement pattern program according to the level of the output signal SPNG of the test circuit 120.

Second Embodiment FIG. 8 is a circuit diagram showing a second embodiment of the test circuit according to the present invention. As shown, the test circuit 12 of the present embodiment.
0a has substantially the same configuration as the test circuit 120 of the first embodiment of the present invention shown in FIG. However, in the present embodiment, the inverter 139 and the NAND gate 140 are newly provided on the output side of the register circuit 125.

The configuration and operation of the partial circuit connected to the output side of the register circuit 125 in the test circuit 120a of this embodiment will be described below. The other parts have the same configuration and function as the test circuit 120 of the first embodiment described above, and therefore the description thereof will be omitted.

As shown in FIG. 8, the input terminal of the inverter 139 is connected to the output terminal of the register 125.
One input terminal of the NAND gate 140 is the inverter 1
A selection signal, eg, a chip selection signal XC, which is connected to the output terminal of 39 and controls the operation of the chip at the other input terminal.
S is input. The output signal of the NAND gate 140 is
Supplied to the device. The operation of the device is controlled according to this output signal.

As described above, in the measurement pattern program, when the operation specifications satisfy the predetermined reference value, the register circuit 125 outputs the low-level specifications N.
The G signal SPNG is output. That is, there is no spec violation in the measurement pattern program, and the operation spec satisfies the predetermined reference value. At this time, since the output signal of the inverter 139 is held at the high level, the output of the NAND gate 140 is determined by the chip selection signal XCS. For example, when the chip selection signal XCS is high level, the output signal of the NAND gate 140 becomes low level. On the contrary, when the chip selection signal XCS is low level,
The output signal of the NAND gate 140 becomes high level.
Predetermined processing is performed inside the device according to the output signal of the NAND gate 140. For example, NAND
When the output of the gate 140 is low level, a chip is selected inside the device, and a predetermined process is performed on the selected chip.

On the other hand, when the measurement pattern program has a spec violation, that is, when the operation spec does not satisfy a predetermined reference value, the register circuit 125 outputs a high-level spec NG signal SPNG. At this time, the output signal of the inverter 139 becomes low level,
The output of the NAND gate 140 is held at high level. At this time, the device can be set to the non-operating state without executing the chip selection inside the device.

As described above, according to this embodiment, the operation of the internal circuit of the device can be controlled according to the spec NG signal SPNG output from the register circuit 125, and the measurement pattern program can be stored in the measurement pattern program at the time of measurement. When there is no spec violation, the internal circuit of the device can be controlled to the operating state, and conversely, when there is a spec violation, the operation of the internal circuit of the device can be stopped.

The above-described test circuit of the present invention is shown in FIG.
Although the present invention can be applied to a semiconductor memory device, for example, a DRAM as shown in, the present invention is not limited to this, and it goes without saying that it can be applied to other functional circuits. That is, the test circuit of the present invention can be applied to other uses for detecting the number of clocks of a predetermined reference clock between two input signals.

[0075]

As described above, according to the test circuit of the present invention and the semiconductor memory device using the test circuit, it is possible to easily determine whether or not the measurement pattern program has a spec violation, and It is possible to detect spec violations without considering process variations.
Therefore, if there is a problem in the operation of the device as a result of the measurement, it is possible to easily determine whether it is a problem of the device itself or a problem caused by a violation of the specifications of the measurement pattern program, and correct the problem of the device. There is an advantage that can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor memory device using a test circuit according to the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of a test circuit according to the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a counter start signal generation circuit.

FIG. 4 is a circuit diagram showing a configuration example of a counter circuit.

FIG. 5 is a circuit diagram showing a configuration example of a register circuit.

FIG. 6 is a timing chart showing the operation of the test circuit when there is no spec violation.

FIG. 7 is a timing chart showing the operation of the test circuit when there is a spec violation.

FIG. 8 is a circuit diagram showing a second embodiment of the test circuit according to the present invention.

[Explanation of symbols]

120 ... Test circuit, 121 ... Counter start signal generation circuit, 122 ... Counter circuit, 123 ... Counter reset circuit, 124 ... Decoder, 125 ... Register circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2G132 AA08 AC03 AG08 AK09 AK18                       AL09                 5L106 AA01 DD00 GG03                 5M024 AA91 BB30 BB40 DD83 DD90                       GG06 GG20 JJ02 JJ32 JJ40                       MM10 PP01 PP02 PP03 PP07

Claims (12)

[Claims] 1. A functional circuit that operates according to sequentially input operation instructions, wherein the time interval from the input of the first operation instruction to the input of the second operation instruction is a predetermined number of reference clocks. A test circuit for determining whether or not the condition is satisfied, wherein a counter that counts the reference clock in response to the first operation command, and a count value of the counter when the second operation command is input. A test circuit having a judgment circuit for judging whether or not the predetermined number of clocks has been reached. 2. The test circuit according to claim 1, further comprising a counter start circuit for starting the counter in response to the first operation command. 3. The counter start circuit supplies a counter start signal generating circuit which outputs a counter start signal in response to the first operation command, and the reference clock signal to the counter in response to the counter start signal. 3. The test circuit according to claim 2, further comprising a clock supply circuit that operates. 4. The test circuit according to claim 1, further comprising a counter reset circuit that outputs a reset signal when the count value of the counter reaches the predetermined number of clocks. 5. The test circuit according to claim 4, wherein the counter resets the count value in response to the reset signal. 6. A counter circuit for comparing the count value of the counter with a number smaller than the predetermined number of clocks, and outputting a coincidence signal when they coincide with each other, wherein the judgment circuit comprises the second circuit. It is determined that the interval between the first and second operation instructions does not satisfy the predetermined number of clocks when an operation instruction is input and a matching comparison result is obtained from any of the comparison circuits. The test circuit according to item 1. 7. A time interval from the input of the first operation instruction to the input of the second operation instruction, in which data is read / written in accordance with the operation instructions sequentially input.
What is claimed is: 1. A semiconductor memory device comprising: a test circuit that determines whether a predetermined number of reference clocks is satisfied, and determines whether the result is good or bad according to the result of the determination. A counter that counts the reference clock according to an instruction, and determines whether the count value of the counter has reached the predetermined number of clocks when the second operation instruction is input. A semiconductor memory device having a judgment circuit for judging acceptability according to the judgment. 8. The semiconductor memory device according to claim 7, further comprising a counter start circuit for starting said counter in response to said first operation command. 9. The counter start circuit supplies a counter start signal generating circuit for outputting a counter start signal in response to the first operation command, and the reference clock signal to the counter in response to the counter start signal. 9. The semiconductor memory device according to claim 8, further comprising: 10. The semiconductor memory device according to claim 7, further comprising a counter reset circuit which outputs a reset signal when the count value of said counter reaches said predetermined number of clocks. 11. The semiconductor memory device according to claim 10, wherein the counter resets the count value in response to the reset signal. 12. A counter circuit comprising at least one comparison circuit for comparing a count value of the counter with a number smaller than the predetermined number of clocks and outputting a coincidence signal when they coincide with each other. It is determined that the interval between the first and second operation instructions does not satisfy the predetermined number of clocks when an operation instruction is input and a matching comparison result is obtained from any of the comparison circuits. Item 7. The semiconductor memory device according to item 7.