JPH1186598A - Method and device for verifying and moreover characterizing data holding time in dram using build-up test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ease dependency on a clock frequency of a build-up self test by selectively changing a rate with which a refresh operation of respective rows of a DRAM is executed by a refresh control circuit in order to verify a better operational margin than a specification on a data holding time in the DRAM by a build-up test circuit. SOLUTION: In a build-up self test (BIST) controller 112, refreshing is executed after storing an already known value into an array 132. An ordinary or normal refresh operation is made to execute by the affirmation cancel or denying of a MUX control signal with the BIST controller 112, and whereby normal RAS and normal CAS signals are made to reach the DRAM 106. In the BIST controller 112, N times of normal refresh operation are suspended in respective refreshing of (M+N) and whereby an effective refresh rate is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to integrated electronic circuits and, more particularly, to a method and apparatus for testing such circuits.

[0002]

BACKGROUND OF THE INVENTION A common and well-known test method for integrated circuits is a built-in test (Build-Test) that uses dedicated portions of the integrated circuit to determine whether the integrated circuit is free of manufacturing defects. In Test: BIT or built-in self-test (Built-In-Self Te)
st: BIST). BIST circuits are often stimuli or stimuli for the circuit under test.
Occurs. The circuit under test is expected response and BIS
Generate a response to be compared by the T-circuit. The result of this comparison is provided by the BIST circuit for use by the manufacturer or user of the integrated circuit.

One particularly well-suited application of BIST is memory, because of the repetitive structure often found in memories. A dynamic random access memory (DRAM) has almost the same test requirements as a static random access memory (SRAM), but has a data retention time (data retention).
im) has the additional requirement of testing the specifications.
DRAMs are specified to have a maximum interval or interval at which all rows or rows must be refreshed. In particular, DRAMs have the property that all read operations and all write operations have the effect of refreshing the accessed row. For normal system operation, this property ensures that data is not corrupted by these accesses, but it is necessary to maintain a regular refresh schedule due to the random nature of the access in normal system operation. It does not reduce. D
A RAM product or production test is performed at a minimum defined rate or rate.
Must be sufficient to ensure that all data stored reliably is retained.

[0004] Earlier BIST architectures generated test sequences to test memory. As an example, the test sequence is stored in ROM and is therefore programmable. One example of such a test architecture is "Built-in Self Test for Integrated Circuits (Bu
ilt-In Self Test for Inte
graded Circuits) in U.S. Patent No. 5,173,906. Another programmable test architecture is the "Microcoded Embedded Self-Test Device for Memory Arrays (Micr
o-CodedBuilt-In Self Test
Apparatus for a Memory Ar
ray) is taught in U.S. Pat. No. 5,224,101. Microcode is microcode RO
M is used to provide a delay period for data retention determined by a program stored in M. However, this delay interval depends on the clock frequency of the built-in test circuit and is implemented as a counter clocked at the clock rate of the sequencer.

[0005]

SUMMARY OF THE INVENTION If a DRA is incorporated
If the test method provided for M is a built-in self-test (BIST), the BIST circuit will generally execute a predetermined sequence of states to stimulate or excite the memory and evaluate the response of the memory. Finite state machine (finite stat) designed to
e machine (FSM). State transitions in a given BIST sequence are generally synchronized with one or more clock inputs. This clocking source is generally the same as that used for other circuits with which the embedded DRAM is integrated. Thus, if a given BIST sequence includes a test for a refresh interval, B
The duration of the refresh interval generated by the IST FSM is directly related to the frequency of the BIST clocking source, while the function that must be guaranteed by testing is a defined data retention interval that is independent of the BIST clocking frequency.

[0006] Other circuits with which the embedded DRAM is integrated (eg, data processor circuits) are typically designed and used to operate reliably over a range of clock frequencies. If BIST
Should operate over the same range of frequencies as other circuits with which the embedded DRAM is integrated,
Especially when the maximum data retention interval is tested,
There is a problem that the BIST data holding interval depends on the clock frequency. Frequency dependence results in difficulties in applying the data retention interval test for a particular time period.

[0007]

According to one aspect of the present invention, there is provided a method for verifying data retention time in a dynamic random access memory (DRAM) using a built-in test circuit, the method comprising a plurality of rows of memory cells. Providing a DRAM having a refresh control circuit coupled to the DRAM, wherein each row periodically requires a refresh operation to hold valid data, and providing a refresh control circuit coupled to the DRAM. , The refresh control circuit provides at least one signal to start the refresh operation of the DRAM to the DRAM,
M requires that each row undergo a periodic refresh operation to meet the data retention time specification for the DRAM, and provides the refresh control circuit and a built-in test circuit coupled to the DRAM. Step, wherein the built-in test circuit includes the DR
A refresh control circuit for selectively changing a rate at which a refresh operation of each row of the DRAM is performed in order to verify an operation margin above an AM data retention time specification.

[0008] The step of providing the built-in test circuit for selectively changing the rate at which the refresh control circuit performs the refresh operation may further comprise refreshing the DRAM row refresh every N out of (M + N) refresh operations. Is advantageously provided.

[0009] The step of selectively inhibiting the refresh operation of the DRAM row refresh for every N out of the (M + N) refresh operations includes the step of using a programmable counter in which N and M are programmable by a user. And the programmable counter can be configured to at least partially perform the prohibition.

The step of providing a built-in test circuit for selectively changing the rate at which the refresh control circuit performs refresh operations further comprises the step of using a counter to count the number of refresh operations and The DRAM inhibits every N out of (M + N) refresh operations, where N and M are integers and N can be less than or equal to M.

The step of providing the built-in test circuit further comprises testing the DRAM by applying a variable refresh rate until the built-in test circuit encounters at least a first fail of data retention. Advantageously, the step of dynamically determining a limit for reliable data retention can be provided.

Further, the DRA is added to the built-in test circuit.
The step of dynamically determining a limit for reliable data retention of M further reports the limit to a controller of the refresh control circuit to change a refresh interval to optimize performance of the DRAM. And providing a circuit for the purpose.

The step of allowing the built-in test circuit to dynamically determine a limit for reliable data retention further comprises the step of scaling the rate of memory refresh at which the DRAM is refreshed. The scale change is the normal rate at which the refresh control circuit starts the refresh operation.

## EQU00003 ## where [1 / (1 + N / M)] * the normal refresh rate is between and equal to the product of N, where N is less than M and N and M are integers. Is also good.

According to another aspect of the present invention, there is provided a memory test circuit for testing data retention of a DRAM, the circuit being a test circuit for electrically monitoring a data refresh signal provided to the DRAM. , The test circuit selectively disables each of the (M + N) data refresh signals for every N, N is smaller than M, and N and M are integers, and the test circuit is a data holding time specification of the DRAM. Verifying a higher operating margin, the test circuit being clocked by a clock signal having a frequency that does not affect or change a test interval period for testing data retention of the DRAM. It is characterized by the following.

[0015] Conveniently, the test circuit further comprises a programmable circuit for allowing a user to program the value of N.

The test circuit may further comprise a signal from zero (M−
The memory test circuit may be configured to include a characterization circuit that provides a plurality of values of N up to 1) so that the memory test circuit can characterize the limits of reliable data retention of the DRAM. it can.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. In the drawings, the same reference numerals indicate the same or corresponding parts throughout the drawings.

FIG. 1 shows a block diagram of a memory system 100 constructed in accordance with the present invention. Memory system 1
00 is a dynamic random access memory (DRA)
M) Control unit 102, built-in self test (BIS
T) Unit 104 and DRAM 106 are included. BI
The ST unit 104 automatically tests the data readability, data writeability, and data retention characteristics of the DRAM 106. Such a test ensures that DRAM 106 and memory system 100 operate properly. BIST unit 104
Can verify that the data retention characteristics of the DRAM 106 conform to a specified or specified minimum time. Further, BIST unit 104 introduces a second mode of operation in which it can determine the actual data retention characteristics of a particular memory system. The BIST unit 104 or associated data processor can then increase the DRAM refresh time to minimize power consumption and maximize bandwidth given a particular DRAM characteristic. B
The IST unit 104 can test the data retention time of the associated DRAM array independently of the frequency of the clock that controls the BIST unit 104. BIS
The T unit 104 depends on the normal refresh function of the DRAM control unit 102. BIST unit 10
4 is powerful, but it does not change the interface between traditional DRAM controllers and traditional DRAM. As a result, the BIST unit 104 can be easily introduced into existing architectures and into modular design methods. BIST unit 104 is well suited for embedded applications where the memory is not directly accessible to the user.

<Connection of Memory System> Continuing the description with reference to FIG.
A controller 108 and a DRAM parameter register 110 are provided. The DRAM controller 108 receives an input “access decode (ACCESS DECS)” from an external device.
CODE) "and the DRAM parameter register 1
Receive 10 contents. The DRAM controller 108 outputs the row address strobe (RAS), the column address strobe (CAS), and the "DRAM REGISTER READ /
WRITE: R / W). The DRAM parameter register 110 receives the data input “Normal data input (N
ORMALDATA IN) "and the control signal" DRA
M register R / W ". DRAM parameter register 110 is described below with respect to FIG.

The BIST unit 104 includes a BIST controller 112, a refresh control register (RCR) 1
14, a comparator 116, and seven 2: 1 multiplexers (MUX) 118, 120, 122, 124, 12
6, 128 and 130. The BIST controller 112 is generally a finite state machine (FSM) designed to stimulate or stimulate the DRAM 106 and execute a predetermined sequence of states to evaluate the response of the DRAM 106. BIST
The controller 112 itself has two counters, an N: M counter and a ROW counter. The N: M counter indicates “normal RAS (NORMA
L RAS) "control signal.
The row counter is clocked by the output of the DRAM 106, the MSB. The BIST unit 104 receives various "BIST CONTROL" signals as inputs from the data processor, microphone controller, digital signal processor, etc.
ST enable (BIST ENABLE) ”and“ BIST register selection (BIST REGISTER)
SELECT) ”. BIST unit 10
4 is a data processor, a microcontroller, a digital signal processor, and various other “BIS
T status (BIST STATUS) signal, i.e., "BIST COMPLETE (BIST COMPLET)
E) and BIST path (BIST PAS
S) "is generated. In the BIST unit 104, B
The IST controller 112 generates control and data signals, i.e., "BIST R / W", "BIST R".
AS ”,“ BIST CAS ”,“ BIST low (BI
ST ROW) "," BIST column (BIST CO
LUMN) "," BIST data input (BIST DA)
TA IN) "," MUX control (MUX CONTROL)
L) ”,“ EXPECTED DAT ”
A) "and some" Refresh Control Register (RCR) Control (RCR) CONTROL R
EGISTER (RCR) CONTROL) signal. In addition, the BIST controller 112
16 receives an internal control signal "Equal" and is bidirectionally coupled to the refresh control register 114 via "VALUE". The refresh control register 114 will be described later with reference to FIG.

MUXs 118, 120, 122, 124,
The first inputs of 126, 128 and 130 are BIST R / W, BIST RAS, BIST
CAS, BIST low, BIST column, BIST data input, and a power supply voltage corresponding to a predetermined logic level, V _DD . MUX 118, 120, 122, 1
The second inputs of 24, 126, 128 and 130 are normal R / W, normal RAS, and normal C, respectively.
AS, normal row, normal column, normal data input, and data output are received. MUX 118, 12
0, 122, 124, 126, 128 and 130 are
Generate signals R / W, RAS, CAS, row, column, data input, and normal data output, respectively.
MUX 118,120,122,124,126,12
The output of each of 8 and 130 is a control signal "MUX control".
Is controlled by

Comparator 116 receives "expected data" and "data out" for comparison and generates a control signal "equal" in response to the comparison being equal or unequal. The data input and the data output of the refresh control register 114 are "normal data input" respectively.
And "Normal data output".

The DRAM 106 has an array 132, MUX1
34, a row decoder 136, a sense amplifier 138, a column selector 140, a control unit 142, and a refresh counter 144. In the embodiment shown, array 132 comprises 128 rows or rows selected by the output of row decoder 136. Row decoder 136 receives the output of MUX 134. MUX13
4 receives the output of the refresh counter 144, a "REFRESH ROW", and an input "LOW". The output of the MUX 134 is selected by a control signal output by the control unit 142. The control unit 142 receives the outputs of the MUXs 118, 120 and 122 and outputs a control signal "clock (CL
OCK) "and the sense enable SE. Refresh counter 144 receives a control signal “clock”. The most significant bit of the refresh counter 144 is M
Output as SB. The output of array 132 is coupled to sense amplifier 138. The output of sense amplifier 138 is coupled to column selector 140. Column selector 1
40 also receives the output of MUX 128 and control signal SE. Column selector 140 outputs the data to an external device via “data output” and MUX 130.

<Outline of Memory System Operation> In operation, memory system 100 has a normal or normal mode operation and a test or test mode operation. In normal mode operation, the data processor, microcontroller, digital signal processor,
Others store data in DRAM 10 according to program instructions.
6 and read from the DRAM 106. In the test mode of operation, the BIST unit 104 performs two overall classes of tests on the DRAM 106: a pattern test and a refresh test. Further, the refresh test itself has a first and a second mode of operation.

<Normal Mode Operation> Continuing the description of the normal mode operation, the MUXs 118, 120 and 12 will be described.
2, 124, 126, 128 and 130 are configured to pass normal R / W, normal RAS, normal CAS, normal row, normal column, normal data input, and data output, respectively. The memory system 100 is initially configured with various parameters that define its operating characteristics. Intelligent actor
(tor) stores these parameters in the DRAM parameter register 110 when the data processing system incorporating the memory system 100 is powered up. These parameters are written to a particular one of the DRAM parameter registers 110 by asserting a particular combination of the access code signals and by providing the desired parameter value to the input "Normal Data Input".
Thereafter, memory system 100 stores the provided data in array 132 or outputs previously stored data from array 132. Scattered with them, D
RAM controller 108 periodically issues refresh signals to DRAM 106 to ensure that stored data is not lost over time due to normal current leakage.

In a read operation, the intelligent actor applies the desired data address to the normal row and normal column signals, asserts the normal R / W signal, and asserts a valid access code signal. The control unit 142 controls the row decoder 13 via the MUX 134
Select the "row" to be coupled to 6. The access decode signal indicates that the address in the normal row and normal column signals is actually directed to the memory system 100. Typically, the memory system 1
00 is not connected to all of the address signals in the data processing system. DRAM controller 108 then generates a first pattern of values for normal RAS and normal CAS, causing array 132 to output the desired data in the appropriate superset. Control unit 142 enables sense amplifier 138 by asserting control signal SE. Sense amplifier 138 detects and amplifies the superset of the data and outputs it to column selector 140.
The column selector 140 parses the superset of data into specified portions and outputs it to the intelligent actor via the data output.

In a write operation, the intelligent actor applies desired data and destination data addresses to the normal data input, normal row and normal column signals, and negates or de-asserts the normal R / W signal (de-asserts). ), And asserts a valid access decode signal. The control unit 142 selects a "low" to be coupled to the row decoder 136 via the MUX 134. Column selector 14
A 0 directs the input data to the correct column in array 132. The DRAM controller 108 then switches to the normal R
Generating a first pattern of values on AS and normal CAS causes array 132 to store the input data in array 132. Control unit 142 enables or activates sense amplifier 138 by asserting control signal SE. Sense amplifier 138 drives the input data into the memory cell identified by the intersection of the normal row and normal column values and restores or recovers the existing data in the same row or unaccessed column of the row.

In the refresh operation, the DRAM controller 108 controls the normal RAS and the normal CA.
Affirming the value of the second pattern on S notifies the DRAM 106 that it should start a refresh operation.
The DRAM controller 108 notifies such operations or actions according to the contents of the DRAM parameter register 110. BIST controller 1
12 are RAs via MUXs 120 and 122, respectively.
Select normal RAS and normal CAS to be coupled to S and CAS. The control unit 142 is an MU
Select the output of refresh counter 144, "Refresh Low", to be coupled to row decoder 136 via X134, and assert control signal SE. Array 13
2 then couples the row indexed by refresh counter 144 to sense amplifier 138. Sense amplifier 138 senses the value stored in the indexed row, amplifies the value, and drives the amplified value back to the indexed row. The control unit 142 increments the refresh counter 144 by pulsing or pulsing the "clock" in preparation for the next refresh cycle. In the embodiment shown, array 132 comprises 128 rows of memory bit cells. As a result, the DRAM controller 108 causes normal RAS and normal CA within a certain time interval to refresh the array 132.
The second pattern on S must be asserted 128 times.

<Operation in Test Mode, Pattern Test>
Continuing with the description of the test mode of operation, BIST unit 104 typically tests each memory bit cell in array 132 when it is first powered up. Generally, logic (not shown) associated with memory system 100 asserts control signal BIST enable to initiate testing after a power-on reset (POR). However, the BIST test can be performed at other time (s), if appropriate. The BIST controller 112 has MUXs 118 and 12
0, 122, 124, 126, 128 and 130
BIST R / W, BIST RAS, BI
ST CAS, BIST row, BIST column, BIS
Allow T data input and _VDD to pass. BIS
The T controller 112 performs a series of test reading and writing with test data to confirm the function of each memory bit cell.

The BIST controller 112 controls the test data pattern, the operation order (read / write or write / write).
Read) and address sequence (ascending direction (as
sending or descending direction (descendin)
g)) to detect as many faults as possible.
In one embodiment of the present invention, the BIST controller 112
Tests each memory entry with an all "1", all "0", and alternating "1" and "0" pattern. Other patterns are known in the art.

The BIST controller 112 generates test read and test write in a manner similar to the normal or normal read and normal or normal write described above. However, in this case, the BIST controller 112 writes the values of the R / W, RAS, CAS, row, column, and data inputs to its output BIST R /
W, BIST RAS, BIST CAS, BIST Row, BIST Column, and BIST Data Input. In one embodiment of the present invention, BIST controller 112 includes a counter (not shown) to sequence various operations of the BIST test. In particular, certain bits of the counter indicate which pattern is in array 1
Controls which values are supplied to the BIST row, certain bits of the counter control which values are supplied to the BIST column, etc. Is performed. In this way, addresses, patterns, and all other necessary combinations can be easily generated.

The BIST controller 112 controls the comparator 11
6, the "data output" value is changed to "expected data (EX
(PECTED DATA) "to confirm the function of each memory bit cell. If these two values are equal, comparator 116 asserts control signal "equal", indicating a successful test. If the two values are not equal, comparator 116 provides control signal "equal".
Affirmative or negative to indicate test failure.

<Operation in Test Mode, Refresh Test, Holding Confirmation> The BIST unit 104
Test the data retention or retention characteristics of each memory bit cell. In the first data retention test mode, the BIST unit 104 performs a DRA by performing a single pass / fail test.
It is determined whether M106 meets or exceeds the specification. In one embodiment, this data retention test is performed after the BIST pattern test described above.
In other embodiments, it can be started separately by its own control signal. In a DRAM, the charge stored in each memory bit cell tends to dissipate or "leak" over time, contaminating the value of the data. In the data retention test, the data stored in the memory has a “retention time (retention time)” defined by the specification.
me) "to determine whether to sustain for a minimum time greater than or equal to the period. As a result, the stored values are reliable if each memory bit cell is refreshed at least once during each retention period.

Initially, the BIST controller 112 stores at least one known value in the array 132 so that at least one refresh can be performed. In one embodiment of the present invention, BIST controller 112 initiates a retention test with the last pattern generated in the BIST pattern test described above. BIS
The T controller 112 enables a normal or normal refresh operation by canceling or negating the MUX control signal so that the normal RAS and normal CAS signals can reach the DRAM 106.

Next, the BIST controller 112 suspends the normal refresh operation of the DRAM controller 108 to effectively reduce the refresh rate.
The BIST controller 112 interrupts the normal refresh operation of the DRAM controller 108 by re-asserting the MUX control signal, and prevents the normal RAS and normal CAS signals from reaching the DRAM 106. BIST controller 112 is (M + N)
, The effective or effective refresh rate is reduced by interrupting the normal refresh operation N times, where N and M are integers. This strategy reduces the effective refresh rate corresponding to the tested hold time of (1 + N / M) * Normal hold time as expressed by the following equation:

## EQU1 ## [1 / (1 + N / M)] * Normal refresh rate

One embodiment of the N: M counter is described in "Counter with Programmable Period and Method Therefor" (A Counter Having Program).
map Periods and Method
No. 08 / 674,381, entitled "Therfor)", which is incorporated herein by reference. This particular N: M counter regularly places N interrupts or interrupts over the (M + N) refresh operations generated by DRAM controller 108.

After some number of refreshes of each row or row of array 132, BIST controller 112 accesses MUX to access array 132.
The control signal is asserted again. BIST controller 112
Determines that DRAM controller 108 has completed the refresh operation for each row in array 132 by monitoring the most significant bit (MSB) output by refresh counter 144. As mentioned above, the refresh counter 144 is incremented by one by the control unit 142 each time a refresh operation is performed. Accordingly, the row counter in BIST controller 112 is incremented each time DRAM 106 cycles through each row. In another embodiment, the row counter is a BIST controller 1
12, each refresh operation that is not masked can be counted. This count is the array 13
When equal to the number of rows of two, the refresh of each row will be completed. The BIST controller 112 compares the "data out" value with the "expected data" value as described above. If "data out" and "expected data" are the same, then the effective or effective refresh rate has not exceeded the hold time.
If the two values are different, the effective refresh rate has exceeded the hold time.

<Test Mode Operation, Refresh Test, and Retention Characterization> In the second data retention test mode, the BIST unit 104 determines the actual retention time of the DRAM 106 by performing a series of pass / fail tests. . In one embodiment, this second mode is selected by setting a particular bit in refresh control register 114 to a logical "1" value.
In the second mode, the BIST controller 1
12 performs a first data retention test using the first values N and M. Next, the BIST controller 112 changes the value of N and / or M depending on whether the previous test passed or failed and the search algorithm used.

In one embodiment, the BIST controller 1
12 is a linear search algorithm (linear search algorithm)
arch algorithm). In the linear search algorithm, the BIST controller 1
12 sets N equal to 1 and M equals the number of rows or rows in array 132. BIST controller 1
12 then tests with these values of N and M. If array 132 passes, then BIST controller 112 increments N and performs the test again. This process continues until N equals M or the array 13
Continue until 2 fails. At the end of this test, BI
The ST controller 112 writes the last value of N into the refresh control register 114.

In another embodiment, BIST controller 112 uses a binary search algorithm in the second data retention test mode. This algorithm is shown in FIG.
This will be described in more detail later with reference to FIG. BIS
The T controller 112 also writes the last value of N into the refresh control register 114.

The user of the system that has implemented the memory system 100 can use the final value of N to adjust the refresh rate programmed into the DRAM parameter register 110. Such adjustments allow the user to minimize the bandwidth allocated to the refresh operation and minimize the power consumed by the refresh operation.

The operation in the test mode will be further described with reference to FIGS.

FIG. 2 shows the memory system 1 shown in FIG.
4 shows a conceptual representation of a 00 programmable register. Refresh timer register, RAS timer register, C
An AS timer register, a precharge timer register, and a page timer register are introduced into the parameter register 110 of the DRAM. The BIST refresh control register is implemented in the refresh control register 114. These registers are visible and programmable to the user of the memory system 100. In other embodiments, these registers can be hardwired to permanent values by the manufacturer of the memory system 100.

The refresh timer register, RAS
Timer registers, CAS timer registers, precharge timer registers, and page timer registers are generally known in the art. The value stored in the refresh timer register is stored in the DRAM controller 108 by the DRAM.
Control the rate at which the refresh operation is started for 106. The value stored in the RAS timer register is the minimum positive width of the normal RAS signal.
Width). The value stored in the CAS timer register controls the minimum positive width of the normal CAS signal. The value stored in the precharge timer register is the minimum de-assertion width or minimum de-assertion width of the normal RAS signal.
th). The value stored in the page timer register controls the maximum positive width of the normal RAS signal. The user selects each of these values according to the design specification of the selected DRAM.

The BIST refresh control register 1
Reference numeral 14 denotes a 16-bit register having 4 fields, 1-bit valid field (V), 1-bit sweep field (S), 7-bit N field, and 7-bit M field. If V is equal to zero, BIST controller 112 does not perform any retention tests. When V is equal to “1”, the BIST controller 112 performs a retention test according to the value of the S field. If the S field equals zero, BI
The ST controller 112 performs a single data retention verification test with the values of N and M loaded into the N and M fields. If the S field is equal to "1", the BIST controller 112 performs a series of data retention tests to characterize the DRAM 106. The values stored in the N and M fields have been described previously.

FIG. 3 shows a flowchart 300 of the operation of the BIST controller 112 shown in FIG. Here, V
Is equal to "1" and S is equal to zero. As a result, B
The IST controller 112 performs a single data retention test after performing all pattern tests.
If V is equal to zero, the BIST controller 11
2 does not perform the step generically named "refresh test". If S is equal to "1", BI
The ST controller 112 will perform the steps shown in FIG. 6 instead of the instruction generically named "refresh test".

The flowchart 300 shows the BIST controller 11.
2 begins when step 302 asserts the MUX control signal. The assertion of the MUX control signal couples the BIST controller 112 to the DRAM 106. BIS
In step 304, the T controller 112 selects the first pattern. Such a pattern may be all 0's, all 1's, or alternatively 0's and 1's. BAST controller 112 then provides this pattern to array 132, reads array 132 and determines if the stored value is equal to the expected value, step 306. BIST controller 112
Next, at step 308, determine if there are any more patterns to add to the array 132. If there are more patterns to add to array 132, BIST controller 112 selects a new pattern at step 310 and returns to step 306.

If there are no more patterns to test, the BIST controller 112 performs a data retention test using the last pattern stored in step 306, step 312. Step 312 corresponds to FIG.
This will be described later with reference to FIG. BIST controller 112
Next, at step 314, it is determined whether there are more patterns to be provided to the array 132. If there are more patterns to add to array 132, BI
The ST controller 112 determines in step 316
Set a new pattern and return to step 312.
If there are no more patterns to test, BIST
The controller 112 determines in step 318 that the MUX
Cancel or negate the control signal. Canceling or negating the MUX control signal causes the DRAM controller 108 to
Reconnect to RAM 106.

The BIST controller 112 reports an error and completes the flowchart 300 at step 320. The BIST controller 112 selectively
By asserting the ST path (BIST PASS), the output BIST is completed (BIST COMPLET).
Report an error by affirming E). BIST
Controller 112 affirms the BIST pass if there was no error in the previous series of tests.

FIG. 4 shows a flowchart 400 of step 310 shown in FIG. In flowchart 400, the BIS
The T controller 112 performs a single data retention test. First, at step 402, the BIST controller 112 enables a normal refresh operation by de-asserting or negating the MUX control signal. As described above, the release or affirmation of the MUX control signal causes the normal RAS signal and the normal CAS signal to be changed to D.
Coupled to RAM 106. BIST controller 112
In step 404, the DRAM controller 1
It waits for the refresh operation from 08. The DRAM controller 108 detects a refresh request by monitoring the normal RAS. (In other embodiments, B
The IST controller can monitor other signals indicating a refresh cycle. 3.) BIST controller 112 increments the N: M counter once it detects a refresh cycle, step 406.

The BIST controller 112 increments the row counter at step 408. Next, BI
The ST controller 112 determines in step 410
Determine if it allows each memory entry to be refreshed twice. If the BIST controller 112 allows each memory entry to be refreshed twice, the BIST controller 1
In step 412, the MUX control signal is affirmed in order to control the DRAM 106. Once in control, BIST controller 112 verifies that the stored data is equal to the expected data, step 414. The data retention test is now complete and the flowchart 400 returns to FIG.

If BIST controller 112 has not yet allowed each memory entry to be refreshed twice, it continues at step 416. Steps 408 and 410 represent a series of steps operable with a row counter that counts each refresh operation passed to DRAM 106. As explained above,
In another embodiment of the present invention, the refresh counter 144
Monitor only the MSB of In such an embodiment, steps 408 and 410 count at least four transitions of the MSB signal before branching to step 412.

Continuing with step 416,
The BIST controller 112 determines at step 416 whether it should interrupt or "skip" the next normal refresh cycle. The BIST controller 112 determines based on the value of the N: M counter whether it should skip the next normal refresh cycle. As mentioned above, the N: M counter inserts N pauses over (M + N) refresh cycles. If the BIST controller 112 determines that it should skip the next normal refresh cycle, the BIST controller asserts the MUX control signal and disconnects the DRAM controller 108 from the DRAM 106, step 4
18. If the BIST controller 112 determines that it should not skip the next normal refresh cycle, the BIST controller returns to step 404.

Continuing from step 418, the BIST controller 112 then proceeds to step 420
It waits for the next attempted refresh cycle from the AM controller 108. The BIST controller returns to step 402 after the next attempted refresh cycle.

FIG. 5 shows a graphical representation of the steps of the flowchart shown in FIG. FIG. 5 shows the BIST controller 11
2 is useful in the description. In general, FIG. 5 shows a pattern test followed by a refresh test.
The left part of FIG. 5 shows the operation related to the pattern test. The right part of FIG. 5 shows the operation related to the data retention test.

The pattern test consists of a series of reads and writes to array 132. Each series of reads and / or writes is represented by a sloping line. A positive slope indicates a series of reads and / or writes to ascending or ascending addresses in array 132. A negative slope indicates a series of reads and / or writes to a descending or descending address in array 132. A mnemonic (mnemo) associated with each sloping line
nic). "R" and "W" indicate read and write operations, respectively. Both initials together indicate two operations on the same memory element. “0” and “1” represent the data pattern and its binary complement, respectively. As an example, BIST
The controller writes a pattern for each memory element that starts with element 127 and ends with element 0. Next, the BIST controller 112 reads a pattern from each element, checks its correctness, and writes a complementary pattern to the same address. The BIST controller 112 accesses the array 132 again in the descending order. The portion of FIG. 5 labeled "Pattern Test" shows a single execution of step 306 shown in FIG.

The data retention test consists of a series of reads, writes, and refreshes for array 132. Refresh sequences are identified by their R, W, or other lack. Refresh sequences are shown for their application to array 132. As noted above, a larger number is generated by DRAM controller 108. In this case, the first
Clearly uses the data stored in the last pattern test. As previously mentioned, interrupts or interruptions are placed in the refresh sequence to reduce the effective refresh rate. In one embodiment, a relatively large gap is inserted after a point in a set of refresh operations. In other embodiments, some relatively small gaps are inserted into the refresh sequence. In each case, each row or row is refreshed with the same data retention interval. Each refresh sequence corresponds to one execution of step 312 in FIG. Confirmation or verification (verifica)
step 414 and setting a new pattern (set new pattern s)
step) 316 is indicated by a single atomic read-write line "R0W1" shown between the first and second refresh patterns.

FIG. 6 shows a flowchart 600 of the operation of the BIST controller 112 shown in FIG. Here, V
Is equal to "1" and S is equal to "1". Also, M is set to the number of rows or rows in array 132. As a result, the BIST controller 112
A series of data retention tests will be performed to characterize the retention time of 106. Further, in this embodiment,
The BIST controller 112 uses a binary search algorithm to quickly determine the hold time.

Flow chart 600 sets the initial value of N equal to (M / 2) and adjusts the adjustment factor (adjustment).
Step 602, which begins by setting the value L of the factor to (N / 2). BIST controller 1
Next, in step 604, the data retention test shown in FIG. BIST controller 112
Then, in step 606, it is determined whether there are any more patterns to be tested at the same holding time.
If there are more patterns to be tested at the same hold time, BIST controller 112 writes this new pattern to array 132 at step 608 and returns to step 604.

If there are no more patterns to test for the same hold time, BIST controller 112 determines at step 610 whether any of the patterns has failed any of the previous hold intervals. If the previous hold interval has failed, the BIST controller 112 reduces the hold interval by subtracting L from N at step 612. If the previous hold interval has not failed, the BIST controller 112 proceeds to step 61
At 4, the holding interval is increased by adding L to N. In any case, the BIST controller 112 halves the adjustment coefficient L in step 616. Next, the BIST controller 12 sets the adjustment coefficient L
To determine if it has completed its binary search. If the adjustment factor is one or more, the binary search has not been completed. BIST controller 112 returns to step 604 and continues the test. If the adjustment factor is less than one, the binary search is complete.

FIG. 7 shows a graphical representation of each step of the flowchart shown in FIG. The BIST controller 112 initially sets N equal to half of 128. Therefore,
The BIST controller 112 initially generates 192 through 64 respectively generated by the DRAM controller 108.
Block the refresh cycle.
This strategy results in a retention test interval of 150 percent of the retention time provided by the normal refresh rate. In this example, this first retention test has passed. The BIST controller 112 then proceeds to 32
N is adjusted by adding Therefore, the BIST controller 112 uses the DRAM in the second retention test.
Each 22 generated by the controller 108
Prevents 4 to 96 refresh cycles. This strategy results in a retention test interval of 175 percent of the retention time provided by the normal refresh rate. In this example, this second retention test fails. The BIST controller 112 then adjusts N by subtracting 16. Accordingly, BIST controller 112 blocks 208 to 80 refresh cycles generated by DRAM controller 108, respectively. This strategy results in a retention test interval of 162.5% of the retention time provided by the normal refresh rate. This process continues until the adjustment factor is less than one.

[0062]

The foregoing description and illustration illustrate a number of advantages associated with the present invention. Although the invention has been described and illustrated with respect to particular embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art can make modifications and changes without departing from the spirit of the invention. For example, certain blocks can be integrated on the same circuit. Conversely, functions shown as originating from the same circuit can be split into two or more separate devices. Accordingly, the present invention is intended to embrace all such changes and modifications that fall within the scope of the appended claims.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory system configured according to the present invention.

FIG. 2 is a conceptual explanatory diagram showing a programmable register of the memory system shown in FIG.

FIG. 3 is a flowchart showing an operation of the built-in self-test controller shown in FIG. 1;

FIG. 4 is a flowchart detailing one of the steps shown in FIG. 3;

FIG. 5 is a graph representation explanatory diagram showing the steps of the flowchart shown in FIG. 3;

FIG. 6 is a flowchart showing an operation of the built-in self-test controller shown in FIG. 1;

FIG. 7 is a graph representation explanatory diagram showing the steps of the flowchart shown in FIG. 6;

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Memory system 102 DRAM control unit 104 Built-in self test (BIST) unit 106 DRAM 108 DRAM controller 110 DRAM parameter register 112 BIST controller 114 Refresh control register (RCR) 116 Comparator 118, 120, 122, 124, 126, 128, 1
30 multiplexer 132 array 134 MUX 136 row decoder 136 sense amplifier 140 column selector 142 control unit 144 refresh counter

 ────────────────────────────────────────────────── ─── Continued on front page (72) William Dawn Atwell, Spicewood, Texas, USA 69669, Route 1 Box 44 M

Claims (10)

[Claims] 1. A method of verifying data retention time in a dynamic random access memory (DRAM) using a built-in test circuit, the method comprising providing a DRAM having a plurality of rows of memory cells, each row comprising: Providing a periodic refresh operation to retain valid data; providing a refresh control circuit coupled to the DRAM, wherein the refresh control circuit comprises the DR
Providing at least one signal to the DRAM for initiating an AM refresh operation, the DRAM providing the DRA
M requiring each row to undergo a refresh operation periodically to meet the data retention time specification for M, and the refresh control circuit and the D
Providing a built-in test circuit coupled to the RAM, the built-in test circuit including a refresh control circuit for verifying an operating margin above a data retention time specification of the DRAM; A method for selectively changing a rate at which a refresh operation is performed, a method for verifying a data retention time in a DRAM using a built-in test circuit. 2. The method according to claim 1, wherein the step of providing the built-in test circuit for selectively changing a rate at which the refresh control circuit performs a refresh operation further comprises the step of performing DRAM row refresh for every N out of (M + N) refresh operations. The method of claim 1, comprising selectively inhibiting a refresh operation. 3. The method according to claim 1, wherein the step of selectively inhibiting the refresh operation of the DRAM row refresh from among the (M + N) refresh operations includes using a programmable counter in which N and M are programmable by a user. 3. The method of claim 2, wherein said programmable counter performs said prohibition, at least in part. 4. The step of providing a built-in test circuit for selectively changing a rate at which the refresh control circuit performs a refresh operation further comprises using a counter to count the number of refresh operations. And the DRAM inhibits the refresh operation of (M + N) every N, and N and M are integers and N
The method of claim 1, wherein is equal to or less than M. 5. The step of providing a built-in test circuit further comprises: testing the DRAM by applying a variable refresh rate until the built-in test circuit encounters at least a first fail of data retention. The method of claim 1, comprising the step of dynamically determining a limit for reliable data retention of the DRAM. 6. The step of allowing the built-in test circuit to dynamically determine a limit for reliable data retention of the DRAM further comprises changing a refresh interval to optimize the performance of the DRAM. The method of claim 5, comprising providing a circuit for reporting limits to a controller of the refresh control circuit. 7. The step of allowing the built-in test circuit to dynamically determine a limit for reliable data retention further comprises: scaling a rate of memory refresh at which the DRAM is refreshed. Thus, the scaling is between the normal rate at which the refresh control circuit initiates the refresh operation and a rate equal to the product of [1 / (1 + N / M)] * Normal refresh rate, where N is The method of claim 5, comprising: less than M and N and M are integers. 8. A memory test circuit for testing data retention of a DRAM, wherein the test circuit electrically monitors a data refresh signal provided to the DRAM, the test circuit comprising: (M + N) Selectively invalidating every N of the data refresh signals, where N is less than M and N and M are integers, the test circuit verifies an operating margin above the data retention time specification of the DRAM; Wherein the test circuit is clocked by a clock signal having a frequency that does not affect or change a test interval period for testing the data retention of the DRAM. Memory test circuit for testing. 9. The memory test circuit of claim 8, wherein the test circuit further comprises: a programmable circuit for allowing a user to program the value of N. 10. The test circuit may further provide a plurality of values of N from zero to (M-1) so that the memory test circuit characterizes the reliable data retention limit of the DRAM. 9. The memory test circuit of claim 8, further comprising: a characterization circuit that enables the memory test circuit.