JP2692649B2 - Measuring device and logic analyzer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a measuring device for measuring a circuit under test, and more particularly to a logic analyzer for analyzing an error in the circuit under test.

[0002]

2. Description of the Related Art When a newly developed and designed logic circuit device (circuit to be measured) is debug-evaluated, various abnormal phenomena may occur. A logic analyzer is generally used as a measuring device in order to investigate the cause of occurrence of such an abnormal phenomenon.

Conventionally, various logic analyzers have been proposed. For example, in Japanese Patent Laid-Open No. 1-170872 (hereinafter, referred to as Prior Art 1), by setting the time from outside, the measurable range is unlimitedly expanded, and the timing relationship between high-speed signals can be measured. Logic Analyzer "is disclosed. As shown in FIG. 4, the logic analyzer disclosed in the prior art 1 includes a timer circuit 31, a data sampling gate 32, a trigger detection circuit 33, a data storage memory 34, an address counter 35, and a display control gate. Has 36. The timer circuit 31 generates a clock start signal for starting writing measurement data to the data storage memory 34 after a time set from the outside from a periodic signal which is always generated from outside at a certain fixed period. Data sampling gate 32
Enables generation of a sampling clock for writing data in the data storage memory 34 by a clock start signal from the timer circuit 31. The trigger detection circuit 33 detects a trigger when the data of the measurement channel designated by an external trigger channel designation becomes "1" or "0". Data storage memory 3
4 stores an external measurement signal. The address counter 35 counts the address of the data storage memory 34. The display control gate 36 is a control gate for displaying the memory contents at the time when the trigger is detected.

Japanese Laid-Open Patent Publication No. 4-40371 (hereinafter referred to as prior art 2) discloses a "logic analyzer device" capable of detecting a time-out abnormality of a level transition timing of an observed input signal and setting it as a trigger condition. Is disclosed. As shown in FIG. 5, the logic analyzer device of the prior art 2 includes a 1-bit register 41, an exclusive OR gate 42, and a one-shot multivibrator 43.
And first and second two-input AND gates 44 and 4
5, a 8-bit register 46, a down counter 47 with preload, and a flip-flop (F / F) 48. The observed input signal is supplied to one input of the exclusive OR gate 42, and the output of the 1-bit register 41 is applied to the other input. The 1-bit register 41 selectively sets the direction of the edge (level transition timing) to be detected, and is "0" when detecting the rising edge of the observed input signal, and when detecting the falling edge. Is set to "1". The output of the exclusive OR gate 42 is the trigger input of the one-shot multivibrator 43, and is triggered by the rising edge of the exclusive OR gate 42 to output an edge detection pulse of a certain width. This edge detection pulse becomes one input of the first 2-input AND gate 44, and the enable signal is applied to the other inputs. The output of the first 2-input AND gate 44 is the load input of the 8-bit down counter 47 with preload, and the output of the second 2-input AND gate 45 is applied to its clock input. The output of the 8-bit register 46 is supplied to the 8-bit preload input of the down counter 47 with preload corresponding to each bit. The carry-out signal of the down counter 47 with preload is the clock input of the flip-flop 48, and the flip-flop 48 takes in the data input of "1" at the timing of this clock input,
It is designed to output a trigger detection signal to the output.

Japanese Unexamined Patent Publication No. 2-195447 (hereinafter referred to as prior art 3) discloses a method in which a power switch is turned off by a generated pulse to prevent a current from flowing into the LSI from the outside, and The "instantaneous power cut-off test method for semiconductor integrated circuits" for completely shutting off the power supply is disclosed. In this prior art 3, as shown in FIG. 6, the power supply terminal of the microcomputer LSI 51 is supplied with a power supply voltage via a power switch 52 composed of a transistor, and the signal terminal of the microcomputer LSI 51 has an analog switch or a control terminal. The buffer 53 is connected to prevent the inflow of current from the outside.
Further, the output terminal of the microcomputer LSI 51 is monitored by the logic analyzer 54 or the like to generate the output of the trigger signal Tr in an arbitrary state. The trigger signal Tr drives the one-shot multivibrator 55 to generate the pulse signal P. The pulse signal P shuts off the power switch 52 and the analog switch or the buffer 53 with control terminal. Thus, in Prior Art 3, the microcomputer LSI
The current is prevented from flowing into 51, and the power supply of the microcomputer LSI 51 is completely cut off.

In the logic analyzers disclosed in the prior arts 1 to 3, the measurement time is defined and set from the measurement start time to the measurement end time. However, in the logic analyzers disclosed in the above-mentioned prior arts 1 to 3, when no trigger can be detected from the circuit under measurement within the measurement time,
The logic analyzer had no information and was powered on.

[0007]

As described above, in the conventional logic analyzer (measuring device), it is defined between the measurement start time and the measurement end time set for the logic analyzer (measuring device). When no trigger is detected from the circuit under measurement within the measurement time, the logic analyzer (measurement apparatus) keeps the power-on state without any information even after the measurement is completed. Therefore, there is a problem that power is wasted.

[0008]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a measuring device (logic analyzer) capable of preventing wasteful power consumption.

The measuring device according to the present invention is a measuring device for measuring a circuit to be measured. When no information is obtained from the circuit to be measured within the measuring time, the measuring device outputs a power-off signal and a power-off signal. A power supply device having a function of stopping power supply in response to a signal.

In the above measuring device, the monitoring means is
For example, a measurement time setting circuit that can set the measurement time for the circuit under test, a trigger detection circuit that detects the trigger generated in the circuit under test, and outputs a trigger detection signal when the trigger is detected, And a timer that outputs a power-off signal when the trigger detection signal is not input. The measurement time setting circuit preferably sets the measurement time according to the measurement start time and the measurement end time.

Further, the logic analyzer according to the present invention is a logic analyzer for performing error analysis of a circuit under test, which outputs a power-off signal when no information is obtained from the circuit under test within the measurement time. And a power supply device having a function of stopping the power supply in response to the power-off signal.

In the logic analyzer, the monitoring means detects, for example, a measurement time setting circuit capable of setting a measurement time for the circuit under test, a trigger generated in the circuit under test, and a trigger when the trigger is detected. It has a trigger detection circuit which outputs a detection signal and a timer which outputs a power-off signal when the trigger detection signal is not input within the measurement time. Further, it is desirable that the measurement time setting circuit sets the measurement time according to the measurement start time and the measurement end time.

[0013]

The monitoring means outputs a power-off signal when no information is obtained from the circuit under test within the measurement time. In response to this power-off signal, the power supply device stops the power supply. Therefore, it is possible to prevent wasteful power consumption.

[0014]

Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, the logic analyzer 10 according to the present invention includes a monitoring unit 11 which outputs a power-off signal when no information is obtained from the circuit under test 20 within a measurement time, and a power-off state. And a power supply device 12 having a function of stopping power supply in response to a signal.

Referring to FIG. 2, the logic analyzer 10 according to the embodiment of the present invention includes, as a monitoring unit 11, a measurement time setting circuit 13 capable of setting the measurement time of the logic analyzer 10 and a circuit under test 20. A trigger detection circuit 14 for detecting a generated trigger and a timer 13 having a clock function are provided.

Next, with reference to FIG. 3 in addition to FIG. 2, the operation of the logic analyzer 10 according to this embodiment will be described.

The operator (not shown) sets the measurement start time and the measurement end time which define the measurement time by the measurement time setting circuit 13 (step S1). As a result, the timer 15 is notified of the measurement start time and the measurement end time (step S2). Next, the operator sets the trigger condition in the logic analyzer 10 (step S
3). At the measurement start time (YES in step S4)
S), the logic analyzer 10 starts measurement (step S5). When the trigger condition occurs in the circuit under test 20 (YES in step S6), the logic analyzer 1
The measurement result is displayed at 0 (step S7). Then, the trigger detection circuit 14 sends a trigger detection signal to the timer 15 (step S8). When the measurement end time has not come (NO in step S9), the process returns to step S6. Also,
If the trigger condition does not occur in the circuit under test 20 in step S6 (NO in step S6), step S6
Go to 9. When the measurement end time comes (YE in step S9)
S), the logic analyzer 10 ends the measurement (step S10).

After the measurement is completed, it is determined whether or not the trigger detection signal is input to the timer 15 between the measurement start time and the measurement end time (step S11). If so (YES in step S11), the measurement result is continuously displayed on the logic analyzer 10 (step S12). On the other hand, if not (NO in step S11), the timer 15 sends a power-off signal to the power supply device 12 (step S13). In response to this power-off signal, the power supply device 12 stops power supply (step S14).

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications and changes can be made without departing from the gist of the present invention. For example, the present invention is not limited to the logic analyzer and can be applied to other measuring devices. Further, it goes without saying that the monitoring unit is not limited to that of the above-described embodiment. Further, the measurement time setting circuit sets the measurement time based on the measurement start time and the measurement end time, but the setting of the measurement time is not limited to this method. That is, for example, when the measurement is started from the current time, it is sufficient to set the measurement time from the current time.

[0021]

As described above, since the measuring device (logic analyzer) according to the present invention stops the power supply when no information is obtained from the circuit under test within the measuring time, nothing is done. It is possible to prevent the measuring device (logic analyzer) from being powered on without having information, and it is possible to suppress unnecessary power consumption. Also,
By setting the measurement start time and the measurement end time as the measurement time, setting the measurement time in a time zone when there is no operator also has the advantage that the measuring device can measure the circuit under test even when there is no operator. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic analyzer according to the present invention.

FIG. 2 is a block diagram showing a configuration of a logic analyzer according to an embodiment of the present invention.

FIG. 3 is a flowchart for explaining the operation of the logic analyzer shown in FIG.

FIG. 4 is a block diagram showing a configuration of a logic analyzer disclosed in Prior Art 1.

FIG. 5 is a block diagram showing a configuration of a logic analyzer device disclosed in Prior Art 2.

FIG. 6 is a block diagram showing a configuration of a power interruption test device for a microcomputer LSI disclosed in Prior Art 3;

[Explanation of symbols]

 10 Logic Analyzer (Measuring Device) 20 Circuit Under Test 11 Monitoring Unit 12 Power Supply Device 13 Measurement Time Setting Circuit 14 Trigger Detection Circuit 15 Timer

Claims (5)

(57) [Claims] 1. A monitoring device for measuring a circuit under test (20), which outputs a power-off signal when no information is obtained from the circuit under test (20) within a measuring time. Means (1
Set 1), in response to the power-off signal, a power supply device (12) having a function of stopping the power supply, the monitoring unit (11), the measurement time for the circuit to be measured (20) Possible
The trigger generated in the measurement time setting circuit (13) and the circuit under measurement (20) is detected,
Outputs a trigger detection signal when the trigger is detected
The trigger detection circuit (14) and when the trigger detection signal is not input within the measurement time.
The timer (15) that outputs the power-off signal.
A measuring device characterized by: Wherein said measuring time setting circuit (13) sets the measurement time by the measurement start time and measurement end time measurement device according to claim 1. 3. A logic analyzer (10) for error analysis of a circuit under test (20) outputs a power-off signal when no information is obtained from the circuit under test (20) within a measurement time. Monitoring means (1
A logic analyzer comprising: 1) and a power supply device (12) having a function of stopping power supply in response to the power-off signal. 4. The monitoring means (11) detects a measurement time setting circuit (13) capable of setting a measurement time for the circuit under measurement (20), and a trigger generated in the circuit under measurement (20). Then
A trigger detection circuit (14) that outputs a trigger detection signal when the trigger is detected, and a timer (15) that outputs the power-off signal when the trigger detection signal is not input within the measurement time period. The logic analyzer according to claim 3 . 5. The logic analyzer according to claim 4 , wherein the measurement time setting circuit (13) sets the measurement time according to a measurement start time and a measurement end time.