JPH08139276A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To enable high precision judgment of the extent of deterioration of an actual circuit without causing increase of outside terminals regarding a semiconductor integrated circuit with a built-in deterioration monitor circuit which monitors the extent of deterioration of a circuit. CONSTITUTION: The device is provided with deterioration monitor circuits 201 to 20n with a monitor wiring, a deterioration extent judgment circuit 28 including an RAM 37 for storing remaining life data of an actual circuit 15 which corresponds to the number of deterioration monitor circuits disconnected in a monitor wiring and a register 42. Remaining life data of the actual circuit 15 corresponding to the number of deterioration monitor circuits disconnected in a monitor wiring is output from an RAM and is stored in the register 42. Remaining life data of the actual circuit 15 stored in the register 42 is output to an outside through a data input/output buffer 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a deterioration monitor circuit for monitoring the degree of deterioration of the circuit.

The degree of integration of semiconductor integrated circuits is increasing year by year, and the miniaturization of elements is progressing. As a result, the life is becoming so short that it cannot be ignored.

Here, the causes of shortening the life include disconnection of wiring due to electromigration and deterioration of the transistor due to hot carriers, and efforts are made to extend the life by devising the material and structure of the element. However, as miniaturization advances, the problem of shortening the life that cannot be ignored will not disappear.

For this reason, when a deterioration monitor circuit is built in and it can be determined that the remaining life is short, measures such as replacement are immediately taken to prevent accidental damage due to a failure. Development and research are being conducted.

[0005]

2. Description of the Related Art Conventionally, as a semiconductor integrated circuit of this type,
FIG. 10 proposes a device having a built-in deterioration monitor circuit as shown in the circuit diagram.

In FIG. 10, 1 is a VCC power supply line for supplying a power supply voltage VCC, 2 and 3 are resistors, 4 and 5 are wirings, 6 is a buffer, and 7 is a test signal output terminal (external) for outputting a test signal TEST. Terminal).

Here, the wiring 4 is a circuit that achieves the function originally required for the semiconductor integrated circuit in which the deterioration monitor circuit is built, that is, a wiring of the minimum width of a so-called actual circuit (not shown). Is also made thinner, so that the disconnection due to deterioration will occur at the earliest on the chip.

In this deterioration monitor circuit, while the wiring 4 is not broken, the test signal TEST is set to H level.
When the (high) level signal is output and the wire 4 is disconnected, the L (low) level signal is output as the test signal TEST.

That is, the semiconductor integrated circuit incorporating this deterioration monitor circuit determines that the life of the actual circuit is short when the L level signal is output as the test signal TEST.

[0010]

In the semiconductor integrated circuit having the deterioration monitor circuit built-in, the degree of deterioration of the actual circuit is determined only in two steps: whether the wire 4 is broken or not. However, there is a problem that the degree of deterioration of the actual circuit cannot be determined with high accuracy.

In the case where a plurality of deterioration monitor circuits are built in and the test signals TEST output from the plurality of deterioration monitor circuits are all output to the outside, the degree of deterioration of the actual circuit is determined. Although the determination can be performed in multiple stages, there is a problem in that the number of external terminals increases in this case.

In view of the above points, an object of the present invention is to provide a semiconductor integrated circuit capable of accurately determining the degree of deterioration of an actual circuit without increasing the number of external terminals. .

[0013]

FIG. 1 is a diagram for explaining the principle of the present invention. The semiconductor integrated circuit according to the present invention is a real circuit 1
In addition to 0, deterioration monitor circuits 11 _{1 to} 11 _n (deterioration monitor circuits 11 _{3 to} 11 _n-1 are not shown), a deterioration degree judgment circuit 12 and a deterioration degree judgment data holding circuit 13 are provided. To be done.

Here, the deterioration monitor circuits 11 _{1 to} 11 _n are
Each of the monitor signals SA1, SA2, SA has a monitor element for monitoring the deterioration of the actual circuit 10, and indicates with a different logic level whether or not the monitor element is defective.
It outputs n.

Further, the deterioration degree determination circuit 12 includes monitor signals SA1 to SA1 output from the deterioration monitor circuits 11 _{1 to} 11 _n.
The degree of deterioration of the actual circuit 10 is determined based on SAn, and deterioration degree determination data is output.

Further, the deterioration degree determination data holding circuit 13
Is to hold the deterioration degree judgment data output from the deterioration degree judgment circuit 12 in a state in which it can be read from the outside.

[0017]

In the present invention, the deterioration degree determination circuit 12 is
On the basis of the monitor signal SA1~SAn output from a plurality of deterioration monitoring circuit 11 ₁ to 11 _n, i.e., based on the deterioration condition of the plurality of deterioration monitoring circuit 11 ₁ to 11 _n, the actual circuit 1
The degree of deterioration of 0 is determined.

As a result, the degree of deterioration of the actual circuit 10 can be determined in multiple steps rather than the two steps as in the conventional example, so that the degree of deterioration of the actual circuit 10 can be determined with high accuracy.

Further, in the present invention, the deterioration degree judgment data holding circuit 13 holds the deterioration degree judgment data output from the deterioration degree judgment circuit 12 in a state in which it can be read out from the outside.

Therefore, the deterioration degree judgment data held in the deterioration degree judgment data holding circuit 13 can be read out to the outside through the data output terminal or the data input / output terminal normally provided in the chip. The provision of the deterioration monitor circuits 11 _{1 to} 11 _n does not increase the number of external terminals.

[0021]

FIG. 2 is a circuit diagram showing the configuration of an embodiment of the present invention. In FIG. 2, 15 is an actual circuit, 16 is an address buffer to which an address signal is input from the outside, and 17 is an address bus that forms a transmission path of the address signal output from the address buffer 16.

Reference numeral 18 is a data input / output buffer for inputting data supplied from the outside and outputting the data to the outside, and 19 is a data bus forming a data transmission path.

Further, reference numerals 20 ₁ , 20 ₂ and 20 _n are deterioration monitor circuits for monitoring deterioration of wiring due to electromigration and outputting monitor signals SA1, SA2 and SAn, and deterioration monitor circuits 20 _{3 to} 20 _n-1. Are not shown.

FIG. 3 is a circuit diagram showing a configuration of a deterioration monitoring circuit 20 _1, in FIG. 3, 22 is a VCC power supply line for supplying a power supply voltage VCC, 23 are resistors, 24 is the wiring of the minimum width of the actual circuit 15 The monitor wiring is formed thinner than that, and 25 is an inverter.

[0025] In the deterioration monitoring circuit 20 _1, if the disconnection monitor lines 24 does not occur, the node 26
Level becomes L level, and the monitor signal SA1 output from the inverter 25 becomes H level.

On the other hand, when the monitor wiring 24 is broken, the level of the node 26 becomes H level, and the monitor signal SA2 output from the inverter 25 becomes L level.

The deterioration monitor circuits 20 _{2 to} 20 _n are also provided with resistors, monitor wirings, and inverters like the deterioration monitor circuit 20 ₁ , but the deterioration monitor circuit 2
In 0 _{1 to} 20 _n , monitor wirings having different patterns and widths are provided so that the monitor conditions are different.

Further, in FIG. 2, 28 is the deterioration degree determination circuit for determining the degree of deterioration of the real circuit 15, 29 is a monitor signal SA1~SAn logic level of output from deterioration monitoring circuit 20 ₁ to 20 _n Is a monitor signal change detection circuit for detecting a change in

FIG. 4 is a circuit diagram showing the configuration of the monitor signal change detection circuit 29. In FIG. 4, 31 ₁ , 3
1 ₂ and 31 _n are latch circuits that latch the monitor signals SA1, SA2, and SAn output from the deterioration monitor circuits 20 ₁ , 20 ₂ , and 20 _n , respectively, in synchronization with the clock signal CLK.

Note that, in synchronization with the clock signal CLK, the latch circuits 31 _{3 to} 3 for latching the monitor signals SA3 to SAn-1 output from the deterioration monitor circuits 20 _{3 to} 20 _n-1.
1 _n-1 is not shown.

Further, 32 ₁ , 32 ₂ , and 32 _n are latch circuits 31 ₁ , 31 ₂ , and 31 _n in synchronization with the clock signal / CLK, which has an inverted relationship with the clock signal CLK.
Is a latch circuit that latches the output signals SB1, SB2, and SBn.

Incidentally, in synchronization with the clock signal / CLK,
Output signals SB3 to SBn- of the latch circuits 31 _{3 to} 31 _n-1
The latch circuits 32 _{3 to} 32 _n- 1 for latching ₁ are not shown.

Further, 33 ₁ and the output signal SC1 of the output signal SB1 of the latch circuit 31 ₁ latches circuit 32 ₁ Ex-O
R (exclusive OR) processing Ex-OR circuit, 33 ₂ Ex-OR circuit and an output signal SC2 of the latch circuit 31 and _second output signals SB2 and latch circuit 32 ₂ is Ex-OR processing, 33
_n is the output signal SBn of the latch circuit 31 _n and the latch circuit 32.
It is an Ex-OR circuit that performs Ex-OR processing on the output signal SCn of _n .

The output signal SB3 of the latch circuit 31 ₃
Ex-OR circuit 33 to Ex-OR processing an output signal SC3 of the latch circuit 32 ₃ and ₃ to the latch circuit 31 _n-1 of the output signal SBn-1 and the latch circuit 32 _n-1 of the output signal SCn
The Ex-OR circuit 33 _n-1 for Ex-ORing -1 and -1 is omitted in the drawing.

Reference numeral 34 is an OR for ORing the output signals SD1 to SDn of the Ex-OR circuits 33 _{1 to} 33 _n.
Circuit.

FIG. 5 is a waveform diagram for explaining the operation of the monitor signal change detection circuit 29. FIG. 5A shows the clock signal CLK and FIG. 5B shows the clock signal / CLK.

Further, FIG. 5C shows the monitor signal SA1 output from the deterioration monitor circuit 20 ₁ , and FIG. 5D shows the monitor signals SA2 to SAn output from the deterioration monitor circuits 20 _{2 to} 20 _n.
Is shown.

FIG. 5E shows the output signal SB1 of the latch circuit 31 ₁ , and FIG. 5F shows the output signals SB2 to SBn of the latch circuits 31 _{2 to} 31 _n .

Further, FIG. 5G shows the output signal SC1 of the latch circuit 32 ₁ , and FIG. 5H shows the output signals SC2 to SCn of the latch circuits 32 _{2 to} 32 _n .

FIG. 5I shows the output signal SD1 of the Ex-OR circuit 33 ₁ , FIG. 5J shows the output signals SD2 to SDn of the Ex-OR circuits 33 _{2 to} 33 _n , and FIG. 5K shows the output signal SE of the OR circuit 34. ing.

[0041] That is, when the disconnection monitor lines of deterioration monitoring circuit 20 ₁ to 20 _n has not occurred, the monitor signal SA1~SA output from deterioration monitoring circuit 20 ₁ to 20 _n
n = H level.

As a result, in this case, the latch circuits 31 ₁ ...
31 _n output signals SB1 to SBn = H level, output signals SC1 to SCn of latch circuits 32 _{1 to} 32 _n = H level,
Output signals SD1 to SDn of Ex-OR circuits 33 _{1 to} 33 _n =
The output signal SE of the OR circuit 34 is L level.

From this state, for example, the deterioration monitor circuit 2
When the monitor wiring 24 of 0 ₁ is disconnected, the monitor signal SA1 = L output from the deterioration monitor circuit 20 ₁
Level.

As a result, when the clock signal CLK = H level, the latch circuit 31 ₁ latches the L level monitor signal SA1 output from the deterioration monitor circuit 20 ₁ and outputs the output signal SB1 of the latch circuit 31 _1. = L level.

At this time, since the output signal SC1 of the latch circuit 32 ₁ is at H level, the output signal SD1 of the Ex-OR circuit 33 ₁ changes to H level and the output signal of the OR circuit 34 becomes SE = H level. Change.

After that, the clock signal CLK = L level,
When inverted to the clock signal / CLK = H level, the latch circuit 32 ₁ latches the output signal SB1 of the latch circuit 31 ₁ at L level.

As a result, the output signal S of the latch circuit 32 ₁
Since C1 = L level, the output SD1 of the Ex-OR circuit 33 ₁ returns to L level, and the output signal SE of the OR circuit 34
= Return to L level.

In this way, the monitor signal change detection circuit 29
Is every time any one of the monitor signals SA1 to SAn output from the deterioration monitor circuits 20 _{1 to} 20 _n changes from the H level to the L level, that is, the deterioration monitor circuits 20 _{1 to} 20 _n.
Each time a disconnection occurs in the monitor wiring of the clock signal C
An H level signal having the same pulse width as LK is output as a monitor signal change detection signal.

Further, in FIG. 2, reference numeral 36 is a counter for counting the number of H level signals output from the monitor signal change detection circuit 29, that is, the number of deterioration monitor circuits in which a disconnection occurs in the monitor wiring.

Further, 37 is a RAM (random access memory) for storing the remaining life data of the actual circuit 15 as deterioration degree judgment data of the actual circuit 15 corresponding to the number of deterioration monitor circuits in which the monitor wiring is broken. The count value of the counter 36 is supplied as an address.

Here, the relationship between the number of deterioration monitor circuits in which the monitor wiring is broken and the remaining life of the actual circuit 15 is as follows:
It can be obtained by performing an acceleration test in advance, and is shown by a solid line 39 in FIG. 6, for example.

Therefore, in the present embodiment, as shown in FIG. 7, the remaining life data corresponding to the solid line 39 shown in FIG. 6 is written in the RAM 37 as deterioration degree determination data.

Here, the relationship between the number of deterioration monitor circuits in which the monitor wiring is broken and the remaining life of the actual circuit 15 is as follows.
The number of deteriorated monitor circuits in which the monitor wiring is broken and the remaining life of the actual circuit 15 are changed, for example, by changing the manufacturing process.
It changes as shown by the broken line 40 in FIG.

Therefore, when the manufacturing process is changed and the relationship between the number of deterioration monitor circuits in which the monitor wiring is broken and the remaining life of the actual circuit 15 becomes as shown by a broken line 40 in FIG. For the product manufactured by the new manufacturing process, the remaining life data of the actual circuit 15 corresponding to the broken line 40 is written in the RAM 37.

In FIG. 2, reference numeral 42 is a register for storing the remaining life data output from the RAM 37. When the monitor signal change detection circuit 29 outputs an H level signal, the H level signal is rewritten. As a result, the remaining life data of the actual circuit 15 newly output from the RAM 37 is stored.

Further, by inputting an address signal designating the register 42 to the address buffer 16 and supplying a read instruction signal to a predetermined external terminal, the remaining life data of the actual circuit 15 stored in the register 42 is input. It is configured to be output to the outside via the output buffer 18.

In this embodiment, the counter 3
6, the RAM 37 and the register 42 are
It is configured to be backed up by a backup power supply.

In the present embodiment having such a configuration, each time the logical level of any one of the monitor signals SA1 to SAn output from the deterioration monitor circuits 20 _{1 to} 20 _n changes, that is, the deterioration monitor circuit 20. _The monitor signal change detection circuit 29 outputs an H level signal as a monitor signal change detection signal each time a disconnection occurs in any of the monitor wirings _{1 to} 20 _n .

The counter 36 counts the number of H level signals output from the monitor signal change detection circuit 29 and supplies the count value to the RAM 37 as an address signal.

Further, the RAM 37 corresponds to the address signal supplied from the counter 36, that is, the actual circuit 1 corresponding to the number of deterioration monitor circuits in which the monitor wiring is broken.
The remaining life data of 5 is output.

Further, the register 42 stores the remaining life data of the actual circuit 15 output from the RAM 37, using the H level signal output from the monitor signal change detection circuit 29 as a rewrite instruction signal.

Here, regarding the remaining life data of the actual circuit 15 stored in the register 42, an address signal designating the register 42 is input to the address buffer 16 and a read instruction signal is supplied to a predetermined external terminal. Thus, the data can be output to the outside via the data input / output buffer 18.

Here, according to this embodiment, the remaining life data of the actual circuit 15 corresponding to the number of deterioration monitor circuits in which the monitor wiring is broken can be known, and the actual circuit 1 can be obtained.
The degree of deterioration of the actual circuit 15 can be determined with high accuracy because the degree of deterioration of No. 5 can be known in multiple steps instead of two steps as in the conventional example.

Further, according to the present embodiment, by designating the register 42 by the address signal, the register 42 is
There through the data output buffer 18 and the remaining service life data of the real circuit 15 to store, i.e., it is possible to output to the outside via the data input and output terminals provided to the normal to the chip, deterioration monitoring circuits 20 ₁ ~ The provision of 20 _n does not increase the number of external terminals.

Further, according to the present embodiment, when the relationship between the number of deterioration monitor circuits in which the monitor wiring is disconnected and the remaining life of the actual circuit 15 changes due to a change in the manufacturing process, a new manufacturing process is performed. RAM 37 of the product manufactured by the process
It is only necessary to change the remaining life data of the actual circuit 15 to be written to, and it is possible to obtain a special effect that there is no need to change the circuit.

In the above embodiment, the deterioration monitor circuits 20 _{1 to} 20 _n for monitoring the deterioration of the wiring due to electromigration have been described. However, instead of this, FIG. Incorporate multiple deterioration monitor circuits as shown below, or
Both the deterioration monitor circuits 20 _{1 to} 20 _n and the deterioration monitor circuit shown in FIG. 8 may be incorporated.

The deterioration monitor circuit shown in FIG.
It is intended to monitor the deterioration of the S transistor due to hot carriers.

In FIG. 8, reference numeral 44 is an inverter to which the clock signal CLKA is input, 45 is a VCC power supply line, and 46.
Is a pMOS transistor, and 47 is an nM forming a monitor element.
It is an OS transistor.

Further, 48 is the output signal S of the inverter 44.
An AND circuit for ANDing the F and the clock signal CLKB, and 49 is an RS flip-flop circuit. The RS flip-flop circuit 49 inputs the output signal SG of the AND circuit 48 to the set terminal S, The reset signal RESET is input to the reset terminal R and a monitor signal is output to the positive phase output terminal Q.

FIG. 9 is a waveform diagram showing the operation of the deterioration monitor circuit. FIG. 9A shows the clock signal CLKA,
9B shows a clock signal CLKB, and FIG. 9C shows an inverter 4
4 shows the output signal SF, FIG. 9D shows the output signal SG of the AND circuit 48, and FIG. 9E shows the monitor signal output from the RS flip-flop circuit 49.

That is, in the inverter 44, before the deterioration of the nMOS transistor 47 due to hot carriers, when the clock signal CLKA changes from the H level to the L level, the pMOS transistor 46 = ON, nM.
The OS transistor 47 is turned off, and the VCC power supply line 4
5 to the output wiring 50 via the pMOS transistor 46
A current flows through the output signal SF and the output signal SF of the inverter 44 becomes H level.

On the other hand, the clock signal CLKA is L
When the level changes from H level to pMOS transistor 46 = OFF and nMOS transistor 47 = ON, a current flows from the output wiring 50 to the ground side through the nMOS transistor 47, and the output signal SF of the inverter 44 is output.
Becomes L level.

Before the nMOS transistor 47 is deteriorated by hot carriers, the current driving capability of the nMOS transistor 47 is large and the drain-source current I _DS of the nMOS transistor can be increased.
The delay when the output signal of the inverter 44 changes from the H level to the L level can be reduced.

Here, in this example, the clock signal CLK
Since the L level part of A and the H level part of the clock signal CLKB do not temporally overlap, the H level part of the output signal SF of the inverter 44,
The H level portion of the clock signal CLKB does not temporally overlap, the output signal SG of the AND circuit 48 maintains the L level, and the monitor signal output from the RS flip-flop circuit 49 also maintains the L level. become.

[0075] However, when the nMOS transistor 47 is deteriorated by hot carriers, the current driving capability of the nMOS transistor 47 is reduced, resulting in reduced current I _DS which can flow between the drain and the source.

Therefore, when the clock signal CLKA changes from the L level to the H level, the output wiring 50 outputs nM.
The current that can flow to the ground side via the OS transistor 47 decreases, and the output signal SF of the inverter 44 is delayed considerably from the H level to the L level. Level part,
The H level portion of the clock signal CLKB overlaps in time.

Therefore, when the nMOS transistor 47 deteriorates due to hot carriers, the output signal SG of the AND circuit 48 intermittently becomes the H level, and the AND circuit 48.
When the H-level output signal SG is output from RS,
The flip-flop circuit 49 is set, and the monitor signal output from the RS flip-flop circuit 49 becomes H level.

The change in the logic level of the monitor signal output from the deterioration monitor circuit can be detected by the monitor signal change detection circuit having the same structure as the monitor signal change detection signal shown in FIG.

Therefore, the deterioration monitor circuits 20 _{1 to} 20 _n
If a plurality of deterioration monitor circuits as shown in FIG. 8 are incorporated instead, the deterioration of the nMOS transistor due to hot carriers can be monitored and the remaining life of the actual circuit 15 can be determined with high accuracy.

When the deterioration monitor circuits 20 _{1 to} 20 _n and the deterioration monitor circuit shown in FIG. 8 are incorporated, deterioration of wiring due to electromigration and nMOS are caused.
Monitors the deterioration of transistors due to hot carriers,
The remaining life of the actual circuit 15 can be determined with high accuracy.

In this case, the deterioration monitor circuit shown in FIG. 8 can determine the remaining life of the actual circuit 15 with higher accuracy by incorporating a plurality of circuits having different monitor conditions.

[0082]

As described above, according to the present invention, a plurality of deterioration monitor circuits are provided so that the degree of deterioration of an actual circuit can be known in multiple stages instead of two stages as in the conventional example. In addition, the deterioration degree determination data (for example, remaining life data) indicating the degree of deterioration of the actual circuit can be externally read out through the data output terminal or the data input / output terminal normally provided in the chip. Since it is configured so that the degree of deterioration of the actual circuit can be determined with high accuracy without increasing the number of external terminals.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a deterioration monitor circuit that constitutes an embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a monitor signal change detection circuit that constitutes an embodiment of the present invention.

FIG. 5 is a waveform diagram for explaining the operation of the monitor signal change detection circuit that constitutes an embodiment of the present invention.

FIG. 6 is a diagram showing the relationship between the number of deterioration monitor circuits in which the monitor wiring is broken and the remaining life of the actual circuit.

FIG. 7 is a diagram showing an example of remaining life data of an actual circuit written in a RAM which constitutes an embodiment of the present invention.

FIG. 8 is a circuit diagram showing another example of the deterioration monitor circuit.

9 is a waveform chart for explaining the operation of the deterioration monitor circuit shown in FIG.

FIG. 10 is a circuit diagram showing a configuration of an example of a conventional deterioration monitor circuit.

[Explanation of symbols]

 (Figure 1) SA1, SA2, SAn monitor signals

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location G01R 31/28 H01L 21/66 W 7735-4M

Claims (3)

[Claims] 1. A plurality of deterioration monitor circuits having a monitor element for monitoring deterioration of an actual circuit and outputting a monitor signal indicating whether or not the monitor element is defective at different logic levels, and a plurality of these deterioration circuits. A deterioration degree determination circuit that determines the degree of deterioration of the actual circuit based on the monitor signal output from the monitor circuit and outputs deterioration degree determination data, and the deterioration degree determination data output from the deterioration degree determination circuit And a deterioration degree determination data holding circuit that holds the data in a state in which the data can be read from the outside. 2. The semiconductor integrated circuit according to claim 1, wherein a part or all of the monitor elements included in the plurality of deterioration monitor circuits are configured so as to have different monitor conditions. 3. A monitor signal change detection circuit that detects a change in the logic level of the monitor signal and outputs a monitor signal change detection signal each time the logic level of the monitor signal changes. A counter that counts the number of the monitor signal change detection signals output from the monitor signal change detection circuit, and stores deterioration degree determination data corresponding to the number of deterioration monitor circuits in which the monitor element has become defective, 2. A storage circuit for outputting deterioration degree judgment data corresponding to the number of deterioration monitor circuits in which the monitor element judged from the count value of the counter has become defective. 2. The semiconductor integrated circuit according to 2.