JPH0621961B2 - Abnormality diagnosis device for sequencer - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a sequence control device, and more particularly to the investigation of the cause of a sudden abnormal phenomenon occurring in an electronic sequence control device, that is, a programmable controller (hereinafter abbreviated as PCs). Regarding useful equipment.

[Background of the Invention]

With the progress of semiconductor electronic technology, PCs have come to be widely used for controlling production equipment. By the way, the sequence control program of the PCs is applied to an actual production line to sufficiently perform the adjustment debugging, and then the production line is put into actual operation. After going into actual operation, many systems have problems in which the detailed cause cannot be determined. Among these problems, the ones that have some reproducibility are:
It is possible to elucidate the mechanism of failure occurrence by creating situations when trouble occurs.

However, when the trouble is not reproducible and the abnormal phenomenon occurs only once a month, it is often not clear under what circumstances the trouble occurred. Especially when the abnormal phenomenon occurs,
This is a particularly serious problem in the case where production is seriously damaged, a production line is stopped for a very long time to return to normal operation, or a processed product being manufactured is defective.

As a conventional method of dealing with such a low reproducibility frequency, the situation of the site before and after the trouble occurred is heard as much as possible from the site worker,
I was equipped with a special recording device to record the situation when the next phenomenon occurred again.

In general, accurate data cannot be obtained as information obtained from field workers, and many problems must be experienced before the problems converge, which usually takes a lot of time.

In addition, in order to connect a special recording device to record an abnormal phenomenon, the user has to purchase an expensive recording device, and it is difficult to install the recording device in a narrow production site. In order to operate the recording device for a long time, the environment such as temperature, humidity and dust must be created.

The control equipment installed in the field is designed to operate normally even in a very bad environment, but the measurement recording equipment is not designed to be harsh for a long time, not only for a short time. Therefore, the measurement and recording device must be continuously monitor-operated.

[Object of the Invention]

An object of the present invention is to mainly store and retain a control state in an arbitrary period before and after an abnormal state occurs in a memory provided in the PCs in order to elucidate the cause of the abnormal state of the field equipment which is rarely reproduced. It is another object of the present invention to provide a sequencer abnormality diagnosis device capable of easily causing a cause of trouble.

[Outline of Invention]

In order to achieve the above-mentioned object of the present invention, the present invention provides a first memory for storing the state of an output process input / output device in an abnormality diagnosis device for a sequencer that periodically controls a relay ladder program, A second memory for aligning and storing randomly distributed information on one memory;
A third memory for storing information written from the second memory at a predetermined timing, a control circuit for controlling timing of writing from the second memory to the third memory and stop of writing, and A display device which is detachably connected to the sequencer through a communication line and which displays based on the information stored in the third memory,
The control circuit includes a switch for instructing the start of writing from the second memory to the third memory, a write interval setting circuit for variably setting the write interval at an interval that is an integral multiple of a sequence cycle, and the second A write stop timing setting circuit that can variably set a write stop timing from the memory to the third memory, and an address control circuit that controls the third memory write address.

Example of Invention

FIG. 2 shows the configuration of a general PCs1. The memory 11 of the PCs 1 stores a sequence command for controlling the field facility 2. Then, the CPU 12 of the PCs 1 controls the ON / OFF state of the corresponding device of the field facility 2 through the input process input / output device 13 (hereinafter abbreviated as PI / O) to generate
The signal level is adjusted so that signals can be exchanged with the device 12, and the ON / OFF state is adjusted by the PI / O controller 14
ON / OF the PI / O image memory 15 in the
The F state is copied with a pattern of "1" and "0".

The CPU 12 of the PCs 1 reads the signals of the input B and the input C from the PI / O image memory 15 in accordance with the sequence command stored in the memory 11 and performs the sequence operation. The calculation result is "1" (when ON) at the corresponding memory address of the PI / O image memory 15,
It is written as "0" (when OFF). This ON / O
ON / OFF for the corresponding field equipment 2 according to the FF condition
The signal of is output.

In the PI / O image memory 15, not only the external input signal group and the external output signal group but also the PCs1 internal contact signal group, the internal timer signal, the internal counter signal group, etc., which play the role of auxiliary relays It operates as a processing buffer memory. Normally, the PI / O image memory 15 stores 1 bit and 1 address for each point of each signal group. This is because it takes time for the information of the corresponding bit to be cut out to catch ON / OFF of the corresponding signal if the CPU 12 has input / output information of a plurality of bits per address when performing the sequence operation. This is because the result processing speed decreases.

By the way, it is assumed that a trouble occurs while executing the sequence control. Consider, for example, the case where there is a tank as shown in FIG. It is assumed that the program is designed so that the agitator 33 does not normally rotate unless the float switch 32 at the upper limit level of the tank 31 is turned on. However, it is assumed that the motor 34 of the agitator 33 is rotated even though the tank 31 is not filled up once every few months (malfunction). This condition rarely occurs, and it is extremely difficult to constantly monitor why it occurs.

An embodiment of the present invention will be described below with reference to FIG.

A large number of signals are all stored in the PI / O image memory 15 of the PCs 1, but when the control program is executed, the ON / OFF information is read randomly from each place of the PI / O image memory 15 when necessary. I am writing. However, in the sequence control target example shown in FIG. 3, the signals to be checked in order to analyze this trouble are the upper limit switch 32, the ON / OFF signal of the motor 34 of the agitator 33, the motor start automatic / manual mode, the switching signal 35, etc. PI / O with only various signals
It is extremely difficult to record the ON / OFF state of each signal randomly existing in the image memory 15 by picking up from this memory address.

The PCs 1 can extremely simply collect the contents of the PI / O image memory 15 in a specific memory area at a high speed. That is, as shown in FIG. 4, information about points which are thought to be involved in the cause of the failure is put in by the application relay ladder command so as to be collected in the diagnostic memories 1 to n by the sequence command. By executing the relay ladder program in FIG. 4, diagnostic information randomly arranged on the PI / O image memory 15 can be transferred at high speed to the setting memory area. That is, in each sequence cycle, the signal group randomly existing in the PI / O image memory 15 can be stored in the diagnostic memory 41 in an orderly manner as shown in FIG.

The operation of the PCs 1 for monitoring an abnormality will be described with reference to FIG. When it is desired to monitor an abnormality, the diagnostic recording start switch 27 is turned on to turn on the corresponding bit 26 of the PI / O image memory 15. A signal based on this bit 26 enters as a set signal of the copy start flip-flop 310, and the output of the copy start flip-flop 310 turns ON.

Based on the output of the sequence program start timer 300 that generates the timing pulse of the sequence cycle,
The diagnostic memory copy timing counter 341 is incremented every sequence cycle. In the diagnostic memory copy timing counter set value register 340, the number of executions that defines how many times a sequence cycle is executed to copy the contents of the diagnostic memory 41 to the diagnostic memory storage buffer memory 42 is set and recorded.
Then, in the comparator 342, the content A of the diagnostic memory copy timing counter 341 and the content B of the diagnostic memory copy timing counter setting value register 340 are compared, and if they match (A = B), the copy request cycle signal 343 is output. It This copy request cycle signal 34
3 is also used as a reset signal for the diagnostic memory copy timing counter 341. When the copy request cycle signal 343 is output, the output 311 of the copy start flip-flop 310 described above is turned on, and the signal 301 indicating the timing of the sequence cycle, which is the output of the sequence program activation timer 300, is turned on. The copy signal 346 is turned on as the output of the AND circuits 344 and 345, and the contents of the diagnostic memory 41 are written in the diagnostic memory storage buffer memory 42.

The diagnostic memory storage buffer 42 has a ring counter buffer format, and a buffer address counter 350 indicates which address should be copied next. This counter stores the contents of the diagnostic memory 41 in the diagnostic memory storage buffer 42. Each time copying is performed, the copy request signal 346 counts up by +1 to reach the final address of the diagnostic memory storage buffer, and the comparator 352 confirms that the content of the buffer address counter 350 is equal to the content of the buffer size setting register 351. When it is detected, the buffer address counter 350 is cleared to 0. And
The contents of the buffer memory 42 are constantly overwritten with new data and recorded. When the diagnostic recording stop command is executed, the operation to know that copying of the diagnostic memory contents to the diagnostic memory storage address must be stopped after a predetermined sequence cycle and to indicate that an external error has occurred (For example, abnormal lamp lighting, buzzer sound, etc.) is performed (described by the sequence user program).

By turning on the diagnostic recording start switch 27, PI
The corresponding bit 26 of the / O image memory 15 is turned ON. A signal based on this bit 26 is input as a reset signal for the copy stop flip-flop 320, and the output of the copy stop flip-flop 320 is turned off. That is, in a normal state, the output of the flip-flop 320 is O.
It becomes FF.

On the other hand, when a trouble occurs, the signal based on the bit 25 in the PI / O image memory 15 indicating whether the trouble has occurred is turned on, and the copy stop flip-flop 320
, And the output 321 of the copy stop flip-flop 320 is turned on. That is, when an abnormality occurs, the output 321 of the copy stop flip-flop 320 becomes O.
N.

A signal indicating the copy timing, which is an integral multiple of the sequence cycle, is input to the copy number counter 335,
At the time of occurrence of an abnormality, after a diagnostic recording stop command (a state in which the output 321 of the copy stop flip-flop 320 is turned on),
The number of copy timings elapsed is counted and stored. When an abnormality occurs, the register 334 stores the number of sequence cycles after the diagnostic recording stop instruction,
A specified number of times whether to stop copying from the diagnostic memory 41 to the diagnostic memory storage buffer 42 is set. When the comparator 336 confirms that the value of the copy number counter 335 after occurrence of an abnormality matches, a signal 337 for stopping the copy of the diagnostic memory 41 is output, the copy start flip-flop 310 is reset, and the copy operation is stopped. Let At this time, if 0 is set as the prescribed number of times, a copy is immediately made when an abnormality occurs, so that data 421 showing the movement immediately before the abnormality occurrence can be obtained as shown in FIG. 6 (1). If 0 <specified line n <diagnostic memory storage buffer capacity, as shown in FIG.
The data of 1 and the data of the rear 422 are known, and if the specified number of times is the buffer capacity, the data 422 on the movement after the occurrence of the abnormality can be found as shown in FIG. 6 (3).

After appearing from the abnormal phenomenon as equipment, as shown in Fig. 7,
When the programming device 7 and the display device 8 such as a CRT are connected to the PCs via the communication port 6 and the program for the logic analyzer function of the programming device 7 is activated, the programming device 7 causes the elapsed time of the diagnostic memory 41 to pass. Information of the diagnostic memory storage buffer 15 indicating
The address counter 350 indicating the final trace address + 1 is read, and the ON / OFF state is displayed on the display device 8 with the lapse of time as the horizontal axis, for example, as shown in FIG.
If the information in the diagnostic memory 41 cannot be displayed on one screen of the display device 8, it is possible to scroll up, down, left, and right to make it easier to see.

According to the present embodiment, the information distributed in various places is sorted at high speed, the sorted information is stored in the diagnostic memory storage buffer 42, and is displayed on the display device 8 in a time chart manner. It is possible to analyze and take countermeasures against abnormal phenomena using only the PCs 1 without newly providing on the equipment side.

In the embodiment shown in FIG. 1, the timing for storing in the diagnostic memory storage buffer 42 is set to the sequence program start timer 30.
It depends on the setting of 0, but it is caused by factors outside PCs1 such as external contacts, and ON / OFF of internal relays inside PCs1.
Can be started, and the trace information can be optimized.

Further, if the diagnostic memory storage buffer 42 shown in FIG. 1 is configured by a shift register as shown in FIG. 9, the address counter 350 becomes unnecessary and the programming device 7 is
When the diagnostic memory storage buffer 42 is referred to after the end of tracing, the latest information is always on the left end and the old information is on the right end. Therefore, it is possible to display the same on the display device 8 as a time chart.

According to this embodiment, the diagnostic recording start button 27
Since the start of diagnostic recording can be set, it can be stored intentionally instead of indiscriminately, and memory can be saved.

In addition, from the diagnostic memory 41 to the diagnostic memory storage buffer 42
It is possible to control the start / stop of copying to the disk at any time, and it is possible to perform detailed abnormality diagnosis.

Furthermore, from the diagnostic memory 41 to the diagnostic memory storage buffer 4
Since the copy interval to 2 is set to an integral multiple of the sequence cycle, it is possible to perform appropriate copy corresponding to the sequence cycle without waste.

〔The invention's effect〕

According to the present invention, at the time of abnormality diagnosis, before and after the occurrence of an abnormality, the control state can be grasped without waste within an arbitrarily set sequence cycle period, the memory in the programmable controller can be saved, and the purpose of the user can be improved. Correspondingly, it is possible to efficiently collect information on the abnormal state of the sequencer.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of an implementation circuit according to the present invention, FIG. 2 is a configuration diagram of a general programmable controller, FIG. 3 is a diagram showing an example of a sequence control target system having a tank,
FIG. 4 is a diagram showing an example of a relay ladder program, FIG. 5 is a diagram showing a state in which random ON / OFF information of the PI / O image memory is aligned at high speed, and FIG. 6 is a buffer for storing diagnostic memory when an abnormality occurs. FIG. 7 is a diagram showing a state in which diagnostic memory data is stored, FIG. 7 is a diagram in which a programming device and a display device are connected to a programmable controller, and FIG.
FIG. 9 is a diagram showing a display example of the contents recorded in the diagnostic memory, and FIG. 9 is a diagram showing a modified embodiment of the present invention. 1 ... PCs, 2 ... Field equipment, 15 ... PI / O image memory, 41 ... Diagnostic memory, 42 ... Diagnostic memory storage buffer, 300 ... Sequence program start cycle timer, 310 ... Copy start flip-flop, Three
34 ... Diagnostic memory copy stop cycle setting register,
335 ... Copy number counter after abnormal occurrence, 336 ...
Comparator, 340 ... Diagnostic memory copy timing counter setting register, 341 ... Diagnostic memory copy timing counter, 342 ... Comparator, 350 ... Diagnostic memory storing buffer address counter, 351 ... Buffer size setting register, 352 ... Comparator.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Manabu Araoka 5-2-1 Omika-cho, Hitachi City, Ibaraki Hitachi Ltd. Omika Plant, Ltd. (72) Inventor Koichi Ogino 2 Takara-cho, Kanagawa-ku, Yokohama, Kanagawa Address Nissan Motor Co., Ltd. (72) Inventor Katsuyuki Onodera 2 Takara-cho, Kanagawa-ku, Yokohama, Kanagawa Nissan Motor Co., Ltd. (56) Reference JP 56-63612 (JP, A) Japanese Patent Application No. 54-95785 (Actual No. Sho 56-16202) Micro film filming the contents of the specification and drawings attached to the application (Published by the Japan Patent Office on February 12, 1981)

Claims (1)

[Claims] 1. An abnormality diagnosing device for a sequencer for periodically controlling a relay ladder program, comprising: a first memory for storing a state of an input process input / output device; and an irregular distribution on the first memory. A second memory for aligning and storing information, a third memory for storing information written at a predetermined timing from the second memory, and a second memory for storing the third memory. The control circuit includes a control circuit for controlling the timing of writing and the stop of writing, and a display device which is detachably connected to the sequencer by a communication line and displays based on the information stored in the third memory. Is a switch for instructing to start writing from the second memory to the third memory, and the writing interval is variable at an interval which is an integral multiple of a sequence cycle. A write interval setting circuit for setting, a write stop time setting circuit for variably setting a write stop timing from the second memory to the third memory, and an address control for controlling a write address of the third memory An abnormality diagnosis device for a sequencer having a circuit.