JPH08212145A - Information processor, method and device for diagnosing memory - Google Patents

Abstract

PURPOSE: To diagnose a read/write enable memory at high speed concerning the information processor, method and device for diagnosing memory with which the fault of the memory is diagnosed. CONSTITUTION: This device is composed of a processor 11 for accessing a memory 12 and recognizing the fault of the memory 12, register 15 for previously holding test data to be written in all the areas of the memory 12 by the processor 11, comparator 16 for comparing whether the test data read out of the memory 12 by the processor 11 are matched with the test data previously held in the register 15 or not, and latch circuit 17 for latching the compared result of the comparator 16 and supplying it to the processor 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, a memory diagnosing method and a memory diagnosing apparatus, and more particularly to an information processing apparatus, a memory diagnosing method and a memory diagnosing apparatus for diagnosing a failure of a readable / writable memory.

In recent years, in information processing devices and the like, accurate processing cannot be performed if information is processed while the memory is defective. Therefore, when the power is turned on, the defective memory is detected and the memory is replaced. Some have an initial memory diagnosis function. However, as the capacity of the memory increases, it takes more time to diagnose a defective element of the memory.

Therefore, there is a demand for faster memory diagnosis.

[0004]

2. Description of the Related Art FIG. 9 shows a block diagram of a conventional example.
The conventional information processing device 40 includes a processor 41 and a processor 41 that process information according to a preset program.
The memory 42 stores data to be processed by the processor 41, and the display device 43 for displaying the processing result of the processor 41. In the initial state such as when the power is turned on, the failure of the memory 42 is diagnosed by controlling the processor 41 by a program. I was doing it.

FIG. 10 shows a flowchart of an initial diagnosis of a conventional memory. If there is a memory diagnostic command to the processor 41 (step S4 _-1), write test data to temporarily access the first address of the memory 42, read out again (step S4 _-2, S4 _-4).

The processor 41 compares the read data with the test data written in the memory 42 to determine whether the two data match or not. If they do not match, an error is displayed on the display device 43 and if they match. For example, memory 42
Write test data to the next address, to determine the match or mismatch between data read from the test data memory 42 is written is read again, detects an error (step S4 _-5 ~S4 _-9).

[0007] Conventionally, more than by the processor 41, has been performed to extract error by repeating the steps S4 _-3 ~S4 _-9.

[0008]

However, in the conventional memory diagnostic method, the processor connected to the memory writes and reads data to and from the memory by the program, and the data at the time of writing and the data at the time of reading are written. Since it was judged that there was an error if the data were different from each other, it took time to judge the error for one address, and especially when the memory capacity became large, it took a huge amount of time to diagnose the entire memory. There was a point.

Further, in the conventional memory diagnosis method, since the error determination is made only by whether or not the data is different, it is not possible to detect the access time failure, the retention failure, and the like. The present invention has been made in view of the above points, and an object of the present invention is to provide an information processing apparatus, a memory diagnostic method, and a memory diagnostic apparatus that can perform failure diagnosis of a memory at high speed.

[0010]

FIG. 1 shows the principle of the present invention. The memory access means 1 stores the same test data in the entire area of the memory and reads the test data from the memory.

The test data holding means 2 holds the test data. The comparison means 3 compares the test data read from the memory with the test data held in the test data holding means, and generates a failure determination signal indicating a failure of the memory when they do not match.

According to a second aspect of the present invention, the test data holding means and the comparison means are constituted by dedicated hardware. According to a third aspect of the present invention, a memory access control means for controlling access to the memory writes the same test data in the entire area of the memory, and the test data written in the entire area of the memory is held in the test data holding means. The data holding step, the test data written in the memory in the data writing step, and the test data held in the test data holding means in the data holding step are read out, and the coincidence and non-coincidence of the data are compared. A comparison step of comparing by the comparison means and designating a non-matching portion of the test data.

According to a fourth aspect of the present invention, there is provided a waiting process for waiting a predetermined time between the data writing process and the comparing process. According to a fifth aspect of the present invention, there is provided a memory diagnosing method for diagnosing a defect of a memory that outputs a data confirmation signal when output data is confirmed, the access process of accessing the memory, and the data confirmation signal being detected to detect the data. There is a definite detection process for detecting definite / indefinite of data when a definite signal is detected, and a delay control process for delaying the data definite signal when the detection result in the definite detection process is indefinite. I will do it.

According to a sixth aspect of the present invention, there is provided access means for accessing a memory which outputs a data confirmation signal after the output data is confirmed, data detecting means for detecting a state of data when the data confirmation signal is input, and It has a delay circuit for delaying the data confirmation signal and a delay time changing means for changing the delay time of the delay circuit.

[0015]

According to the first aspect of the present invention, the same test data is written in the entire area of the memory by the memory access means, the written test data is sequentially read from the memory, and is held in the test data holding means by the comparing means. The failure diagnosis of the memory can be performed only by comparing with the test data, and the access to the memory and the failure diagnosis can be performed independently, so that the diagnosis can be performed at high speed.

According to the second aspect, by structuring the test data holding means and the comparing means by dedicated hardware, failure diagnosis can be independently performed by the dedicated hardware, and the control of the program can be simplified. It enables diagnosis. According to claim 3, after writing the test data in the entire area of the memory and the test data holding means, the test data written in the test data holding means is supplied to the comparing means, and the comparing means sequentially reads the data from the memory. By the comparison means, the comparison means compares the test data of the test data holding means with the test data read from the memory, and by detecting the inconsistency, the data can be compared at once, so that the memory diagnosis can be executed at high speed. .

According to the present invention, by providing a waiting process between the data writing process and the comparing process, it is possible to detect the state of the memory after a certain time has elapsed since the data was stored in the memory, and the device failure. Besides, it becomes possible to diagnose defective refresh. According to the present invention, by repeating the access process, the confirmation detection process, and the delay control process until the data is confirmed and executing the data confirmation defect, the data confirmation delay time can be detected. Etc. can be done easily.

According to the sixth aspect, the data confirmation signal is sequentially delayed until the time when the data can be confirmed, whereby the defect of the data confirmation time and the defect time can be detected.

[0019]

1 is a block diagram of a first embodiment of the present invention. In this embodiment, an initial diagnosis method of a memory built in the information processing device will be described. The information processing apparatus 10 according to the present embodiment includes a processor 11 that processes information according to a preset program, a memory 12 that stores data processed by the processor 11, a display device 13 that displays a processing result of the processor 11, and a memory. It is composed of a failure diagnosis hardware unit 14 for diagnosing 12 failures.

The failure diagnosis hardware section 14 compares the data stored in the register 15 and the memory 12 for holding the test data with the test data held in the register 15, and when they match, the low level, and when they do not match, the high level. It is composed of a comparator 16 that outputs a level signal and a latch circuit 17 that latches the signal from the comparator 16.

The register 15 has the same value as the test data in the unit of long bytes stored in the addresses Adr1 to Adrn of the memory 12, for example, "FFAA550" in hexadecimal.
The test data "0" is held. Fig. 3 shows an operation flowchart of the first embodiment of the present invention.
In the memory diagnostic command is generated internally in accordance with the power-on (step S1 _-1), first, long-byte test data set in advance by accessing the memory 12,
For example, in hexadecimal notation, "FFAA5500" is written in each address Adr1 to n of the memory 12 and the test data "FFA550" stored in the memory 12 in the register.
0 writes FFAA5500 "" test data of the same value "(step S1 _-2, S1 _-3).

Next, the processor 11 supplies the test data held in the register 15 to the comparator 16 so that the address for accessing the memory 12 is the first address Adr1.
Is set, the memory 12 is accessed, the data is read from the memory 12, and the data is supplied to the comparator 16 (steps S1 _-4 , S1 _-5 , S1 _-6 ).

The comparator 16 compares the test data D1 supplied from the register 15 with the data D2 stored at the address Adr1 supplied from the memory 12, and when the data D1 and the data D2 match, the output Q is at a low level. When the data D1 and the data D2 do not match, the output Q is set to the high level. The output Q of the comparator 16 is supplied to the latch circuit 17.

The address Adr1 of the data read from the memory 12 is supplied to the latch circuit 17, the output Q of the comparator 16 is latched, and it is supplied to the processor 11 as an error determination signal of the corresponding address Adr1. If the data D1 and the data D2 match and there is no failure or defect in the accessed address of the memory 12, the processor 1
When a low-level error determination signal is supplied from the latch circuit 17 to 1 and the data D1 and the data D2 do not match and the accessed address of the memory 12 has a failure / defective, the processor 11 receives the latch circuit 17 A higher level error discrimination signal is supplied.

When the error determination signal from the latch circuit 17 becomes high level, the processor 11 determines that the currently accessed address of the memory 12 has a defect, and the display device 13 has a defect at a predetermined address of the memory 12. A message to that effect is displayed and the processing is stopped (steps _S1-7 , S).
_1-8 ).

Further, if the processor 11 is no failure in the step S1 _-7, then the accessed address is equal last address in Adrn to determine whether the last address Adr, there will be no defect in the memory 12 Therefore, the following processing operation is performed and the accessed address is the final address A.
Otherwise dr, returns the address Adrn accessing the increment (+1) Step S1 _-6 (step S
1 _-9 , S1 _-10 ).

The above steps S1 _-6 processor 11 by repeating the ～S1 _-10 is if there is a defect in the memory 12, recognizes the failure, you can stop the following operations, if there is no failure, proceeds to the next operation It will be. According to the present embodiment, operations such as data comparison and element failure determination are unnecessary in the processor 11 until an element failure is found, so that the data processing time in the processor 11 can be shortened and the failure can be performed at high speed. Can be judged.

FIG. 4 shows a block diagram of the second embodiment of the present invention. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted. This embodiment differs from the first embodiment in the control operation of the processor 21, and the processor 21 reads the data written in the memory 11 after a certain time has elapsed after writing the data in the memory 11 and detects the error. It is possible to diagnose a defective refresh circuit such as a DRAM.

FIG. 5 shows an operation flowchart of the second embodiment of the present invention. In the processor 21, when a memory diagnosis command is internally generated in response to power-on or the like (step S2
_-1 ), first, accessing the memory 12 and setting preset long-byte test data, for example, in hexadecimal display,
“FFAA5500” is set to each address Adr1 of the memory 12.
To n, and the test data “FFAA5500” having the same value as the test data “FFA5500” stored in the memory 12 is written in the register (step S
2 _-2 , S2 _-3 ).

Next, the processor 21 puts the diagnostic processing operation of the memory 12 in a standby state for a predetermined time corresponding to the refresh time of the memory 12, for example, for several seconds, and the processor 2
Other processing such as initialization of other circuits (not shown) such as an input / output interface connected to 1 is performed (step S
2 _-4 ).

After the elapse of a predetermined time, the processor 21 supplies the test data held in the register 15 to the comparator 16, sets the address for accessing the memory 12 at the first address Adr1, and accesses the memory 12,
The data is read from the memory 12 and supplied to the comparator 16 (steps _S2-5 , _S2-6 , _S2-7 ).

The comparator 16 compares the test data D1 supplied from the register 15 with the data D2 stored at the address Adr1 supplied from the memory 12, and when the data D1 and the data D2 match, the output Q is at a low level. When the data D1 and the data D2 do not match, the output Q is set to the high level. The output Q of the comparator 16 is supplied to the latch circuit 17.

The address Adr1 of the data read from the memory 12 is supplied to the latch circuit 17, the output Q of the comparator 16 is latched, and it is supplied to the processor 21 as an error determination signal of the corresponding address Adr1. If the data D1 and the data D2 match and the accessed address of the memory 12 has no failure or defect, the processor 2
When a low-level error determination signal is supplied from the latch circuit 17 to 1 and the data D1 and the data D2 do not match and the accessed address of the memory 12 has a failure / defective, the processor 21 receives the latch circuit 17 A higher level error discrimination signal is supplied.

When the error determination signal from the latch circuit 17 becomes high level, the processor 21 determines that the currently accessed address of the memory 12 is defective, and the display device 13 has a defect at a predetermined address of the memory 12. A message to that effect is displayed and the processing is stopped (steps _S2-8 , S).
_2-9 ).

Further, if the processor 21 has no failure in step S2 _-8, then the accessed address is equal last address in Adrn to determine whether the last address Adr, there will be no defect in the memory 12 Therefore, the following processing operation is performed and the accessed address is the final address A.
Otherwise dr, returns the address Adrn accessing the increment (+1) Step S2 _-7 (step S2
_-10 , S2 _-11 ).

[0036] If there is failure in the processor 21 by repeating the above steps S1 _-7 ~S1 _-11, recognizes the failure, can stop the following operations, if there is no failure, thus moving to the next operation . According to the present embodiment, the data is read from the memory 12 after a lapse of a predetermined time after writing the data in the memory 12, and whether the data matches or does not match the test data is detected, and the defect of the memory 12 is recognized. If the memory 12 is a static RAM, the data is deformed after a lapse of a predetermined time, so that it can be detected that the element is defective. If the memory 12 is a dynamic RAM, the element is similarly defective and the refresh circuit You can guess the breakdown.

FIG. 6 shows a block diagram of a third embodiment of the present invention. The information processing apparatus 30 of this embodiment includes a processor 31 that processes information according to a preset program, and a memory 3 that stores data processed by the processor 31.
2. A display device 33 for displaying the processing result of the data processed by the processor 31 and a memory access delay circuit 34 for measuring the delay time until the data is determined when the memory 12 is accessed.

The memory access delay circuit 34 delays the data confirmation signal by the delay circuit section 35 and the delay time of the data confirmation signal supplied from the delay circuit 35 by the processor 3.
The switch unit 36 that switches in accordance with the switching control signal from 1
It is composed of FIG. 7 shows an operation flowchart of the third embodiment of the present invention.

[0039] When the memory diagnostic command is generated internally in response to the processor 31 power-on or the like (step S3 _-1),
First, a switching control signal is supplied to the switch unit 36 of the memory access delay circuit 34, the switch unit 36 is controlled so that the delay time T of the delay circuit unit 34 becomes "0", and the first address Adr1 of the memory 32 is accessed. (step S3 _-2, S3 _-3).

Next, in the processor 31, the data and the data confirmation signal (for example, Motorola 3, DT in the memory) supplied from the memory 32 when the memory 32 is accessed.
By detecting ACK), the processor 31 detects whether or not the data can be confirmed (step _S3-4 ).

FIG. 8 shows an operation waveform diagram for explaining the confirmation of data. When accessing the memory 32, the processor 31 sends a -RAS (inverted ROW ADDRESS STROBE) signal as shown in FIGS.
CAS (Reverse COLUMM ADDRESS STRO
BE) signal is supplied to the memory 32, which is shown in FIG.
As shown in (C), the data is supplied to the processor 31 when the -RAS signal and the -CAS signal are simultaneously supplied.

The memory 32 outputs -DT as shown in FIGS. 8D and 8B, and -DT for determining the data output in synchronization with the -CLK (inverted clock) signal.
An ACK (inverted DTACK) signal is output. The processor 31 determines the data when the -DTACK signal from the memory 32 falls.

If the -DTACK signal falls at the time when the data from the memory 32 is indeterminate, the processor 31 cannot determine the data. That is, if the timing of supplying the data from the memory 32 and the timing of the -DTACK signal are deviated, the processor 32 cannot determine the data, and such a memory is defective.

Returning to FIG. 7, the description will be continued. Processor 3
1 If finalized data in step S3 _-4, memory 3
There is no defect in 2 and the memory diagnostic operation is terminated,
Move on to the next operation. If the data cannot be confirmed, the processor 31 controls the switch unit 36 to control the delay circuit unit 3.
The delay time of 5 is set to T = t ₀ , and the memory 32 is accessed (steps S3 _-5 , S3 _-6 , S3 _-7 ).

Here, the processor 31 detects whether or not the data is fixed (step _S3-8 ). Here, when the data is fixed, the display device 3 displays a display indicating that the data is fixed by delaying the -DTACK signal by the time T = t _0.
Step 3 (step _S3-9 ).

[0046] The processor 31 may be able finalized data in step S3 _-8, t ₀ greater than 2t ₀ the delay time T of the delay circuit section 35 controls the switch section 36
Then, the memory is accessed and the presence or absence of data confirmation is detected again (step _S3-10 ).

[0047] repeated until the step S3 _-6 to S3 _-10 the maximum delay time T = nt of the delay circuit 35 or, -
Request data determinable delay time DTACK signal (step S3 _-11). Further, when the data is not confirmed even when the maximum delay time T = nt ₀ of the delay circuit unit 35 is reached, the processor 31 displays on the display device 33 that the delay time is excessive (step _S3-12 ).

As described above, according to the present embodiment, it is possible to check the access time, and by knowing the access time, it is possible to accurately set the delay time of the access time at the time of designing the memory 32 and to obtain accurate numerical data for design mistakes. And contribute to speeding up the design.

[0049]

As described above, according to claim 1 of the present invention, the same test data is written in the entire area of the memory by the memory access means, the written test data is sequentially read from the memory, and the test data is written by the comparison means. The failure / diagnosis of the memory can be performed only by comparing it with the test data held in the holding means, and the access to the memory and the failure diagnosis can be performed independently, so that the diagnosis can be performed at high speed.

According to the second aspect, by structuring the test data holding means and the comparing means by the dedicated hardware, the failure can be diagnosed independently by the dedicated hardware, and the program control can be simplified. It enables diagnosis. According to claim 3, after writing the test data in the entire memory and the test data holding means, the test data written in the test data holding means is supplied to the comparing means, and the comparing means sequentially reads the data from the memory. The comparison means compares the test data in the test data holding means with the test data read from the memory, and by detecting the inconsistency, the data can be compared all at once, so that the memory diagnosis can be executed at high speed. With the features of.

According to the fourth aspect, by providing a waiting process between the data writing process and the comparing process, it is possible to detect the state of the memory after a certain period of time has elapsed since the data was stored in the memory, and the device failure was detected. It also has other features such as the ability to diagnose defective refresh.

According to the fifth aspect of the present invention, since the data confirmation failure can be detected and the data confirmation delay time can be detected by repeating and executing the access process, the confirmation detection process, and the delay control process until the data is confirmed, the memory can be detected. It has features such as easy adjustment of the circuit.

According to the sixth aspect of the present invention, by delaying the data decision signal sequentially until the time when the data can be decided, the defect of the data decision time and the defective time can be detected. It has features such as easy diagnosis of circuit design mistakes.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is an operation flowchart of the first embodiment of the present invention.

FIG. 4 is a block diagram of a second embodiment of the present invention.

FIG. 5 is an operation flowchart of the second embodiment of the present invention.

FIG. 6 is a block diagram of a third embodiment of the present invention.

FIG. 7 is an operation flowchart of the third embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the third embodiment of the present invention.

FIG. 9 is a block diagram of a conventional example.

FIG. 10 is an operation flowchart of a conventional example.

[Explanation of symbols]

 1 Memory 2 Memory Access Means 3 Test Data Holding Means 4 Comparing Means 11 Processor 12 Memory 13 Display Device 14 Fault Diagnosis Hardware Section 15 Registers 16 Comparators 17 Latch Circuits

Claims (6)

[Claims] 1. An information processing device having a function of diagnosing a failure of a mounted memory, wherein the same test data is stored in the entire area of the memory and the test data is read from the memory, and the memory access means stores the test data in the memory. Comparing the test data read from the memory with the test data held in the test data holding means,
An information processing apparatus, comprising: a comparison unit that generates a failure determination signal indicating a failure of the memory when they do not match. 2. The information processing apparatus according to claim 1, wherein the test data holding unit and the comparison unit are configured by dedicated hardware. 3. A data writing process of writing the same test data in the entire area of the memory by a memory access control means for controlling access to the memory, and holding the test data written in the entire area of the memory in a test data holding means. In the data holding step, the test data written in the memory in the data writing step and the test data held in the test data holding means in the data holding step are read out, and the data match / mismatch is compared. Compare by comparison means,
And a comparison step of indicating a non-matching portion of the test data. 4. The memory diagnostic method according to claim 3, further comprising a waiting process waiting for a predetermined time between the data writing process and the comparing process. 5. A memory diagnostic method for diagnosing a defect in a memory that outputs a data confirmation signal when output data is confirmed, the method comprising: accessing the memory; detecting the data confirmation signal; There is a definite detection step of detecting definite / indefinite of data when the definite signal is detected, and a delay control step of delaying the data definite signal when the detection result in the definite detection step is indefinite. A memory diagnostic method characterized by the above. 6. An access unit for accessing a memory which outputs a data confirmation signal after the output data is confirmed, a data detection unit for detecting a state of data when the data confirmation signal is input, and the data confirmation signal. And a delay time varying means for varying the delay time of the delay circuit.