CN116955240B - Delay calibration system and method for PHY circuit in DDR controller - Google Patents

Delay calibration system and method for PHY circuit in DDR controller Download PDF

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Publication number
CN116955240B
CN116955240B CN202311193566.6A CN202311193566A CN116955240B CN 116955240 B CN116955240 B CN 116955240B CN 202311193566 A CN202311193566 A CN 202311193566A CN 116955240 B CN116955240 B CN 116955240B
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calibration
refresh
delay value
ddr
time
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CN116955240A (en
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孙浩涛
王艳敏
贾弘翊
韦嶔
张红荣
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XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
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XI'AN INTELLIGENCE SILICON TECHNOLOGY Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a delay calibration system and a delay calibration method for a PHY circuit in a DDR (double data rate) controller, wherein the system comprises the DDR controller, a PHY module and DDR particles, wherein the DDR controller is used for initializing parameters of the DDR particles, sending a refresh command to the DDR particles when reaching preset refresh time each time, executing calibration operation to path delay values of the PHY circuit when reaching the preset refresh time each time and updating the path delay values after the calibration operation is completed; the PHY module is used for performing data read-write operation on DDR particles under the control of the DDR controller and storing a current path delay value and a current calibration state; the DDR particles are used for executing data read-write operation by using the calibrated path delay value, receiving refresh commands sent by the DDR controller and executing refresh operation. The delay calibration system does not need user participation, does not influence the DDR normal read-write efficiency, and realizes dynamic calibration of the PHY circuit delay.

Description

Delay calibration system and method for PHY circuit in DDR controller
Technical Field
The invention belongs to the technical field of circuit calibration, and particularly relates to a delay calibration system and method of a PHY circuit in a DDR controller.
Background
System-on-a-Chip (SOC Chip for short) is increasingly used in various fields, such as servers, desktop computers, mobile terminals, and the like, and thus, the performance and power consumption requirements of the SOC Chip are also increasingly high. In many SOC chips, a double rate synchronous dynamic random access memory (DDR SDRAM, double Data Rate Synchronous Dynamic Random Access Memory) controller (commonly referred to simply as a DDR controller) is typically used to cache portions of the data.
The DDR PHY (Double Data Rate Physical Layer, DDR physical layer) is a bridge connecting DDR particles (double rate synchronous dynamic random memory particles) and the DDR controller, and is responsible for converting data sent by the DDR controller into signals conforming to DDR protocol and sending the signals to the DDR particles; conversely, it is also responsible for converting the data sent from the DRAM (Dynamic Random Access Memory ) into signals conforming to the DFI protocol and sending the signals to the memory controller.
When the DDR controller writes or reads DDR particles for a long time, the path delay of the DDR PHY circuit can correspondingly change due to the change of external environment (temperature, voltage and the like). The change of circuit delay has great influence on the accuracy of data receiving and transmitting of the DDR controller. Therefore, dynamically calibrating the delay in the DDR PHY circuit is important for the DDR controller to accurately transmit and receive data.
In the prior art, the DDR controller usually calibrates the DDR PHY circuit after receiving a user command, however, the normal read-write time of the bus is occupied by the user command calibration, the efficiency is affected, and the user needs to participate in a dynamic calibration flow, which is not friendly to the user.
On the other hand, the DDR controller can send a calibration command in idle time to realize delay calibration of the PHY circuit. However, when the DDR controller is used for automatically sending the calibration command at idle time, the user cannot be predicted at which time to initiate the read-write operation, and when the DDR controller is sent at the same time as the user command, the idle time calibration of the controller can cause response delay of the user command, so that the period of the read-write response of the user is increased.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a delay calibration system and method for PHY circuits in DDR controllers. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a delay calibration system of a PHY circuit in a DDR controller, which comprises the DDR controller, a PHY module and DDR particles, wherein,
the DDR controller is used for initializing parameters of the DDR particles, sending out a refresh command to the DDR particles when a preset refresh time is reached each time, executing calibration operation to a path delay value of the PHY circuit when the preset refresh time is reached each time, and updating the path delay value after the calibration operation is completed;
the PHY module is used for performing data read-write operation on the DDR particles under the control of the DDR controller, and storing a current path delay value and a current calibration state;
and the DDR particles are used for executing data read-write operation by using the calibrated path delay value, receiving a refresh command sent by the DDR controller and executing refresh operation.
In one embodiment of the invention, the DDR controller includes an initialization unit, a clock control unit, a refresh unit, and a refresh calibration state machine, wherein,
the initializing unit is used for initializing parameters of the DDR particles and setting refreshing time;
the clock control unit is used for detecting whether the current time is refresh start time or refresh end time according to the refresh time, sending a refresh start signal to the refresh unit and a calibration start signal to the refresh calibration state machine at the refresh start time, and sending a refresh end signal to the refresh unit and a calibration end signal to the refresh calibration state machine at the refresh end time;
the refreshing unit is used for sending a refreshing command to the DDR particles under the action of the refreshing start signal and ending sending the refreshing command under the action of the refreshing end signal;
the refresh calibration state machine is used for executing calibration operation on the path delay value of the read-write path of the PHY circuit under the action of the calibration start signal, and ending executing the calibration operation under the action of the calibration end signal.
In one embodiment of the invention, the PHY module includes a write path unit, a read path unit, a delay storage unit, and a calibration state storage unit, wherein,
the write path unit is used for enabling the DDR particles to write data under the control of the DDR controller at non-refreshing time;
the read path unit is used for sampling data read out from the DDR particles under the control of the DDR controller at non-refresh time;
the delay storage unit is used for acquiring and storing a path delay value calibrated by the refreshing calibration state machine;
the calibration state storage unit is used for storing the current calibration state after each refresh time is finished, and the calibration state refers to the step state of the calibration process when the current refresh time is finished.
In one embodiment of the present invention, the PHY module further includes a calibration data storage register for storing preset calibration data, the calibration data storage register being capable of performing a read operation using the calibration data during calibration of the path delay value and returning a result to the DDR controller to verify whether the calibrated path delay value is appropriate.
In one embodiment of the invention, the refresh calibration state machine comprises a calibration unit and a state detection unit, wherein,
the calibration unit is used for reading the calibration state stored at the end of the previous round of refresh time from the calibration state storage unit under the action of the calibration start signal and continuously executing the calibration operation, and ending the calibration operation when the calibration end signal is received;
the state detection unit is used for detecting whether the calibration state is completed when the calibration ending signal is received, and if the calibration is completed, the calibrated path delay value is sent to the delay storage unit for storage; and if the calibration is not finished, transmitting the current calibration state to the calibration state storage unit for storage, and keeping the path delay value stored in the delay storage unit unchanged.
In one embodiment of the invention, performing a calibration operation includes:
acquiring a path delay value of a read-write path of a current PHY circuit, reducing the path delay value according to a preset step, executing a read operation in the PHY circuit by using pre-stored calibration data, if the read operation is correct, continuing to reduce the path delay value and executing the read operation, and if the read operation is incorrect, acquiring the path delay value adjusted last time as a left boundary of an allowable delay value;
the path delay value is increased according to preset steps, read operation is executed in the PHY circuit by utilizing pre-stored calibration data, if the read operation is correct, the path delay value is continuously increased and the read operation is executed, and if the read operation is incorrect, the path delay value adjusted last time is obtained as the right boundary of the allowable delay value;
acquiring an intermediate value between the left boundary and the right boundary of the path delay value as the path delay value after the calibration;
and calibrating the path delay value on each read-write path in the PHY circuit in sequence to obtain the path delay value after the calibration of each read-write path.
Another aspect of the present invention provides a delay calibration method for a PHY circuit in a DDR controller, including:
s1: initializing parameters of DDR particles, and setting refreshing time;
s2: performing data read-write operation on the DDR particles;
s3: when the preset refreshing time is reached, a refreshing command is sent out to the DDR particles, and meanwhile, the calibration operation is carried out to the path delay value of the PHY circuit;
s4: and returning to continue to execute the read-write operation when the refresh time is over, and storing the current calibration state and/or the updated path delay value.
In one embodiment of the present invention, the delay calibration method of the PHY circuit in the DDR controller further includes:
calibration data is preset and stored, and the calibration data can execute a read operation in the PHY circuit in the path delay value calibration process so as to verify whether the adjusted path delay value is proper.
In one embodiment of the present invention, the S3 includes:
detecting whether the current time is refresh start time or refresh end time according to preset refresh time, sending a refresh start signal to a refresh unit and a calibration start signal to a refresh calibration state machine at the refresh start time, and sending a refresh end signal to the refresh unit and a calibration end signal to the refresh calibration state machine at the refresh end time;
sending a refresh command to the DDR particles under the action of the refresh start signal, and ending sending the refresh command under the action of the refresh end signal;
and executing calibration operation on the path delay value of the read-write path of the PHY circuit under the action of the calibration start signal, and ending executing the calibration operation under the action of the calibration end signal.
In one embodiment of the present invention, performing a calibration operation on a path delay value of a PHY circuit under the effect of the calibration start signal and ending performing the calibration operation under the effect of the calibration end signal includes:
under the action of the calibration start signal, reading the calibration state stored at the end of the previous round of refresh time and continuously executing the calibration operation;
and ending the calibration operation when the calibration ending signal is received, detecting whether the calibration process is finished, if so, obtaining and updating the calibrated path delay value, and if not, storing the current calibration state and keeping the path delay value unchanged.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention provides a delay calibration system and a delay calibration method for a PHY circuit in a DDR controller, wherein the dynamic calibration does not need user participation, does not influence the DDR normal read-write efficiency, and realizes the dynamic calibration of the delay of the PHY circuit.
2. The calibration data in the calibration data storage register of the invention is configurable, so that calibration can be conveniently performed by using data with different formats.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a delay calibration system for PHY circuits in a DDR controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a DDR controller according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a PHY module according to an embodiment of the present invention;
FIG. 4 is a flowchart of a delay calibration method for PHY circuits in a DDR controller according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a processing procedure of a delay calibration method of a PHY circuit in a DDR controller according to an embodiment of the present invention.
Detailed Description
In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the following is a detailed description of a delay calibration system and method of a PHY circuit in a DDR controller according to the present invention with reference to the accompanying drawings and the detailed description.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises the element.
Example 1
Referring to fig. 1, fig. 1 is a schematic block diagram of a delay calibration system of a PHY circuit in a DDR controller according to an embodiment of the present invention. The delay calibration system comprises a DDR controller 1, a PHY module 2 and DDR particles 3, wherein the DDR controller 1 is used for initializing parameters of the DDR particles 3, sending a refresh command to the DDR particles 3 through the PHY module 2 when a preset refresh time is reached each time, executing calibration operation to a path delay value of a PHY circuit when the preset refresh time is reached each time, and updating the path delay value after the calibration operation is completed; the PHY module 2 is used for performing data read-write operation on the DDR particles 3 under the control of the DDR controller 1, and storing a current path delay value and a current calibration state; the DDR granule 3 is configured to perform a data read/write operation using the calibrated path delay value, receive a refresh command issued by the DDR controller 1, and perform a refresh operation.
In this embodiment, DDR particle 3 must be refreshed at regular intervals (e.g., 64 ms) to ensure that the capacitance of the DDR particle memory cell remains at the correct level. Therefore, the DDR controller 1 is required to transmit a refresh command once within the refresh time interval; to improve refresh efficiency, DDR granule allows deferring multiple refresh commands, e.g., deferring 8 refresh commands, so DDR controller 1 can send 9 refresh commands at once after 9 refresh time intervals, so that DDR granule 3 completes 9 refresh commands at once to improve efficiency. Based on the mechanism, when the DDR controller continuously sends out 9 refresh commands, at this moment, the PHY module 2 has no data flow on the path of the read-write circuit, and in the refresh gap, the DDR controller 1 synchronously sends out calibration commands to the PHY circuit, thereby realizing the dynamic calibration of circuit delay.
It should be noted that, since the time used for calibration once is longer than the time used for refreshing once, that is, longer than the refresh time interval, the mechanism of calibration by using the refresh time is usually required to complete calibration once in many refresh cycles; the user cannot sense the calibration process completely in the refresh time period, and all the processes are completed by the DDR controller 1 and the PHY module 2.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a DDR controller according to an embodiment of the present invention. The DDR controller 1 of the present embodiment includes an initialization unit 11, a clock control unit 12, a refresh unit 13, and a refresh calibration state machine 14, where the initialization unit 11 is configured to perform parameter initialization on DDR particles 3 and set a refresh time; the clock control unit 12 is configured to detect in real time whether the current time is a refresh start time or a refresh end time according to the set refresh time, send a refresh start signal and a calibration start signal to the refresh unit 13 and the refresh calibration state machine 14 at the refresh start time, and send a refresh end signal and a calibration end signal to the refresh unit 13 and the refresh calibration state machine 14 at the refresh end time, respectively; the refresh unit 13 is configured to issue a refresh command to the DDR granule 3 under the action of a refresh start signal and end sending the refresh command under the action of a refresh end signal; the refresh calibration state machine 14 is configured to perform a calibration operation on a path delay value of a read-write path of the PHY circuit under the action of a calibration start signal, and to end the calibration operation under the action of a calibration end signal.
Further, referring to fig. 3, fig. 3 is a schematic structural diagram of a PHY module according to an embodiment of the present invention. The PHY module 2 of the present embodiment includes a write path unit 21, a read path unit 22, a delay storage unit 23, and a calibration state storage unit 24, wherein the write path unit 21 is configured to cause the DDR granule 3 to write data under the control of the DDR controller at a non-refresh time; the read path unit 22 is used for sampling data read out from the DDR particles under the control of the DDR controller at a non-refresh time; the delay storage unit 23 is used for acquiring and storing the path delay value calibrated by the refresh calibration state machine 14; the calibration state storage unit 24 is configured to store a current calibration state after each refresh time, where the calibration state refers to a step state of the calibration process performed at the end of the current refresh time.
Specifically, the DDR controller 1 internally includes the refresh calibration state machine 14, and when the refresh operation is performed, the refresh calibration state machine 14 starts the calibration procedure synchronously through the calibration control signal bus, and the result of the calibration (i.e., the calibrated path delay value) is finally retained in the delay storage unit 23 (e.g., the delay storage register), and the calibrated path delay value is used in the subsequent read/write process. Since the time for completing one calibration is longer than the time for completing one refresh, the calibration process usually needs a plurality of refresh times, and in one refresh time, the calibration process can only be executed for a part of the calibration process, for example, calibrating the path delay value of the data line in a part of the DDR granules, at this time, the calibration state storage unit 24 is used to store the calibration state that needs to be started every refresh time, that is, the step state of the calibration process performed at the end of the current refresh time, at the next refresh time interval, the refresh calibration state machine 14 invokes the stored calibration state from the calibration state storage unit 24, and continues the calibration from the current calibration state, and when in a certain refresh time interval, the calibration process is ended and the path delay value of each read-write path in the PHY circuit is obtained, at the end of the refresh time, all the path delay values are updated and stored in the delay storage unit 23, and the calibrated path delay value is used in the subsequent read-write process.
In this embodiment, the refresh calibration state machine 14 specifically includes a calibration unit and a state detection unit, where the calibration unit is configured to read, under the effect of a calibration start signal, a calibration state stored at the end of a previous refresh time from the calibration state storage unit and continue to perform a calibration operation, and end the calibration operation when a calibration end signal is received; the state detection unit is used for detecting whether the calibration state is completed when receiving the calibration end signal, and if the calibration is completed, the calibrated path delay value is sent to the delay storage unit 23 for storage; if the calibration is not completed, the current calibration state is sent to the calibration state storage unit 24 for storage, and the path delay value stored in the delay storage unit 23 remains unchanged.
In addition, the PHY module 2 further includes a calibration data storage register 25 for storing preset calibration data, where the calibration data storage register 25 can perform a read operation in the calibration data storage register 25 using the calibration data during the calibration of the path delay value, and return the result to the DDR controller to verify whether the calibrated path delay value is appropriate. Specifically, when the calibration operation is performed with the refresh time, the normal read-write operation cannot be performed, and thus the calibration data storage register 25 is also included in the PHY module 2, and is readable and writable to simulate the read-write behavior of DDR granules. The initial value of the calibration data store register 25 is set by the user.
In this embodiment, the specific procedure for performing the calibration operation includes:
(1) Under the action of a calibration start signal, the calibration unit of the refresh calibration state machine 14 acquires a path delay value of a current PHY circuit read-write path (i.e., a path delay value acquired in a last calibration process) from the delay storage unit 23, reduces the path delay value according to a preset step, performs a read operation in the PHY circuit by using calibration data stored in the calibration data storage register 25 in advance, continues to reduce the path delay value and performs the read operation if the read operation is correct, and acquires the path delay value adjusted last time as a left boundary of an allowable delay value if the read operation is incorrect, wherein the allowable delay value here represents an acceptable path delay value, and is generally a numerical range;
(2) Similarly, the path delay value of the current PHY circuit read-write path is obtained from the delay storage unit 23, the path delay value is increased according to a preset step, the calibration data stored in the calibration data storage register 25 in advance is utilized to perform a read operation in the PHY circuit, if the read operation is correct, the path delay value is continuously increased and the read operation is performed, and if the read operation is incorrect, the path delay value adjusted last time is obtained as the right boundary of the allowable delay value;
(3) After obtaining the left boundary and the right boundary of the path delay value, obtaining an intermediate value between the left boundary and the right boundary as the path delay value after the calibration;
(4) And calibrating the path delay value on each read-write path in the PHY circuit in sequence to obtain the path delay value after the calibration of each read-write path.
In other words, in the calibration process, the path delay value on each read-write path in the PHY circuit is adjusted, and the calibration data storage register is read once for one time, so as to find the best position of the delay, i.e. the best value of the path delay value. Taking DQ0 (first read/write path) as an example, assuming that the initial path delay value is 10, firstly performing a step-by-step subtraction on the initial path delay value to be 1, where the path delay value is 9, performing a read operation on the calibration data stored in the calibration data storage register 25 in the PHY circuit by using the path delay value 9, and feeding back the result to the DDR controller 1, if the read is correct, continuing the step-by-step subtraction to be 1, and if the read is incorrect, taking the path delay value obtained by the previous subtraction as the left boundary; and similarly, adding the initial path delay value to step 1 to find the right boundary of the path delay value, and finally taking the intermediate value of the left boundary and the right boundary as the optimal delay position.
The embodiment provides a delay calibration system of a PHY circuit in a DDR controller, which does not need user participation, does not influence the DDR normal read-write efficiency, and realizes dynamic calibration of the delay of the PHY circuit. In addition, the calibration data in the calibration data storage register is configurable, so that calibration can be conveniently performed by using different format data.
Example two
On the basis of the first embodiment, the present embodiment further provides a delay calibration method for a PHY circuit in a DDR controller, referring to fig. 4 and 5, where the delay calibration method includes:
s1: and initializing parameters of the DDR particles, and setting refreshing time.
S2: and performing data read-write operation on the DDR particles.
S3: and when the preset refresh time is reached, a refresh command is sent out to the DDR particles, and meanwhile, the calibration operation is carried out to the path delay value of the PHY circuit.
In this embodiment, S3 includes:
detecting whether the current time is refresh start time or refresh end time according to preset refresh time, sending refresh start signals to a refresh unit at the refresh start time, respectively sending refresh start signals and sending calibration start signals to the refresh unit and to a refresh calibration state machine, and respectively sending refresh end signals to the refresh unit and sending refresh end signals and sending calibration end signals to the refresh calibration state machine at the refresh end time;
sending a refresh command to DDR particles under the action of a refresh start signal and ending sending the refresh command under the action of a refresh end signal;
and executing the calibration operation on the path delay value of the read-write path of the PHY circuit under the action of the calibration start signal and ending executing the calibration operation under the action of the calibration end signal. Specifically, under the action of a calibration start signal, reading a calibration state stored at the end of a previous round of refresh time and starting to continue to execute a calibration operation; and ending the calibration operation when receiving the calibration ending signal, detecting whether the calibration process is finished, if so, obtaining and updating the calibrated path delay value, and if not, storing the current calibration state and keeping the path delay value unchanged.
S4: and returning to continue to execute the read-write operation when the refresh time is over, and storing the current calibration state and/or the updated path delay value.
Further, the delay calibration method further comprises:
calibration data is preset and stored, and the calibration data can execute a read operation in a PHY circuit in the path delay value calibration process and return a result to the DDR controller so as to verify whether the adjusted path delay value is proper.
In this embodiment, the specific procedure for performing the calibration operation includes:
(1) Under the action of a calibration start signal, acquiring a path delay value of the PHY circuit, reducing the path delay value according to a preset step, executing a read operation on the PHY circuit (for example, a calibration data storage register in a PHY module in the first embodiment) by using pre-stored calibration data, if the read operation is correct, continuing to reduce the path delay value and executing the read operation, and if the read operation is incorrect, acquiring the path delay value adjusted last time as a left boundary of an allowable delay value;
(2) The initial path delay value is increased according to preset steps, read operation is executed in the PHY circuit by utilizing pre-stored calibration data, if the read operation is correct, the path delay value is continuously increased and the read operation is executed, and if the read operation is incorrect, the last adjusted delay value is obtained as the right boundary of the allowable delay value;
(3) After obtaining the left boundary and the right boundary of the path delay value, obtaining an intermediate value between the left boundary and the right boundary as the path delay value after the calibration;
(4) And calibrating the path delay value on each read-write path in the PHY circuit in sequence to obtain the calibrated path delay value.
In the several embodiments provided in the present invention, it should be understood that the apparatus and method disclosed in the present invention may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed.
In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in hardware plus software functional modules.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (8)

1. A delay calibration system of PHY circuits in a DDR controller is characterized by comprising the DDR controller, a PHY module and DDR particles, wherein,
the DDR controller is used for initializing parameters of the DDR particles, sending out a refresh command to the DDR particles when a preset refresh time is reached each time, executing calibration operation to a path delay value of the PHY circuit when the preset refresh time is reached each time, and updating the path delay value after the calibration operation is completed;
the PHY module is used for performing data read-write operation on the DDR particles under the control of the DDR controller, and storing a current path delay value and a current calibration state; the DDR particles are used for executing data read-write operation by using the calibrated path delay value, receiving a refresh command sent by the DDR controller and executing refresh operation;
the DDR controller comprises an initialization unit, a clock control unit, a refresh unit and a refresh calibration state machine, wherein,
the initializing unit is used for initializing parameters of the DDR particles and setting refreshing time;
the clock control unit is used for detecting whether the current time is refresh start time or refresh end time according to the refresh time, sending a refresh start signal to the refresh unit and a calibration start signal to the refresh calibration state machine at the refresh start time, and sending a refresh end signal to the refresh unit and a calibration end signal to the refresh calibration state machine at the refresh end time;
the refreshing unit is used for sending a refreshing command to the DDR particles under the action of the refreshing start signal and ending sending the refreshing command under the action of the refreshing end signal;
the refresh calibration state machine is used for executing calibration operation on the path delay value of the read-write path of the PHY circuit under the action of the calibration start signal, and ending executing the calibration operation under the action of the calibration end signal.
2. The delay calibration system of PHY circuitry in a DDR controller of claim 1, wherein the PHY module comprises a write path unit, a read path unit, a delay storage unit, and a calibration state storage unit, wherein,
the write path unit is used for enabling the DDR particles to write data under the control of the DDR controller at non-refreshing time;
the read path unit is used for sampling data read out from the DDR particles under the control of the DDR controller at non-refresh time;
the delay storage unit is used for acquiring and storing a path delay value calibrated by the refreshing calibration state machine;
the calibration state storage unit is used for storing the current calibration state after each refresh time is finished, and the calibration state refers to the step state of the calibration process when the current refresh time is finished.
3. The delay calibration system of PHY circuitry in a DDR controller of claim 2, wherein the PHY module further comprises a calibration data store register to hold pre-set calibration data, the calibration data store register to enable read operations to be performed using the calibration data during calibration of path delay values and return results to the DDR controller to verify that the calibrated path delay values are appropriate.
4. A delay calibration system for PHY circuits in a DDR controller according to claim 3, wherein said refresh calibration state machine comprises a calibration unit and a state detection unit, wherein,
the calibration unit is used for reading the calibration state stored at the end of the previous round of refresh time from the calibration state storage unit under the action of the calibration start signal and continuously executing the calibration operation, and ending the calibration operation when the calibration end signal is received;
the state detection unit is used for detecting whether the calibration state is completed when the calibration ending signal is received, and if the calibration is completed, the calibrated path delay value is sent to the delay storage unit for storage; and if the calibration is not finished, transmitting the current calibration state to the calibration state storage unit for storage, and keeping the path delay value stored in the delay storage unit unchanged.
5. The delay calibration system of PHY circuitry in a DDR controller of claim 4, wherein performing the calibration operation comprises:
acquiring a path delay value of a read-write path of a current PHY circuit, reducing the path delay value according to a preset step, executing a read operation in the PHY circuit by using pre-stored calibration data, if the read operation is correct, continuing to reduce the path delay value and executing the read operation, and if the read operation is incorrect, acquiring the path delay value adjusted last time as a left boundary of an allowable delay value;
the path delay value is increased according to preset steps, read operation is executed in the PHY circuit by utilizing pre-stored calibration data, if the read operation is correct, the path delay value is continuously increased and the read operation is executed, and if the read operation is incorrect, the path delay value adjusted last time is obtained as the right boundary of the allowable delay value;
acquiring an intermediate value between the left boundary and the right boundary of the path delay value as the path delay value after the calibration;
and calibrating the path delay value on each read-write path in the PHY circuit in sequence to obtain the path delay value after the calibration of each read-write path.
6. A method for calibrating delay of a PHY circuit in a DDR controller, comprising:
s1: initializing parameters of DDR particles, and setting refreshing time;
s2: performing data read-write operation on the DDR particles;
s3: when the preset refreshing time is reached, a refreshing command is sent out to the DDR particles, and meanwhile, the calibration operation is carried out to the path delay value of the PHY circuit;
s4: returning to continue to perform read-write operation when the refresh time is over, saving the current calibration state and/or updated path delay value,
the step S3 comprises the following steps:
detecting whether the current time is refresh start time or refresh end time according to preset refresh time, sending a refresh start signal to a refresh unit and a calibration start signal to a refresh calibration state machine at the refresh start time, and sending a refresh end signal to the refresh unit and a calibration end signal to the refresh calibration state machine at the refresh end time;
sending a refresh command to the DDR particles under the action of the refresh start signal, and ending sending the refresh command under the action of the refresh end signal;
and executing calibration operation on the path delay value of the read-write path of the PHY circuit under the action of the calibration start signal, and ending executing the calibration operation under the action of the calibration end signal.
7. The method of delay calibration of PHY circuitry in a DDR controller of claim 6, further comprising:
calibration data is preset and stored, and the calibration data can execute a read operation in the PHY circuit in the path delay value calibration process so as to verify whether the adjusted path delay value is proper.
8. The delay calibration method of PHY circuitry in a DDR controller of claim 7, wherein performing a calibration operation on a path delay value of PHY circuitry under the action of the calibration start signal and ending performing a calibration operation under the action of the calibration end signal comprises:
under the action of the calibration start signal, reading the calibration state stored at the end of the previous round of refresh time and continuously executing the calibration operation;
and ending the calibration operation when the calibration ending signal is received, detecting whether the calibration process is finished, if so, obtaining and updating the calibrated path delay value, and if not, storing the current calibration state and keeping the path delay value unchanged.
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