CN115862707A - PSRAM phase calibration method and controller - Google Patents
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Abstract
The invention provides a PSRAM phase calibration method and a controller, wherein the controller comprises the following steps: the system comprises a system control module, an interface control module and a phase calibration module, wherein the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing a PSRAM protocol and a time sequence; the interface control module comprises a read delay chain and a write delay chain; the write delay chain is used for adjusting the delay relation between a write clock and other signals, and the read delay chain is used for adjusting the phase relation between a STROBE signal and DQ; the phase calibration module uses a burst read-write command, reads and compares specific data written into the PSRAM device, calculates and adjusts a read delay chain and a write delay chain of the interface control module according to the result, and completes phase calibration.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a PSRAM phase calibration method and a controller.
Background
Pseudo Static Random Access Memory (PSRAM) architecture is a device between Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Compared with DDR, the IO voltage of the PSRAM is 1.8V and is lower than 2.5V of DDR, and the driving capability of IO is slightly weak; compared with DDR2, the STROBE signal without difference of the PSRAM has no ODT function and insufficient signal integrity.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the material described in this section is not prior art to the claims in this application and is not admitted to be prior art by inclusion in this section.
Disclosure of Invention
In view of the above technical problems in the related art, the present invention provides a PSRAM controller, which includes: the system comprises a system control module, an interface control module and a phase calibration module, wherein the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing a PSRAM protocol and a time sequence;
the interface control module comprises a read delay chain and a write delay chain; the write delay chain is used for adjusting the delay relation between a write clock and other signals, and the read delay chain is used for adjusting the phase relation between a STROBE signal and DQ;
the phase calibration module uses a burst read-write command, reads and compares specific data written into the PSRAM device, calculates and adjusts a read delay chain and a write delay chain of the interface control module according to the result, and completes phase calibration.
Specifically, the read delay chain comprises a two-stage delay chain, the one-stage delay chain is formed by serially connecting standard units with balanced rising and falling edge delays and is finely adjusted through the output of a data selector, and the two-stage delay chain is formed by serially connecting a plurality of one-stage delay chains and is coarsely adjusted through the output of the data selector.
Specifically, the write delay chain is the same as a first-stage delay chain of the read delay chain.
Specifically, the phase calibration module includes: the device comprises a calibration state machine, a delay calculation module, a read-write detection module and a clock generation module; the calibration state machine controls a calibration process, which comprises an initial calibration process and a real-time calibration process; the read-write detection module sends specific burst write and read to the system control module and compares the read data to judge whether the read-write is correct or not; the delay calculating unit is used for adjusting the delay chain according to the calibration state and the result of the correctness of the read data; and the clock generation module is controlled according to the calibration state machine to realize burr-free frequency up-down on the input original clock.
Specifically, the clock generating module includes: an even frequency divider and a selector for eliminating glitch.
In a second aspect, another embodiment of the present invention provides a PSRAM phase calibration method, which includes the following steps:
s1, acquiring PSRAM starting, and performing initial reading calibration;
wherein the step S1 comprises: s10, configuring a write delay chain by adopting a register default value, and configuring the read delay chain of STROBE and DQ to 0; s11, reducing the frequency of a working clock; s12, writing a specific number into the PSRAM; s13, recovering the clock frequency; s14, reading a specific number from the PSRAM to obtain read-back data; s15, comparing the read data with a specific number; s16, if the value is correct, finding the minimum value of the read delay chain window, and executing the step S20; s17, otherwise, increasing the phase between STROBE and DQ by increasing a DQ read delay chain; s18, judging whether the maximum value of the read delay chain is reached; s19, if the maximum value of the delay chain is reached, the fact that the value which can not work can not be found even after one time of scanning is indicated, and error reporting and exiting are carried out; s20, reducing the frequency of a working clock; s21, writing the specific number into the PSRAM; s22, recovering the clock frequency; s23, reading a specific number from the PSRAM to obtain read-back data; s24, comparing the read data with a specific number, S25, if the data is wrong, finding the maximum value of a read delay chain window, and executing the step S28; s26, otherwise, increasing the phase between STROBE and DQ by increasing a DQ read delay chain; s27, judging whether the maximum value of the read delay chain is reached, and if so, finding the maximum value of a read delay chain window; s28, averaging the minimum value and the maximum value of the window to be used as a calibration value of the read delay chain;
s3, performing initial writing calibration;
wherein step S3 comprises: s31, configuring a clock write delay chain to be half of the length of the delay chain, and configuring a signal write delay chain to be 0; s32, writing the specific number into the PSRAM; specifically sending a write command to write the specific number into the PSRAM, wherein the specific write mode is the same as the mode in the step S1; s33, reading a specific number from the PSRAM to obtain read-back data; s34, comparing the read-back data with a certain number, S35, if the read-back data is correct, finding the minimum value of a write delay chain window, and executing S38; s36, if not, adding a signal writing delay chain, S37, judging whether the maximum value of the delay chain is reached, if so, exceeding the speed, and performing error reporting and exiting; s38, writing the specific number into the PSRAM; s39, reading a specific number from the PSRAM to obtain read-back data; s40, comparing the read data with a specific number, S41, if the data is wrong, finding the maximum value of a write delay chain window; s42, if the signal is correct, adding a signal writing delay chain; s43, judging whether the maximum value of the delay chain is reached, and if so, finding the maximum value of a read delay chain window; s44, averaging the minimum value and the maximum value of the window to be used as a calibration value of the write delay chain;
and S5, respectively applying the calibration value of the reading delay chain and the calibration value of the writing delay chain to the reading delay chain and the writing delay chain.
Specifically, the method further comprises: s3', real-time reading and calibrating, specifically: s31', reducing the frequency of a working clock; s32', writing a specific number into the PSRAM; s33', recovering the clock frequency; s34', reading a specific number from the PSRAM to obtain read-back data; s35 'comparing the read data with a specific number, S36', if correct, keeping the current value of the delay chain, and completing calibration; s37', if the error occurs, reducing a DQ read delay chain; s38', judging whether the DQ read delay chain is smaller than a set range, and if so, restoring the original value of the DQ read delay chain; and performing steps S31'-34'; s391', comparing the read data with a specific number, S392', if correct, keeping the current value of the delay chain, and finishing calibration; s393', if wrong, adding a DQ read delay chain; s394', judge whether DQ read delay chain is larger than the set range, S395', if yes, calibration fails.
Specifically, the method further comprises: s4', real-time writing calibration, which specifically comprises the following steps: s41', writing a specific number into a PSRAM; specifically sending a write command to write a specific number into the PSRAM; s42', reading a specific number from the PSRAM to obtain read-back data; s43', comparing the read data with a specific number, S44', if correct, keeping the current value of the delay chain, and completing calibration; s45', if not, reducing the signal writing delay chain, S46', judging whether the signal writing delay chain is smaller than a set range, S47', if so, recovering the original value of the signal writing delay chain, and executing the steps S41' -S43'; s48', if the current value is correct, the delay chain keeps the current value, and the calibration is completed; s49', if not, adding a signal writing delay chain, S491', judging whether the signal writing delay chain is larger than a set range, and if so, the calibration fails.
Specifically, the DQ read delay chain is decreased, the DQ read delay chain is increased, the DQ write delay chain is decreased, and the DQ write delay chain is increased by 1.
The PSRAM phase calibration method and the controller improve the accuracy of a delay chain and the highest communication speed with PSRAM equipment through calibration flow control and a calibration algorithm. Meanwhile, the invention provides real-time calibration for compensating equipment delay drift and delay chain drift caused by voltage and temperature in the working process of the chip.
1) The initial read calibration and the write calibration are realized, and the read-write delay chain is ensured to work at the optimal phase;
2) The initial reading calibration adopts dichotomy acceleration, so that the application waiting time is reduced;
3) And the real-time fine adjustment calibration is carried out during real-time idle, the phase drift influence caused by voltage and temperature is compensated, and the stability is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a diagram of a PSRAM controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of STROBE and DQ phases in a read timing provided by an embodiment of the invention;
FIG. 3 is a schematic diagram of a read delay chain according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the PSRAM burst write clock and data phase provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of an overall PSRAM phase calibration process according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an initial read calibration provided by an embodiment of the present invention;
FIG. 7 is a schematic diagram of initial write calibration provided by an embodiment of the invention;
FIG. 8 is a schematic diagram of a real-time read calibration provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of a real-time write calibration provided by an embodiment of the invention;
FIG. 10 is a schematic diagram of a read/write detection module and a clock generation module according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a read/write state machine according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a glitch removal state control provided by an embodiment of the present invention;
FIG. 13 is a diagram illustrating a minimum dichotomy of an initial read calibration scan according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of initial read calibration scan maximum dichotomy provided by an embodiment of the invention;
fig. 15 is a schematic diagram of a calibration state machine according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present invention.
Example one
Referring to fig. 1, the present embodiment discloses a PSRAM controller, which includes a phase calibration module, a system control module, and an interface control module, wherein the interface control module includes a read delay chain and a write delay chain; the phase calibration module comprises a calibration state machine, a clock generation module, a delay calculation unit and a read-write detection module; the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing a PSRAM protocol and a time sequence; the write delay chain is used for adjusting the delay relation between a write clock and other signals, and the read delay chain is used for adjusting the phase relation between a STROBE signal and DQ; the phase calibration module uses a burst read-write command, reads and compares specific data after writing the data into the PSRAM device, calculates and adjusts the delay chain of the interface control module according to the result, and completes the phase calibration process.
The phase calibration module is matched with the system control module and the interface control module to complete phase calibration. The system control module in fig. 1 controls the state of the whole PSRAM controller, and supports functions of various PSRAM devices, such as a power-on initialization process, a reset mode, a sleep mode, and the like. The interface control module is mainly used for realizing PSRAM protocol and time sequence. The interface state machine receives PSRAM command, address, data and the like provided by the system control module and sends the PSRAM command, address, data and the like according to the time sequence required by the PSRAM equipment. The write delay chain is used to adjust the delay relationship between the write clock and other signals, and the read delay chain is used to adjust the phase relationship between the STROBE signal and the DQs.
The phase calibration module uses a burst read-write command, reads and compares specific data written into the PSRAM device, calculates and adjusts the delay chain of the interface control module according to the result, and completes the phase calibration process. And the burst read-write command and the burst read-write data of the phase calibration module are forwarded to the interface control module through the system control module, and the calculated delay result is sent to a delay chain in the interface control module. The phase calibration module is internally provided with four modules: the device comprises a calibration state machine, a delay calculation module, a read-write detection module and a clock generation module. The calibration state machine controls a calibration process, which comprises an initial calibration process and a real-time calibration process; the read-write detection module sends specific burst write and read to the system control module and compares the read data to judge whether the read-write is correct or not; a delay chain rapid calibration algorithm is realized in the delay calculation module, and the next adjustment direction is determined according to the calibration state and the reading and writing result; and the clock generation module is controlled according to the calibration state machine to realize burr-free frequency up-down on the input original clock.
Referring to FIG. 2, according to the protocol requirements of PSRAM, STROBE and DQ signals in read timing are in phase relationship. Although different PSRAM devices have slightly different timings for STROBE and DQ, the phase relationship between STROBE and DQ passing through board level traces and chip internal traces cannot be guaranteed, and it cannot be guaranteed that the STROBE has a sufficient sampling window for DQ sampling. Therefore, it is necessary to adjust the phase between the two using the read delay chain, and it is usually desirable to adjust both the STROBE and DQ to 90 degrees in order to ensure that the setup and hold margins are sufficient for both at high speed. In order for the PSRAM controller to sample the data correctly at high speed, a two-stage delay chain is designed in the read delay chain, as shown in fig. 3. The first-stage delay chain is formed by connecting standard units with balanced rising edge and falling edge delay in series, and the fine adjustment effect is achieved through the output of the data selector. The two-stage delay chain is formed by connecting a plurality of first-stage delay chains in series, and the coarse adjustment effect is achieved through the output of the data selector. As shown in fig. 4, the protocol for PSRAM requires that the clock and data in the burst write clock be 90 degrees in phase, and there is a sufficient sampling window for the data to be sampled by the clock signal after reaching the PSRAM device. Therefore, the first-stage chain in the write delay chain and the read delay chain adopts the same structure, and the calibration module ensures that the 90-degree phase is still kept when the clock and the data are sent to the IO of the chip through the fine tuning delay.
According to the time sequence of the read-write command and the characteristics of the read-write delay chain, the initial calibration and the real-time calibration are designed in the embodiment. The initial calibration ensures that the read-write delay chain is in the optimal configuration before normal functions are run, and the timing margin between the read-write clock and the sampling signal is the largest. The real-time calibration is used for fine tuning the delay chain to offset timing sequence changes caused by voltage and temperature fluctuations when the work is idle. Since the write timing phase is maintained at substantially 90 degrees, only fine tuning is required and the read phase needs to be adjusted from 0, so that the read calibration is performed first to ensure that the read calibration is performed normally and then the write calibration is performed. As shown in fig. 5, after the start-up, the initial read calibration is performed first, and then the initial write calibration is performed, and then the standby state is entered. The real-time calibration is an optional item, is suitable for the application that the PSRAM equipment is not operated at full load, and is informed to start the real-time calibration by the chip main system, and then the read calibration and the write calibration are carried out. In order to ensure that the read calibration can be correctly performed, the read calibration adopts a mode of reducing the frequency of a write clock to write data at a low speed, so that the correctness of the write data is ensured, and then the read operation is performed at the recovered original frequency. The detailed flow of each calibration is as follows:
as in FIG. 6, the write delay chain will be configured with register defaults first, and then the read delay chain of STROBE and DQ will be configured to 0. Then, the processes of reducing the clock frequency, writing data, recovering the clock frequency and reading data are carried out, and the processes are called as frequency reduction writing and recovery reading for short. Then comparing the read data, and if the comparison result is correct, finding out the minimum value of the read delay chain window; otherwise the phase between STROBE and DQ is increased by adding the DQ read delay chain. If the maximum value of the delay chain is reached, the scanning process cannot find a working value, and an error is reported for exiting. And after finding the minimum value of the read delay chain window, continuing the process of down-frequency writing and reading recovery. When the first read-write error is found or the delay chain reaches the maximum value, the maximum value of the window is found. Finally, the window minimum and maximum values are averaged and applied as a calibration value for the read delay chain.
As in fig. 7, the flow of the initial write calibration is similar to the initial read calibration. Because the read calibration is already completed, there is no need for a write-down recovery read process. The first step sets the write delay chain of the clock to half to configure the signal write delay chain to 0 in preparation for scanning the delay chain from 0 to the maximum. And after the minimum value and the maximum value of the delay chain window are sequentially found, the average value of the minimum value and the maximum value is used as the calibration value of the final data writing delay chain.
The real-time calibration is only fine-tuned, and whether a proper delay chain value exists in the delay chain within a certain range is searched for in the process of reducing and increasing the delay chain within a certain range. First, the scan attempts to find the correct delay for reading and writing in the decreasing direction. When the reading and writing can not be correctly performed even if the reading and writing is reduced to a certain value, the scanning direction is changed to the increasing direction for scanning. If the correct delay cannot be found even if a certain value is increased, the delay chain is failed due to external conditions, and an error exit needs to be reported. As shown in fig. 8, the real-time read calibration first performs a write-down-recovery read process. Then, comparing the data, if the comparison result is correct, finding out a proper delay value, and finishing calibration; if the comparison is wrong, the DQ read delay chain is reduced, and then the write-down recovery read process is performed. If the DQ read delay chain is smaller than the set range, the value of the DQ read delay chain before real-time calibration is restored, and then the process of frequency reduction, writing and restoring reading is carried out. Continuously comparing the read data, if the comparison result is correct, finding out a proper delay value, and finishing calibration; if the comparison is erroneous, the DQ read latency chain is increased and the write-down recovery read process is repeated. And finally, if the DQ read delay chain is larger than the set range, the calibration fails, otherwise, the value when the reading and writing are correct is applied to the delay chain.
As in fig. 9, the real-time write calibration first performs a write-read process. Then, the read data are compared, if the comparison result is correct, a proper delay value is found, and the calibration is completed; if the comparison is wrong, the signal writing delay chain is reduced, and then the writing and reading processes are carried out. If the signal writing delay chain is smaller than the set range, the value of the signal writing chain before real-time calibration is restored, and then the process of writing and reading is carried out. Continuously comparing the read data, if the comparison result is correct, finding a proper delay value, and finishing calibration; if the comparison is wrong, a signal writing delay chain is added, and the writing and reading process is repeated. And finally, if the signal writing delay chain is larger than the set range, the calibration fails, otherwise, the value when the reading and writing are correct is applied to the delay chain.
The four calibration processes are all processes of comparing write data and read data, and the processes are realized by the read-write detection module and the clock generation module together. As in fig. 10, there are four submodules inside: write data, read data, a database, and a read-write state machine. Wherein the state machine controls a clock selection signal of the clock generation module.
In the read-write detection module, the data writing module is responsible for generating a data writing command, an address, a length and a request, and transmitting the data writing command, the address, the length and the request to the interface control module through the system control module to generate a writing time sequence. The data of the write data module is retrieved from the database by the register arrangement, typically having a random number and a 01 data string. The 01 data string is a data sequence of 8 bits 0 in odd cycles and 8 bits 1 in even cycles, and the 01 data string is transmitted to enable each data bit in adjacent cycles of the PSRAM to be inverted. The data reading module is responsible for generating data reading commands, addresses, lengths and requests, and transmits the data reading commands, the addresses, the lengths and the requests to the interface control module through the system control module to generate a burst reading time sequence. After the data is read back from the PSRAM device, the read data module compares the returned data with the data in the database one by one to give correct and incorrect signals.
As in fig. 11, the read/write state machine is optionally implemented by calibrating the signals of the state machine as follows: clock frequency reduction- > write data- > clock recovery- > read data or write data- > read data. And the selection signal is output to control a clock source of the clock generation module in the states of clock frequency reduction and clock recovery. The clock generation module includes an even divider and a glitch-removing selector. Even number division is used in the frequency divider to simplify the design, since only the effect of reducing the frequency needs to be done in the design. The frequency division factor of 2,4,6,8 times can be selected through the register configuration, and the frequency division is realized through the counter. Glitches are generated on a clock line when a divided clock and an original clock are switched, and a circuit for removing the glitches is provided in a clock selector in order to remove the glitches. As shown in fig. 12, the state control is adopted in which when the clock selection signal changes, the selector output is turned off first and then the clock source is switched. At this time, since the glitch caused by switching the clocks is not output, the glitch of the output is eliminated. After the switch, it is necessary to wait for a period of time, and after the output is turned on, the selector outputs a new clock.
The delay calculation module is used for giving the adjustment of the delay chain according to the different states of the four calibrations and the result of whether the read data is correct or not. In the real-time calibration, only fine adjustment is needed for the delay chain, so that only + -1 is needed for the delay chain after each judgment result. In the initial write calibration, the transmission delay chain is short, so that the delay chain is continuously scanned by +1 after each judgment result. For the read delay chain, the delay chain is divided into two stages and is relatively long, so that the dichotomy is adopted.
Referring to fig. 6 and fig. 13, specifically, the procedure of adding the DQ read delay chain and adopting the initial read calibration scan minimum bisection method is used. And after starting, firstly performing a frequency reduction writing recovery reading process, if the comparison result is wrong, indicating that the delay chain is insufficient, firstly adding a secondary delay chain, and repeatedly performing frequency reduction writing recovery reading until the comparison result is correct. And if the comparison result is correct, the value of the scan chain is in the current primary chain, at this time, the value of the secondary delay chain is reduced by one, the value of the primary delay chain is configured to be half of the maximum value, and the adjustment amount is configured to be 1/4 of the maximum value. Continuing to perform the frequency reduction writing and recovery reading, if the comparison result is wrong, the first-stage delay chain is the delay chain of the last writing and reading plus the adjustment quantity of the last writing and reading, and meanwhile, reducing the adjustment quantity by half; if the comparison result is correct, the first-stage delay chain is the delay chain of the last writing and reading-the adjustment amount of the last writing and reading, and the adjustment amount is halved. And circulating until the adjustment amount is less than 2, and finding the optimal first-stage delay chain value.
As shown in fig. 14, the procedure of initial read calibration scan maximum dichotomy is similar to the minimum finding procedure. The difference is that when the secondary delay chain is adjusted, if the writing and reading processes are correct, the secondary delay chain is added until the first writing and reading result is wrong, namely the boundary of the maximum delay chain is found; the delay chain is added when the first-stage delay chain binary search is correct.
As shown in fig. 15, the calibration state machine is configured to perform initial read calibration and initial write calibration after initialization start, and then enter a complete state. And in the completion state, waiting for a real-time calibration command, and after receiving the command, performing real-time reading calibration and then performing real-time writing calibration. The calibration state machine outputs current state signals to other three modules for calibration in different delay chains and different modes.
The PSRAM controller of this embodiment improves the accuracy of the delay chain and the highest speed of communication with the PSRAM device through calibration flow control and a calibration algorithm. Meanwhile, the implementation can also carry out real-time calibration and is used for compensating equipment delay drift and delay chain drift caused by voltage and temperature in the working process of the chip.
1) The initial read calibration and the write calibration are realized, and the read-write delay chain is ensured to work at the optimal phase;
2) The initial reading calibration adopts dichotomy acceleration, so that the application waiting time is reduced;
3) And the real-time fine adjustment calibration is carried out during real-time idle, the phase drift influence caused by voltage and temperature is compensated, and the stability is improved.
Example two
The embodiment discloses a PSRAM phase calibration method, which comprises the following steps:
s1, acquiring PSRAM starting, and performing initial reading calibration;
referring to fig. 6, wherein step S1 includes: s10, configuring a write delay chain by adopting a register default value, and configuring the read delay chain of STROBE and DQ to 0; s11, reducing the frequency of a working clock; s12, writing the specific number into the PSRAM; specifically, a specific number may be written into the PSRAM by sending a write command, where the specific number may be fixed data set in advance, and when writing into the PSRAM, an address and fixed data set in advance may be sent, for example, the address may be dynamically allocated and also a fixed address set in advance. S13, recovering the clock frequency; the recovered clock frequency of the present embodiment refers to the operation clock frequency before the clock frequency is recovered to the high-speed operation clock, i.e. the operation clock frequency is reduced. S14, reading a specific number from the PSRAM to obtain readback data (S11-S14 are hereinafter referred to as a process of lower writing recovery reading); specifically, a certain number is read from the PSRAM by sending a read command; s15, comparing the read data with a specific number, S16, if the read data is correct, finding the minimum value of a read delay chain window, and executing the step S20; s17, otherwise, increasing the phase between STROBE and DQ by adding a DQ read delay chain; and S18, judging whether the maximum value of the read delay chain is reached, and S19, if the maximum value of the read delay chain is reached, indicating that the value which can not work can not be found even after one time of scanning, and performing error reporting and exiting. S20, reducing the frequency of a working clock; s21, writing the specific number into the PSRAM; s22, recovering the clock frequency; s23, reading a specific number from the PSRAM to obtain read-back data; s24, comparing the read data with a specific number, S25, if the data is wrong, finding the maximum value of a read delay chain window, and executing the step S28; s26, otherwise, increasing the phase between STROBE and DQ by increasing a DQ read delay chain; s27, judging whether the maximum value of the read delay chain is reached, and if so, finding the maximum value of a read delay chain window; s28, averaging the minimum value and the maximum value of the window to be used as a calibration value of the read delay chain;
the present embodiment continues the process of down-writing recovery reading after finding the minimum value of the read delay chain window. When the first read-write error is found or the delay chain reaches the maximum value, the maximum value of the window is found. Finally, the window minimum and maximum values are averaged and applied as a calibration value for the read delay chain.
S3, performing initial writing calibration;
wherein step S3 comprises: s31, configuring a clock write delay chain to be half of the length of the delay chain, and configuring a signal write delay chain to be 0; specifically, the length of the delay chain in this embodiment is changed according to design requirements, but if a certain circuit is designed, the length of the delay chain is not changed; this embodiment may configure the clock write delay chain to be half the length of the write delay chain; s32, writing the specific number into the PSRAM; specifically sending a write command to write the specific number into the PSRAM, wherein the specific write mode is the same as the mode in the step S1; s33, reading a specific number from the PSRAM to obtain read-back data; s34, comparing the read back data with a specific number, S35, if the read back data is correct, finding the minimum value of a write delay chain window, and executing S38; s36, if not, adding a signal writing delay chain, S37, judging whether the maximum value of the delay chain is reached, if so, exceeding the speed, and performing error reporting and exiting; the maximum value of the delay chain in the embodiment refers to the length of the delay chain when the circuit is designed; therefore, the delay chain cannot be adjusted after the maximum value of the delay chain is reached. Hereinafter, the delay chain maximum value is the same. S38, writing the specific number into the PSRAM; s39, reading a specific number from the PSRAM to obtain read-back data; s40, comparing the read data with a specific number, S41, if the data is wrong, finding the maximum value of a write delay chain window; s42, if the signal is correct, adding a signal writing delay chain; s43, judging whether the maximum value of the delay chain is reached, and if so, finding the maximum value of a read delay chain window;
the initial write calibration of this embodiment is similar in flow to the initial read calibration. Because the read calibration is already completed, there is no need for a write-down recovery read process. The first step sets the write delay chain of the clock to half to configure the signal write delay chain to 0 in preparation for scanning the delay chain from 0 to the maximum. And after the minimum value and the maximum value of the delay chain window are sequentially found, the average value of the minimum value and the maximum value is used as the calibration value of the final data writing delay chain.
Referring to fig. 8, further, the PSRAM phase calibration method of this embodiment further includes: s3', real-time reading and calibrating, specifically: s31', reducing the frequency of a working clock; s32', writing a specific number into the PSRAM; s33', recovering the clock frequency; s34', reading a specific number from the PSRAM to obtain read-back data; s35', comparing the read data with a specific number, S36', if the data is correct, keeping the current value of the delay chain, and finishing calibration; s37', if the error occurs, reducing a DQ read delay chain; s38', judging whether the DQ read delay chain is smaller than a set range, and if so, restoring the original value of the DQ read delay chain; and performing steps S31'-34'; s391', comparing the read data with a specific number, S392', if correct, keeping the current value of the delay chain, and finishing calibration; s393', if wrong, adding a DQ read delay chain; s394', judge whether DQ read delay chain is larger than the set range, S395', if yes, calibration fails.
The real-time read calibration of the embodiment first performs a process of down-conversion, write-recovery, and read. Then, comparing the data, if the comparison result is correct, finding out a proper delay value, and finishing calibration; if the comparison is wrong, the DQ read latency chain is reduced, and then a write-down recovery read process is performed. If the DQ read delay chain is smaller than the set range, the value of the DQ read delay chain before real-time calibration is restored, and then the process of frequency reduction, writing and restoring reading is carried out. Continuously comparing the read data, if the comparison result is correct, finding out a proper delay value, and finishing calibration; if the comparison is erroneous, the DQ read latency chain is increased and the write-down recovery read process is repeated. And finally, if the DQ read delay chain is larger than the set range, the calibration fails, otherwise, the value when the reading and writing are correct is applied to the delay chain.
Referring to fig. 9, the present embodiment further includes: s4', real-time writing calibration, which specifically comprises the following steps: s41', writing a specific number into a PSRAM; specifically sending a write command to write the specific number into the PSRAM, wherein the specific write mode is the same as the mode in the step S1; s42', reading a specific number from the PSRAM to obtain read-back data; s43', comparing the read data with a specific number, S44', if correct, keeping the current value of the delay chain, and completing calibration; s45', if not, reducing the signal writing delay chain, S46', judging whether the signal writing delay chain is smaller than a set range, S47', if so, recovering the original value of the signal writing delay chain, and executing the steps S41' -S43'; s48', if the current value is correct, the delay chain keeps the current value, and the calibration is completed; s49', otherwise, adding a signal writing delay chain, S491', judging whether the signal writing delay chain is larger than a set range, S492', if so, failing to calibrate.
The real-time write calibration of the present embodiment first performs a write-read process. Then, the read data are compared, if the comparison result is correct, a proper delay value is found, and the calibration is completed; if the comparison is wrong, the signal writing delay chain is reduced, and then the writing and reading processes are carried out. If the signal writing delay chain is smaller than the set range, the value of the signal writing chain before real-time calibration is restored, and then the process of writing and reading is carried out. Continuously comparing the read data, if the comparison result is correct, finding a proper delay value, and finishing calibration; if the comparison is wrong, a signal writing delay chain is added, and the writing and reading process is repeated. And finally, if the signal writing delay chain is larger than the set range, the calibration fails, otherwise, the value when the reading and writing are correct is applied to the delay chain.
The real-time calibration of the embodiment is only fine-tuned, and whether a proper delay chain value exists in the delay chain with a certain range of reduction and increase is searched. First, the scan attempts to find the correct delay for reading and writing in the decreasing direction. When the reading and writing can not be correctly performed even if the reading and writing is reduced to a certain value, the scanning direction is changed to the increasing direction for scanning. If the correct delay cannot be found even if a certain value is increased, the delay chain is failed due to external conditions, and an error exit needs to be reported.
In the real-time calibration, only fine adjustment is needed for the delay chain, so that only + -1 is needed for the delay chain after each judgment result. In the initial write calibration, the transmission delay chain is short, so that the delay chain is continuously scanned by +1 after each judgment result. For the read delay chain, the delay chain is divided into two stages and is relatively long, so that the dichotomy is adopted.
FIG. 13 shows the flow of the initial read calibration scan minimum dichotomy. And after starting, firstly performing a frequency reduction writing recovery reading process, if the comparison result is wrong, indicating that the delay chain is insufficient, firstly adding a secondary delay chain, and repeatedly performing frequency reduction writing recovery reading until the comparison result is correct. And if the comparison result is correct, the value of the scan chain is in the current primary chain, at this time, the value of the secondary delay chain is reduced by one, the value of the primary delay chain is configured to be half of the maximum value, and the adjustment amount is configured to be 1/4 of the maximum value. Continuing to perform the frequency reduction writing and recovery reading, if the comparison result is wrong, the first-stage delay chain is the delay chain of the last writing and reading plus the adjustment quantity of the last writing and reading, and meanwhile, reducing the adjustment quantity by half; if the comparison result is correct, the first-stage delay chain is the delay chain of the last writing and reading-the adjustment amount of the last writing and reading, and the adjustment amount is halved. And circulating the steps until the adjustment quantity is less than 2, and finding the optimal first-stage delay chain value.
According to the PSRAM phase calibration method, the accuracy of the delay chain is improved through calibration flow control and a calibration algorithm, and the highest speed of communication with PSRAM equipment is improved. Meanwhile, the implementation can also carry out real-time calibration and is used for compensating equipment delay drift and delay chain drift caused by voltage and temperature in the working process of the chip.
1) The initial read calibration and the write calibration are realized, and the read-write delay chain is ensured to work at the optimal phase;
2) The initial reading calibration adopts dichotomy acceleration, so that the application waiting time is reduced;
3) And the real-time fine adjustment calibration is carried out during real-time idle, the phase drift influence caused by voltage and temperature is compensated, and the stability is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. A PSRAM controller comprising: the system comprises a system control module, an interface control module and a phase calibration module, wherein the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing a PSRAM protocol and a time sequence;
the method is characterized in that: the interface control module comprises a read delay chain and a write delay chain; the write delay chain is used for adjusting the delay relation between a write clock and other signals, and the read delay chain is used for adjusting the phase relation between a STROBE signal and DQ;
the phase calibration module uses a burst read-write command, reads and compares specific data after writing the specific data into the PSRAM device, calculates and adjusts a read delay chain and a write delay chain of the interface control module according to the result, and completes phase calibration.
2. The PSRAM controller of claim 1, wherein the read delay chain comprises a two-stage delay chain, the one stage delay chain comprising a series of standard cells with balanced rising and falling edge delays, fine tuned by a data selector output, and the two stage delay chain comprising a plurality of the one stage delay chains in series, coarse tuned by the data selector output.
3. The PSRAM controller of claim 2, wherein the write delay chain is the same as a first stage delay chain of the read delay chain.
4. The PSRAM controller of claim 3, wherein the phase calibration module comprises: the device comprises a calibration state machine, a delay calculation module, a read-write detection module and a clock generation module; the calibration state machine controls a calibration process, which comprises an initial calibration process and a real-time calibration process; the read-write detection module sends specific burst write and read to the system control module and compares the read data to judge whether the read-write is correct or not; the delay calculating unit is used for adjusting the delay chain according to the calibration state and the result of the correctness of the read data; and the clock generation module is controlled according to the calibration state machine to realize burr-free frequency rising and frequency falling of the input original clock.
5. The PSRAM controller of claim 4, wherein the clock generation module comprises: an even frequency divider and a selector for eliminating glitch.
6. A PSRAM phase calibration method is characterized by comprising the following steps:
s1, acquiring PSRAM starting, and performing initial reading calibration;
wherein the step S1 comprises: s10, configuring a write delay chain by adopting a register default value, and configuring the read delay chain of STROBE and DQ to 0; s11, reducing the frequency of a working clock; s12, writing the specific number into the PSRAM; s13, recovering the clock frequency; s14, reading a specific number from the PSRAM to obtain read-back data; s15, comparing the read data with a specific number; s16, if the value is correct, finding the minimum value of the read delay chain window, and executing the step S20; s17, otherwise, increasing the phase between STROBE and DQ by increasing a DQ read delay chain; s18, judging whether the maximum value of the read delay chain is reached; s19, if the maximum value of the delay chain is reached, the fact that the value which can not work can not be found even after one time of scanning is indicated, and error reporting and exiting are carried out; s20, reducing the frequency of a working clock; s21, writing the specific number into the PSRAM; s22, recovering the clock frequency; s23, reading a specific number from the PSRAM to obtain read-back data; s24, comparing the read data with a specific number, S25, if the data is wrong, finding the maximum value of a read delay chain window, and executing the step S28; s26, otherwise, increasing the phase between STROBE and DQ by increasing a DQ read delay chain; s27, judging whether the maximum value of the read delay chain is reached, and if so, finding the maximum value of a read delay chain window; s28, averaging the minimum value and the maximum value of the window to be used as a calibration value of the read delay chain;
s3, performing initial writing calibration;
wherein step S3 comprises: s31, configuring a clock write delay chain to be half of the length of the delay chain, and configuring a signal write delay chain to be 0; s32, writing the specific number into the PSRAM; specifically sending a write command to write the specific number into the PSRAM, wherein the specific write mode is the same as the mode in the step S1; s33, reading a specific number from the PSRAM to obtain read-back data; s34, comparing the read-back data with a certain number, S35, if the read-back data is correct, finding the minimum value of a write delay chain window, and executing S38; s36, if not, adding a signal writing delay chain, S37, judging whether the maximum value of the delay chain is reached, if so, exceeding the speed, and performing error reporting and exiting; s38, writing the specific number into the PSRAM; s39, reading a specific number from the PSRAM to obtain read-back data; s40, comparing the read data with a specific number, S41, if the data is wrong, finding the maximum value of a write delay chain window; s42, if the signal is correct, adding a signal writing delay chain; s43, judging whether the maximum value of the delay chain is reached, and if so, finding the maximum value of a read delay chain window; s44, averaging the minimum value and the maximum value of the window to be used as a calibration value of the write delay chain;
and S5, respectively applying the calibration value of the reading delay chain and the calibration value of the writing delay chain to the reading delay chain and the writing delay chain.
7. The method of claim 6, further comprising: s3', real-time reading and calibrating, specifically: s31', reducing the frequency of a working clock; s32', writing a specific number into the PSRAM; s33', recovering the clock frequency; s34', reading a specific number from the PSRAM to obtain read-back data; s35 'comparing the read data with a specific number, S36', if correct, keeping the current value of the delay chain, and completing calibration; s37', if the error occurs, reducing a DQ read delay chain; s38', judging whether the DQ read delay chain is smaller than a set range, and if so, restoring the original value of the DQ read delay chain; and performing steps S31'-34'; s391', comparing the read data with a specific number, S392', if correct, keeping the current value of the delay chain, and finishing calibration; s393', if wrong, adding a DQ read delay chain; s394', judge whether DQ read delay chain is larger than the set range, S395', if yes, calibration fails.
8. The method of claim 6, further comprising: s4', real-time writing calibration, which specifically comprises the following steps: s41', writing a specific number into a PSRAM; specifically sending a write command to write a specific number into the PSRAM; s42', reading a specific number from the PSRAM to obtain read-back data; s43', comparing the read data with a specific number, S44', if correct, keeping the current value of the delay chain, and completing calibration; s45', if not, reducing the signal writing delay chain, S46', judging whether the signal writing delay chain is smaller than a set range, S47', if so, recovering the original value of the signal writing delay chain, and executing the steps S41' -S43'; s48', if the current value is correct, the delay chain keeps the current value, and the calibration is completed; s49', otherwise, adding a signal writing delay chain, S491', judging whether the signal writing delay chain is larger than a set range, S492', if so, failing to calibrate.
9. The method of claim 7 or 8, wherein the reduced DQ read latency chain, the increased DQ read latency chain, the reduced signal write latency chain, and the increased signal write latency chain are each reduced or increased by 1.
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