CN114171106A - Read-write calibration method and circuit - Google Patents
Read-write calibration method and circuit Download PDFInfo
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- G11C—STATIC STORES
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Abstract
The application provides a read-write calibration method and a circuit, and the method comprises the following steps: respectively verifying the reading and writing accuracy of the storage controllers working under different first phases according to the reading and writing consistency data, wherein the first phases are the phases of first clock signals provided for the storage controllers; when the verification is passed, taking a phase difference of the first phase and a second phase as a candidate phase difference, wherein the second phase is the phase of a second clock signal provided for the memory module; and selecting a target phase difference from the candidate phase differences according to a preset rule, and adjusting a first clock signal of the storage controller to enable the storage controller to work in a first phase corresponding to the target phase difference. According to the method and the device, the reading and writing accuracy of the storage controller under different first phases is verified by automatically adjusting the phase difference between the first phase and the second phase, so that the optimal phase difference is found out, the reading and writing accuracy of the storage controller is automatically calibrated, and the accuracy of reading and writing data is ensured.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a read/write calibration method and circuit.
Background
The memory is widely applied to consumer electronic products such as mobile phones and electronic dictionaries due to the advantages of volume and power consumption, and the read-write accuracy of the memory determines the performance of the electronic products. Therefore, the memory particles need to be operated during the design and production of the memory chip to ensure the correctness of the reading and writing of the memory. For a traditional memory controller, under different clock frequencies, a clock channel or a data channel of the memory controller needs to be adjusted in a time delay manner manually, and then a phase difference between a clock signal of the memory controller and a clock signal of a memory is adjusted, so that the correctness of reading and writing data is ensured, time and labor are wasted, and the memory controller is not flexible and reliable enough.
Disclosure of Invention
The time-delay adjusting device aims to solve the technical problems that time and labor are wasted and accuracy is not high due to the fact that time-delay adjustment is needed to be carried out on a memory in the prior art. The application provides a read-write calibration method and a circuit, and mainly aims to automatically find out the optimal phase difference between a storage controller and a storage module so as to calibrate the read-write accuracy of the storage controller.
In order to achieve the above object, the present application provides a read/write calibration method, including:
respectively verifying the reading and writing accuracy of the storage controllers working under different first phases according to reading and writing consistency data, wherein the reading and writing consistency data comprise: whether the data read from the same memory address of the memory module and the written data are the same or not under the first phase, wherein the first phase is the phase of a first clock signal provided for the memory controller;
when the read-write accuracy verification of the memory controller working under the first phase passes, taking the phase difference between the first phase and a second phase in which the memory module works as a candidate phase difference, wherein the second phase is the phase of a second clock signal provided for the memory module;
selecting a target phase difference from the candidate phase differences according to a preset rule;
and adjusting the first phase of the first clock signal of the storage controller to enable the storage controller to work under the first phase corresponding to the target phase difference.
In addition, in order to achieve the above object, the present application further provides a read/write calibration circuit, which includes a clock module, a calibration module, and a memory controller connected to each other;
the clock module is used for providing a first clock signal for the memory controller and the calibration module and providing a second clock signal for the memory module, wherein a phase difference exists between a first phase of the first clock signal and a second phase of the second clock signal;
the memory controller is used for working under a first clock signal to read and write data of the memory module working under a second clock signal;
the calibration module includes:
the first adjusting module is used for adjusting a first phase of the first clock signal through the clock module so as to adjust a phase difference between the first phase and the second clock signal;
the verification module is used for respectively verifying the read-write accuracy of the storage controllers working under different first phases according to read-write consistency data, and the read-write consistency data comprises: whether the data read from the same memory address of the memory module and the written data are the same or not under the first phase, wherein the first phase is the phase of a first clock signal provided for the memory controller;
the first screening module is used for taking the phase difference between the first phase and a second phase in which the storage module works as a candidate phase difference when the read-write accuracy verification of the storage controller working under the first phase passes, wherein the second phase is the phase of a second clock signal provided for the storage module;
the second screening module is used for selecting a target phase difference from the candidate phase differences according to a preset rule;
and the second adjusting module is used for adjusting the first phase of the first clock signal of the storage controller so that the storage controller works under the first phase corresponding to the target phase difference.
According to the read-write calibration method and circuit, the phase difference between the storage controller and the storage module is automatically adjusted to verify the read-write accuracy of the storage controller working under different first phases, so that the optimal phase difference is found out from different phase differences corresponding to different first phases, and then the storage controller finally works under the first phase corresponding to the optimal phase difference, so that the read-write accuracy of the storage controller is automatically calibrated, and the correctness of read-write data is guaranteed.
Drawings
FIG. 1 is a schematic flow chart illustrating a read/write calibration method according to an embodiment of the present application;
FIG. 2 is a block diagram of a read/write calibration circuit according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a read/write calibration circuit according to another embodiment of the present disclosure.
The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Fig. 1 is a schematic flow chart of a read/write calibration method according to an embodiment of the present application. Referring to fig. 1, the method is illustrated as applied to a calibration module or a calibration apparatus. The read-write calibration method comprises the following steps S100-S400.
S100: respectively verifying the reading and writing accuracy of the storage controllers working under different first phases according to the reading and writing consistency data, wherein the reading and writing consistency data comprises the following steps: and whether the data read from the same memory address of the memory module and the written data are the same or not under the first phase, wherein the first phase is the phase of a first clock signal provided for the memory controller.
Specifically, the memory controller operates in a first phase and the memory block operates in a second phase, the different first and second phases each having a different phase difference, the second phase being the phase of a second clock signal provided to the memory block. The memory controller is used for performing operations such as reading and writing operations on the memory granules in the memory module, that is, other operations such as writing data into the memory granules of the memory module or reading data from the memory granules of the memory module. The storage module is a memory, and may specifically be a psram (pseudo random access memory). The PSRAM has the highest working clock of 200MHZ, the bit width supports 4/8/16 bits, and the read-write access is carried out in a clock double-edge mode.
Data needs to be sampled through the upper edge and the lower edge of a clock, the sampling clock needs to be adjusted to be in a proper state to ensure the accuracy of the sampled data, otherwise, error codes or metastable states are easily generated when the data is read from a memory in the sampling process of the data. The clock module may provide a plurality of first clock signals having different first phases to the memory controller, and provide a second clock signal to the memory module, the first clock signal being an operating clock of the memory controller, the second clock signal being an operating clock of the memory module. The memory controller controls the memory module to read and write data according to the first clock signal, wherein the memory module is controlled by the second clock signal and driven by the second clock signal. The phase difference between the first clock signal and the second clock signal is a key factor for enabling data to be correctly read from the memory module.
For each first phase, the corresponding read-write consistency data is: and whether the data read from the same memory address of the memory module and the written data are the same or not by the memory controller operating in the first phase.
In one embodiment, before step S100, the calibration module is configured, for example, to configure the maximum number of loop detections and the scanning window. The maximum number of the cyclic detection is a preset verification number or a maximum verification number for performing read-write verification on the storage controller under each phase difference; the scanning window is the difference value of two adjacent phase differences or the step length of the next phase difference obtained from the current phase difference. The memory controller is configured to provide a clock frequency of a clock module of the first clock signal and the second clock signal and an initial phase difference of the first clock signal and the second clock signal. For example, the clock frequency may be set to any frequency point of 0 to 200MHz, and the initial phase difference may be set to 30 °. And configuring modes of read-write calibration, such as an automatic calibration mode and a manual calibration module. The present application is implemented in an auto-calibration mode.
The clock module provides first clock signals with different first phases for the memory controller, provides second clock signals with the same second phase for the memory module, and the memory controller controls the writing and reading operations of the memory module under different first phases. The calibration module respectively compares the data written in by the memory controller working at different first phases with the read data to verify the read-write accuracy of the memory controller at different first phases, wherein a phase difference exists between the memory controller working at the first phase and the memory module working at the second phase, and the phase difference is the difference between the first phase and the second phase. The first phase can be calculated according to the phase difference and the second phase, that is, the first phase and the phase difference have a corresponding relationship. For example, the calibration module compares data read from the same memory address by the memory controller operating in the initial phase with previously written data, and determines whether the data read by the memory controller in the initial phase is the same as the written data. Specifically, the first phase is the sum of the second phase and the current phase difference, the current phase difference is the sum of the last phase difference and a preset scanning window, the initial value of the current phase difference is a preset initial phase difference, the current phase difference is smaller than or equal to a cut-off phase difference, that is, the cut-off value of the current phase difference is a cut-off phase difference, and the cut-off value of the first phase is the sum of the second phase and the cut-off phase difference; the initial phase difference is a preset phase difference starting point, and the cut-off phase difference is a preset phase difference end point. Specifically, in an alternative embodiment, the different first phases are an initial phase, an initial phase +1 × scan window, an initial phase +2 × scan window, … …, an initial phase + n × scan window, … …, and a cutoff phase, respectively, where n is a natural number.
In order to ensure the reliability and authenticity of the read-write accuracy verification, the calibration module can respectively verify the read-write accuracy of the memory controller working in the same first phase for multiple times. And if the data read from the same storage address by the storage controller working in the same first phase is the same as the previously written data in multiple times of verification, judging that the reading and writing accuracy of the storage controller in the first phase is normal. And if the data read from the same memory address by the memory controller at any time is different from the previously written data in multiple times of verification, judging that the reading and writing accuracy of the memory controller at the first phase is abnormal.
The calibration module can be composed of an FPGA/CPLD device, the FPGA/CPLD device is a reconfigurable device, the circuit is programmable, and different circuits can be generated by modifying a programming file. In contrast, in the conventional ASIC device, the circuit is not secondarily modified once it is generated. Therefore, the read-write accuracy of the memory controller working under different clock frequencies, different bit widths and different phases can be verified and calibrated by using the FPGA/CPLD device.
The clock module may be a pll (phase Locked loop): the phase-locked loop or phase-locked loop is used for uniformly integrating clock signals to ensure that high-frequency devices work normally, such as the access data of a memory.
The step realizes that the first phase is adjusted by adjusting the phase difference between the first phase and the second phase, and consistency verification is carried out on data read out from the same storage address and written in by the read-write controllers working at different first phases, so that read-write verification is respectively carried out on the read-write controllers working at each first phase.
S200: and when the read-write accuracy verification of the memory controller working under the first phase passes, taking the phase difference between the first phase and a second phase in which the memory module works as a candidate phase difference, wherein the second phase is the phase of a second clock signal provided for the memory module.
Specifically, if the read-write consistency data indicates that the memory controller operates in the same first phase and the data read from the same memory address is the same as the previously written data, the phase difference between the first phase and the second phase of the memory block is a candidate phase difference.
S300: and selecting a target phase difference from the candidate phase differences according to a preset rule.
S400: and adjusting the first phase of the first clock signal of the storage controller to enable the storage controller to work under the first phase corresponding to the target phase difference.
Specifically, the target phase difference is a phase difference between the target first phase and the target second phase of the final operation of the memory controller, and is an optimal phase difference among the candidate phase differences, and may be any one of the candidate phase differences. For example, one of the candidate phase differences that is an intermediate value may be selected as the target phase difference. And obtaining a target first phase according to the sum of the target phase difference and the second phase, and adjusting the delay of the first clock signal to adjust the phase of the first clock signal of the memory controller back to the target first phase, so that the memory controller can work under the target first phase. The storage controller working at the target first phase can ensure the correctness of reading and writing data.
In the embodiment, the calibration module is used for automatically screening out the optimal phase difference between the first clock signal and the second clock signal of the memory controller and the memory module, and adjusting the first clock signal of the memory controller to the first phase corresponding to the optimal phase difference, so that the read-write calibration of the memory controller under any working frequency or data bit width is realized, and the accuracy of the read-write data is ensured.
In one embodiment, step S100 specifically includes:
and respectively verifying the read-write accuracy of the memory controller working in any first phase from the initial phase to the cut-off phase aiming at the current first phase:
controlling the memory controller to write data into any available address of the memory module working in the second phase in the current first phase;
wherein the written data is a written result.
Controlling the memory controller to read data from an available address of the memory module operating in the second phase at the current first phase;
wherein the read data is a read result.
Comparing whether the data written by the memory controller in the current first phase is the same as the read data;
wherein, whether the writing result and the reading result respectively obtained in the first two steps are the same or not is compared.
Accumulating verification times of read-write accuracy verification of the storage controller working in the current first phase;
if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times do not reach the preset verification times, circularly executing the step of controlling the storage controller to write data into any available address of the storage module working under the second phase under the current first phase to the step of accumulating the verification times of the read-write accuracy verification of the storage controller working under the current first phase;
if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times reach the preset verification times, ending the verification of the read-write accuracy of the storage controller working in the current first phase;
and if the data written in the current first phase by the storage controller is different from the read data, finishing the verification of the read-write accuracy of the storage controller working in the current first phase.
Specifically, as described above, any one of the first phases from the initial phase to the cut-off phase is the sum of the corresponding phase difference and the second phase, and therefore, the first phase and the phase difference have a corresponding relationship. The initial phase difference to the cut-off phase difference corresponds to the initial phase to the cut-off phase. The cut-off phase difference is an end point of the phase difference set in advance. The initial phase difference to the cut-off phase difference include a plurality of different phase differences and differences of adjacent phase differences are equal or a step from a current phase difference to a next phase difference is equal, including the initial phase difference and the cut-off phase difference. The delay value of 1 step is 1/8 cycles of the VCO frequency in the configuration parameters of the clock module.
When a system where a memory controller and a calibration module are located is initialized, the calibration module enters an IDLE state (IDLE); when the calibration module detects that the initialization flag signal cfg _ done sent by the memory controller is high, indicating that the initialization of the memory module (e.g., a memory granule of the PSRAM) controlled by the memory controller is completed, the calibration module enters a write DATA state WR _ DATA.
The clock module provides a first clock signal for the memory controller and a second clock signal for the memory module, a phase difference exists between the first clock signal and the second clock signal, the phase difference is a certain phase difference between a start phase difference and a stop phase difference, and the current phase difference is a phase difference between a current first phase where the memory controller works and a second phase of the memory module.
The calibration module sends a write request WR _ req to the memory controller operating in the current first phase in a write DATA state WR _ DATA, and the memory controller operating in the current first phase returns a ready-to-write signal WR _ rdy to the calibration module after receiving the write request WR _ req, wherein the ready-to-write signal WR _ req indicates that the memory controller operating in the current first phase is in a state of being ready to write. After receiving the ready-to-write signal wr _ rdy, the calibration module sends data wr _ data to be written and an address wr _ addr to be written to the memory controller operating in the current first phase, the memory controller operating in the current first phase writes the data wr _ data to be written to the address wr _ addr to be written to the memory module, and after the writing is completed, the memory controller operating in the current first phase sends a write completion signal wr _ done to the calibration module.
And the calibration module enters a DATA reading state RD _ DATA after receiving the write completion signal wr _ done. In the read DATA state RD _ DATA, the calibration module sends a read request red _ req to the memory controller operating in the current first phase, and the memory controller operating in the current first phase returns a read valid signal RD _ valid to the calibration module after receiving the read request RD _ req, where the read valid signal RD _ valid indicates that the memory controller operating in the current first phase can currently read DATA. After receiving the valid reading signal rd _ valid, the calibration module sends an address rd _ addr to be read to the memory controller operating in the current first phase, the memory controller operating in the current first phase reads data rd _ data from the address rd _ addr to be read of the memory module and returns the data rd _ data to the calibration module, and after the reading is completed, the memory controller operating in the current first phase sends a read completion signal rd _ done to the calibration module.
The calibration module enters an SAMPLE state after receiving a read completion signal rd _ done, and accumulates the verification times of the memory controller working in the current first phase, that is, the counter loop _ cnt accumulates 1. The counter loop _ cnt is used for accumulating the verification times of the memory controller in the same first phase. The counter loop _ cnt is cleared and then counted again when the memory controller is operating in another first phase.
If the DATA written in the current first phase by the memory controller is the same as the read DATA and the accumulated verification times do not reach the preset verification times, the memory controller circularly executes the steps to re-enter the WR _ DATA state, writes DATA into a certain memory address of the memory module through the memory controller working in the current first phase again, reads the DATA from the same memory address, compares whether the written DATA is the same as the read DATA to verify the read-write function of the memory controller working in the current first phase, and accumulates the verification times until the accumulated verification times reach the preset verification times or the DATA written in the current first phase by the memory controller is different from the read DATA, and stops performing read-write accuracy verification on the memory controller in the current first phase.
And if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times reach the preset verification times, or the data written in the current first phase by the storage controller is different from the read data, ending the read-write accuracy verification of the storage controller working in the current first phase.
That is, if the data written by the storage controller operating in the current first phase is different from the read data and the accumulated verification times do not reach the preset verification times, the read-write accuracy verification of the storage controller operating in the current first phase is finished; and if the data written in by the storage controller working in the current first phase is different from the read data and the accumulated verification times reach the preset verification times, ending the verification of the reading and writing accuracy of the storage controller working in the current first phase.
And a register is arranged in the calibration module and used for storing the result of each verification. If the data written in by the memory controller in the current first phase is different from the data read out by the memory controller, the error bit corresponding to the register is high, which indicates that an error code exists in the current verification stage, and at this time, the calibration module does not perform read-write accuracy verification on the memory controller working in the current first phase any more. And if the current first phase is not the cut-off phase, the memory controller works in the next first phase, and the calibration module performs at least one read-write accuracy verification on the memory controller working in the next first phase according to the same method.
The storage controller operates in any first phase, the verification times of the storage controller in the first phase are at least one time, and the maximum verification times do not exceed the preset verification times. The larger the preset verification times are set, the more in-place verification of the storage controller is and the more credible the verification is. The preset verification times can be preset according to actual conditions, for example, 200 times, and the actual verification times do not exceed 200 times.
The embodiment realizes the automatic verification of the read-write accuracy of the storage controller working in different first phases.
In one embodiment, the initial phase is a sum of the second phase and the initial phase difference, and the cut-off phase is a sum of the second phase and the cut-off phase difference.
Step S100 further includes:
after the read-write accuracy verification of the storage controller working under the current first phase is finished, if the current phase difference between the current first phase and the second phase is not a cut-off phase difference, scanning the current phase difference according to a scanning window to obtain the next phase difference;
obtaining a next first phase according to the sum of the next phase difference and the second phase, adjusting the first phase of the first clock signal, enabling the memory controller to work in the next first phase, and taking the next first phase as the current first phase; that is, the next first phase is obtained according to the sum of the next phase difference and the second phase, and the current first phase is updated according to the next first phase; and adjusting the phase of the first clock signal according to the updated current first phase, so that the memory controller works in the updated current first phase.
After finishing the verification of the read-write accuracy of the storage controller working under the current first phase, if the current phase difference between the current first phase and the second phase is a cut-off phase difference, finishing the verification of the read-write accuracy of the storage controller working under different first phases.
Specifically, if the data written by the memory controller in the current first phase is different from the read data, the calibration module does not verify the read-write accuracy of the memory controller operating in the current first phase any more, but adjusts the phase difference to adjust the first phase of the memory controller, so that the memory controller operates in the next first phase, and verifies the read-write accuracy of the memory controller operating in the next phase. The next first phase is the sum of the next phase difference and the second phase, and the next phase difference is obtained by scanning the current phase difference according to the scanning window.
And after the read-write accuracy verification of the storage controller working in the current first phase is stopped, the calibration module enters an ADJUST state. In the ADJUST state, if the phase difference between the current first phase and the second phase is not the cut-off phase difference, the calibration module ADJUSTs the phase difference between the first clock signal and the second clock signal according to the scanning window on the basis of the current phase difference, so that the next phase difference is obtained by adding the current phase difference and the scanning window. The specific phase difference adjustment is that the calibration module adjusts the first phase of the first clock signal, and the second phase of the second clock signal is kept unchanged, so that the purpose of adjusting the phase difference of the first clock signal and the second clock signal is achieved.
For example, the current phase difference is 30 °, the scanning window is 30 °, and the next phase difference is 60 °. Similarly, the same scan window is 30 °, and if the current phase difference is 60 °, the next phase difference is 90 °. The scanning window is preconfigured and the scanning window or step size can also be limited by setting a maximum number of scanning steps. For example, if the maximum scanning step number is limited not to exceed 12 steps, the value range of the scanning window can be obtained according to the initial phase difference and the cut-off phase difference.
Furthermore, if the current phase difference is the cut-off phase difference, the current phase difference is the last phase difference to be verified, so after the verification of the read-write accuracy of the memory controller working under the current first phase is finished, the verification of all possible phase differences is completed, and the verification step can be stopped.
In one embodiment, step S200 specifically includes:
and under the condition that the accumulated verification times reach the preset verification times and the data written in and read out by the storage controller are verified to be the same each time, taking the phase difference between the current first phase operated by the storage controller and the second phase operated by the storage module as a candidate phase difference. That is, when the accumulated verification times reaches the preset verification times and the data written in and read out by the memory controller are verified at each time to be the same, the read-write accuracy verification of the memory controller working at the first phase passes.
Specifically, for example, the initial phase difference is 30 °, the cutoff phase difference is 180 °, and the scanning window is 30 °, then all phase differences include: 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees and 180 degrees. The first phase corresponding to each phase difference is obtained according to the sum of the 6 phase differences of 30 degrees, 60 degrees, 90 degrees, 120 degrees, 150 degrees and 180 degrees and the second phase. And performing read-write accuracy verification on the memory controller working in each first phase for at most 200 times. After scanning 30-180 °, if only the data read out from the same memory address by the read/write controller each time in 200 respective read/write accuracy verifications by the memory controller at the first phase corresponding to the 3 phase differences of 90 °, 120 °, and 150 ° are the same as the data written in before, then 90 °, 120 °, and 150 ° are taken as candidate phase differences.
In one embodiment, step S300 specifically includes:
and selecting the candidate phase difference with the phase difference as a middle value from the continuous candidate phase differences with the largest quantity as the target phase difference. Specifically, one or more continuous phase difference sequences are selected from candidate phase differences, wherein the difference between every two adjacent candidate phase differences in the continuous phase difference sequences is a preset scanning window; and selecting the continuous phase difference sequence with the largest number of candidate phase differences, and taking the candidate phase difference with the phase difference as a middle value in the selected continuous phase difference sequence as a target phase difference.
Specifically, the target phase difference is an intermediate value of a segment of consecutive correct phase differences. For example, if 90 °, 120 °, and 150 ° are candidate phase differences, 120 ° is taken as the target phase difference.
As another example, the scanning window is 10 °, the candidate phase differences are 30 °, 40 °, 50 °, 60 °, 70 °, 120 °, 130 °, 140 °, and then the consecutive phase difference sequence 1 is: [30 °, 40 °, 50 °, 60 °, 70 ° ], the continuous phase difference sequence 2 is [120 °, 130 °, 140 ° ], the data of candidate phase differences in the continuous phase difference sequence 1 is 5, the data of candidate phase differences in the continuous phase difference sequence 2 is 3, and the intermediate value 50 ° of the continuous phase difference sequence 1 is selected as the target phase difference. Further, if the consecutive phase difference sequence 1 is: [30 °, 40 °, 50 °, 60 ° ], the intermediate values are 40 ° and 50 °, respectively, if the number of candidate phase differences is even, and both values can be regarded as the target phase difference.
In one embodiment, comparing whether the data written by the memory controller and the data read by the memory controller under the current phase difference are the same comprises:
acquiring the read delay of the storage controller;
according to the read delay, carrying out alignment processing on the data written in the current first phase and the read data of the memory controller;
and comparing the written data after the alignment processing with the correspondingly read data to judge whether the data are the same.
In particular, the read latency of the memory controller is an inherent property, generally related to the hardware performance of the system (e.g., frequency related, chip related) and is not completely avoidable. All previous states are for finding the best clock sampling window, resulting in the best phase difference. However, there may be cases where the high and low bytes are inverted or staggered by one clock cycle, and automatic byte alignment is required.
And acquiring data written in and data read out from the same storage address by the storage controller, aligning the data written in and the data read out from the same storage address, acquiring an alignment value in the alignment operation process, and acquiring the read delay of the storage controller according to the alignment value. Since read latency is an inherent property, the resulting read latency applies to the various stages. When the read-write accuracy of the memory controller is verified each time, the written data and the read data need to be aligned first, so as to eliminate the interference of the read delay on the verification result.
In one embodiment, the method further comprises: acquiring the read delay of the storage controller; and according to the read delay, performing alignment processing on the data read out each time by the memory controller working at the first phase corresponding to the target phase difference, and taking the read data after the alignment processing as final read data.
Specifically, even if there is a read delay in the target phase difference, the data read by the memory controller operating in the target phase difference also needs to be aligned to be correctly read.
According to the method and the device, the traditional storage controller is combined with the calibration module and the clock module, the time delay adjustment of the clock channel or the data channel under different clock frequencies and different bit widths is realized, the time delay adjustment of the clock channel or the data channel of the storage is not needed manually, time and labor are saved, the device has wide application, the correctness of reading and writing data is guaranteed, and the device is flexible and reliable.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
FIG. 2 is a block diagram of a read/write calibration circuit according to an embodiment of the present disclosure; referring to fig. 2, the read-write calibration circuit includes a clock module, a calibration module, and a memory controller connected to each other;
the clock module is used for providing a first clock signal for the memory controller and the calibration module and providing a second clock signal for the memory module, wherein a phase difference exists between a first phase of the first clock signal and a second phase of the second clock signal;
the memory controller is used for working under a first clock signal to read and write data of the memory module working under a second clock signal;
the calibration module includes:
a first adjusting module for adjusting a first phase of the first clock signal by the clock module to adjust a phase difference between the first phase and the second phase,
the verification module is used for respectively verifying the read-write accuracy of the storage controllers working under different first phases according to the read-write consistency data, and the read-write consistency data comprises the following steps: whether the data read from the same storage address of the storage module and the written data are the same or not under a first phase, wherein the first phase is the phase of a first clock signal provided for the storage controller;
the first screening module is used for taking the phase difference between a first phase and a second phase in which the storage module works as a candidate phase difference when the read-write accuracy verification of the storage controller working under the first phase passes, wherein the second phase is the phase of a second clock signal provided for the storage module;
the second screening module is used for selecting a target phase difference from the candidate phase differences according to a preset rule;
and the second adjusting module is used for adjusting the first phase of the first clock signal of the storage controller so that the storage controller works under the first phase corresponding to the target phase difference.
Referring to fig. 2, the clock module provides a first clock signal to the memory controller and the calibration module, the first clock signal being a system operating clock of the memory controller and the calibration module, and provides a second clock signal to the memory module through an interface of the memory controller, the second clock signal being an operating clock of the memory module for driving the memory module. The memory controller controls the memory module controlled by the second clock signal to read and write the memory particles according to the first clock signal. The calibration module receives the first clock signal as a clock of the calibration module, and is also used for changing the phase of the first clock signal by controlling the clock module, so as to adjust the phase difference between the first clock signal and the second clock signal, and enable the memory controller to work under different first phases corresponding to different phase differences. The read/write calibration circuit of fig. 2 adjusts the phase difference between the first clock signal and the second clock signal by changing one clock signal while keeping the other clock signal unchanged.
More specifically, the first and second clock signals are the sclk and clk clock signals, respectively. The calibration block receives the sclk clock signal as a clock for the calibration block. The calibration module may also include a user interface through which a user may configure various parameters of the calibration module.
In one embodiment, the verification module is specifically configured to verify the read-write accuracy of the memory controller operating in any one first phase from the initial phase to the cut-off phase by:
the write control module is used for controlling the storage controller to write data into any available address of the storage module working under the second phase under the current first phase;
the read control module is used for controlling the storage controller to read data from an available address of the storage module working in the second phase at the current first phase;
the comparison module is used for comparing whether the data written by the memory controller in the current first phase is the same as the read data;
the counting module is used for accumulating verification times of read-write accuracy verification of the storage controller working in the current first phase;
the first circulation module is used for circulating to the write control module to the counting module if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times do not reach the preset verification times;
the first ending module is used for ending the read-write accuracy verification of the storage controller working under the current first phase if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times reach the preset verification times;
and the second ending module is used for ending the read-write accuracy verification of the storage controller working under the current first phase if the data written into the storage controller under the current first phase is different from the read data.
In one embodiment, the verification module further comprises:
the phase difference adjusting module is used for scanning the current phase difference according to the scanning window to obtain the next phase difference if the current phase difference between the current first phase and the second phase is not a cut-off phase difference after finishing the read-write accuracy verification of the storage controller working under the current first phase;
the third adjusting module is used for obtaining a next first phase according to the sum of the next phase difference and the second phase, adjusting the first phase of the first clock signal, enabling the memory controller to work in the next first phase, and taking the next first phase as the current first phase;
that is to say, the third adjusting module is configured to obtain a next first phase according to a sum of the next phase difference and the second phase, and update the current first phase according to the next first phase; and adjusting the phase of the first clock signal according to the updated current first phase, so that the memory controller works in the updated current first phase.
And a third ending module, configured to end execution of the verification module if a current phase difference between the current first phase and the second phase is a cut-off phase difference after completing verification of read-write accuracy of the memory controller operating in the current first phase.
In one embodiment, the first screening module is specifically configured to: and when the read-write accuracy verification of the memory controller working under the first phase passes, taking the phase difference between the first phase and a second phase in which the memory module works as a candidate phase difference, wherein the second phase is the phase of a second clock signal provided for the memory module.
In one embodiment, the second filtering module is specifically configured to select, as the target phase difference, a candidate phase difference with a phase difference as a median value from among the largest and consecutive candidate phase differences. Specifically, the second screening module is configured to select one or more continuous phase difference sequences from the candidate phase differences, where a difference between every two adjacent candidate phase differences in the continuous phase difference sequences is a preset scanning window; and selecting the continuous phase difference sequence with the largest number of candidate phase differences, and taking the candidate phase difference with the phase difference as a middle value in the selected continuous phase difference sequence as a target phase difference.
In one embodiment, the comparing module specifically includes:
the delay acquisition module is used for acquiring the read delay of the storage controller;
the alignment module is used for performing alignment processing on the data written in the current first phase and the read data of the memory controller according to the read delay;
and the comparison module is used for comparing the data written after the alignment processing with the data read correspondingly to judge whether the data are the same.
In one embodiment, the present application provides a read-write calibration apparatus, comprising:
a first adjusting module for adjusting a first phase of the first clock signal by the clock module to adjust a phase difference between the first phase and the second phase,
the verification module is used for respectively verifying the read-write accuracy of the storage controllers working under different first phases according to read-write consistency data, and the read-write consistency data comprises: whether the data read from the same memory address of the memory module and the written data are the same or not under the first phase, wherein the first phase is the phase of a first clock signal provided for the memory controller
The first screening module is used for taking the phase difference between the first phase and a second phase in which the storage module works as a candidate phase difference when the read-write accuracy verification of the storage controller working under the first phase passes, wherein the second phase is the phase of a second clock signal provided for the storage module;
the second screening module is used for selecting a target phase difference from the candidate phase differences according to a preset rule;
and the second adjusting module is used for adjusting the first phase of the first clock signal of the storage controller so that the storage controller works under the first phase corresponding to the target phase difference.
FIG. 3 is a block diagram of a read/write calibration circuit according to an embodiment of the present disclosure; the clock module is a PLL phase-locked loop, the storage module is a PSRAM pseudo random access memory, and the storage controller is a PPSRAM storage controller. The calibration module, the PSRAM storage controller and the clock module PLL are packaged into an FPGA/CPLD device and used for performing data read-write operation and read-write calibration operation on PSRAM pseudo random access memory from PSRAM storage particles. The clock module PLL provides the PSRAM _ sclk clock signal and the PSRAM _ clk clock signal to the PSRAM memory controller, and provides the PSRAM _ sclk clock signal to the calibration module as the operating clock signal of the calibration module. The calibration module controls a clock module PLL to adjust the PSRAM _ sclk clock signal through a PLL _ adjust signal according to the PSRAM _ sclk clock signal so as to adjust the phase difference between the PSRAM _ sclk clock signal and the PSRAM _ clk clock signal. Since data is sampled by a clock, the delay adjustment of the PSRAM _ sclk affects the reading and writing of data by the memory controller, and the PSRAM memory controller has different capabilities of reading and writing data under different phase differences. The reading and writing accuracy of the PSRAM storage controller working under different phase differences is verified, so that the optimal phase difference is screened out and used as the final working phase difference of the PSRAM storage controller.
The specific implementation process of the read-write calibration circuit of the present application is the same as the read-write calibration method described above, and is not described herein again.
Wherein the meaning of "first" and "second" in the above modules/units is only to distinguish different modules/units, and is not used to define which module/unit has higher priority or other defining meaning. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such process, method, article, or apparatus, and such that a division of modules presented in this application is merely a logical division and may be implemented in a practical application in a further manner.
For the specific limitations of the read/write calibration apparatus, reference may be made to the limitations of the read/write calibration method above, and details are not repeated here. All or part of the modules in the read-write calibration device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which includes a memory, a processor, and computer readable instructions (e.g., a computer program) stored on the memory and executable on the processor, and when the processor executes the computer readable instructions, the steps of the read-write calibration method in the above embodiments are implemented, for example, steps S100 to S300 shown in fig. 1 and other extensions of the method and related steps. Alternatively, the processor executes the computer readable instructions to implement the functions of the modules/units of the read-write calibration apparatus in the above embodiments. To avoid repetition, further description is omitted here.
The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the computer device and the various interfaces and lines connecting the various parts of the overall computer device.
The memory may be used to store computer readable instructions and/or modules, and the processor may implement various functions of the computer apparatus by executing or executing the computer readable instructions and/or modules stored in the memory and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, video data, etc.) created according to the use of the cellular phone, etc.
The memory may be integrated in the processor or may be provided separately from the processor.
Those skilled in the art will appreciate that the illustrated architecture is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer readable storage medium is provided, on which computer readable instructions are stored, which when executed by a processor implement the steps of the read-write calibration method in the above embodiments, such as the steps S100 to S300 shown in fig. 1 and extensions of other extensions and related steps of the method. Alternatively, the computer readable instructions, when executed by the processor, implement the functions of the modules/units of the read-write calibration apparatus in the above embodiments. To avoid repetition, further description is omitted here.
It will be understood by those of ordinary skill in the art that all or part of the processes of the methods of the embodiments described above may be implemented by instructing associated hardware to implement computer readable instructions, which may be stored in a computer readable storage medium, and when executed, may include processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double-rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), synchronous Link (Synchlink) DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, apparatus, article, or method that includes the element.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments. Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present application may be substantially or partially embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.
The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.
Claims (10)
1. A read-write calibration method is applied to a calibration module, the calibration module is connected with a storage controller, and the method is characterized by comprising the following steps:
respectively verifying the reading and writing accuracy of the storage controllers working under different first phases according to reading and writing consistency data, wherein the reading and writing consistency data comprise: whether the data read from the same memory address of the memory module and the written data are the same or not under the first phase, wherein the first phase is the phase of a first clock signal provided for the memory controller;
when the read-write accuracy verification of the memory controller working under the first phase passes, taking the phase difference between the first phase and a second phase in which the memory module works as a candidate phase difference, wherein the second phase is the phase of a second clock signal provided for the memory module;
selecting a target phase difference from the candidate phase differences according to a preset rule;
and adjusting a first phase of a first clock signal of the storage controller to enable the storage controller to work under the first phase corresponding to the target phase difference.
2. The method of claim 1, wherein verifying the read-write accuracy of the memory controllers operating in different first phases according to the read-write consistency data respectively comprises:
for the current first phase, controlling the memory controller to write data into any available address of the memory module working in the second phase in the current first phase;
controlling a memory controller to read data from the available address of a memory module operating in the second phase at the current first phase;
comparing whether the data written by the memory controller in the current first phase is the same as the read data;
accumulating verification times of read-write accuracy verification of the storage controller working under the current first phase;
if the data written in the current first phase by the memory controller is the same as the read data and the accumulated verification times do not reach the preset verification times, circularly executing the step of controlling the memory controller to write data into any available address of the memory module working under the second phase under the current first phase to the step of accumulating the verification times of the read-write accuracy verification of the memory controller working under the current first phase;
if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times reach the preset verification times, ending the verification of the reading and writing accuracy of the storage controller working in the current first phase;
and if the data written in the current first phase by the storage controller is different from the read data, ending the read-write accuracy verification of the storage controller working in the current first phase.
3. The method of claim 2, wherein the first phase is a sum of the second phase and a current phase difference, the current phase difference is a sum of a last phase difference and a preset scanning window, an initial value of the current phase difference is a preset initial phase difference, and the current phase difference is less than or equal to a cut-off phase difference;
after the verifying the read-write accuracy capability of the storage controller working in the current first phase is finished, the method further includes:
if the current phase difference between the current first phase and the second phase is not a cut-off phase difference, scanning the current phase difference according to a scanning window to obtain a next phase difference;
obtaining a next first phase according to the sum of the next phase difference and the second phase, and updating the current first phase according to the next first phase;
adjusting the phase of the first clock signal according to the updated current first phase, so that the memory controller works in the updated current first phase;
and if the current phase difference between the current first phase and the second phase is a cut-off phase difference, ending verification of the read-write accuracy of the storage controller working under different first phases.
4. The method of claim 2, wherein the determining a phase difference between the first phase and a second phase in which the memory module operates as a candidate phase difference when the read-write accuracy of the memory controller operating in the first phase is verified comprises:
when the accumulated verification times reach preset verification times and the data written in and read out by the storage controller are verified to be the same each time, verifying that the reading and writing accuracy of the storage controller working in the first phase passes;
and taking the phase difference between the current first phase operated by the storage controller and the second phase operated by the storage module as a candidate phase difference.
5. The method of claim 4, wherein selecting a target phase difference from the candidate phase differences according to a predetermined rule comprises:
selecting one or more continuous phase difference sequences from the candidate phase differences, wherein the difference between every two adjacent candidate phase differences in the continuous phase difference sequences is a preset scanning window;
and selecting the continuous phase difference sequence with the largest number of candidate phase differences, and taking the candidate phase difference with the phase difference as a middle value in the selected continuous phase difference sequence as a target phase difference.
6. A read-write calibration circuit is characterized by comprising a clock module, a calibration module and a storage controller which are connected;
the clock module is used for providing a first clock signal for the memory controller and the calibration module and providing a second clock signal for the memory module, wherein a phase difference exists between a first phase of the first clock signal and a second phase of the second clock signal;
the memory controller is used for working under the first clock signal to read and write data of the memory module working under the second clock signal;
the calibration module includes:
a first adjusting module for adjusting a first phase of the first clock signal by the clock module to adjust a phase difference between the first phase and the second phase,
the verification module is used for respectively verifying the read-write accuracy of the storage controllers working under different first phases according to read-write consistency data, and the read-write consistency data comprises: whether the data read from the same memory address of the memory module and the written data are the same or not under the first phase, wherein the first phase is the phase of a first clock signal provided for the memory controller;
the first screening module is used for taking the phase difference between the first phase and a second phase in which the storage module works as a candidate phase difference when the read-write accuracy verification of the storage controller working under the first phase passes, wherein the second phase is the phase of a second clock signal provided for the storage module;
a second screening module for selecting a target phase difference from the candidate phase differences according to a preset rule,
and the second adjusting module is used for adjusting the first phase of the first clock signal of the storage controller so that the storage controller works under the first phase corresponding to the target phase difference.
7. The circuit of claim 6, wherein the verification module comprises:
the write control module is used for controlling the storage controller to write data into any available address of the storage module working under the second phase under the current first phase aiming at the current first phase;
the reading control module is used for controlling the storage controller to read data from the available address of the storage module working in the second phase in the current first phase;
the comparison module is used for comparing whether the data written in the current first phase and the read data in the memory controller are the same or not;
the counting module is used for accumulating verification times of read-write accuracy verification of the storage controller working under the current first phase;
the first circulation module is used for circulating to the write control module to the counting module if the data written in the current first phase by the storage controller is the same as the read data and the accumulated verification times do not reach the preset verification times;
a first ending module, configured to end the read-write verification on the storage controller operating in the current first phase if the data written in the current first phase by the storage controller is the same as the data read out by the storage controller and the accumulated verification times reach the preset verification times;
and the second ending module is used for ending the read-write verification of the storage controller working under the current first phase if the data written into the storage controller under the current first phase is different from the read-out data.
8. The circuit of claim 7, wherein the verification module further comprises:
the phase difference adjusting module is used for scanning the current phase difference according to a scanning window to obtain the next phase difference if the current phase difference between the current first phase and the second phase is not a cut-off phase difference after finishing the verification of the read-write accuracy of the storage controller working under the current first phase;
the third adjusting module is used for obtaining a next first phase according to the sum of the next phase difference and the second phase, and updating the current first phase according to the next first phase; adjusting the phase of the first clock signal according to the updated current first phase, so that the memory controller works in the updated current first phase; (ii) a
A third ending module, configured to end execution of the verification module if a current phase difference between the current first phase and the second phase is a cut-off phase difference after ending verification of read-write accuracy of the memory controller operating in the current first phase.
9. The circuit of claim 7, wherein the first screening module is specifically configured to: when the accumulated verification times reach preset verification times and the data written in and read out by the storage controller are verified to be the same each time, verifying that the reading and writing accuracy of the storage controller working in the first phase passes; and taking the phase difference between the current first phase operated by the storage controller and the second phase operated by the storage module as a candidate phase difference.
10. The circuit of claim 9, wherein the second screening module is specifically configured to: selecting one or more continuous phase difference sequences from the candidate phase differences, wherein the difference between every two adjacent candidate phase differences in the continuous phase difference sequences is a preset scanning window; and selecting the continuous phase difference sequence with the largest number of candidate phase differences, and taking the candidate phase difference with the phase difference as a middle value in the selected continuous phase difference sequence as a target phase difference.
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| CN115862707B (en) * | 2022-11-25 | 2024-03-12 | 湖南兴芯微电子科技有限公司 | PSRAM phase calibration method and controller |
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