CN114443175B - Startup configuration method for missile-borne FPGA (field programmable Gate array) online upgrading - Google Patents
Startup configuration method for missile-borne FPGA (field programmable Gate array) online upgrading Download PDFInfo
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- CN114443175B CN114443175B CN202210370998.9A CN202210370998A CN114443175B CN 114443175 B CN114443175 B CN 114443175B CN 202210370998 A CN202210370998 A CN 202210370998A CN 114443175 B CN114443175 B CN 114443175B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
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- G—PHYSICS
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- G06F8/63—Image based installation; Cloning; Build to order
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
Abstract
The invention provides a starting configuration method for missile-borne FPGA (field programmable gate array) online upgrading, which comprises the following steps of: the upper computer downloading module sends the FPGA configuration file to the FPGA module; the FPGA module writes the FPGA configuration file into a Flash memory; finishing the rapid start configuration of the FPGA configuration file based on a Flash programming algorithm to obtain an upgrade image file and a G image bit stream file; checking the integrity of the upgrade image file based on a CRC32 algorithm; and restarting the missile-borne product to complete configuration. According to the starting configuration method for the missile-borne FPGA online upgrading, the FPGA program can be upgraded online by utilizing the interface of the missile-borne product under the condition that an external interface is not increased, so that the product volume and the cost are greatly reduced; the method is completed without a special downloader, professional software and professionals, is simple to use and maintain and easy to operate, and reduces the risk of test failure; the starting time is short, and the missile-borne data acquisition is not easy to lose.
Description
Technical Field
The invention belongs to the technical field of missile-borne product FPGA starting configuration, and particularly relates to a starting configuration method for online upgrading of a missile-borne FPGA.
Background
With the rapid development of national defense industry, target range test items of missile-borne products are gradually increased, and FPGA programs of the products are frequently upgraded on site. The traditional upgrading of the FPGA program needs to use a downloader to connect with the FPGA through a JTAG interface, and has the following main disadvantages:
the JTAG interface needs TMS, TCK, TDI, TDO, GND and VCC connection points, and when the missile-borne product needs miniaturization, the product cost and the product volume can be increased by leading out the JTAG interface;
a special downloader and professional software are required to be used, and are upgraded by professional personnel, so that the use conditions are harsh, the research and development cost and the maintenance work are increased, and the popularization and the use are not facilitated;
JTAG interfaces are often designed inside products, the products need to be uncovered for processing, reliability cannot be guaranteed when the products are disassembled and assembled, and the risk of test failure is increased.
The remote upgrading of the FPGA can be realized by utilizing the MultiBoot and Fallback characteristics of the FPGA, but the method is relatively complex, the G mirror image cannot be updated, the configuration starting time is more than twice of the standard configuration time, and the loss of key data can be caused by the fact that the missile parameter acquisition time is too long.
Disclosure of Invention
In view of the above, the present invention aims to provide a start configuration method for on-line upgrade of a missile-borne FPGA, so as to solve the problems that the use of JTAG interface contacts for program upgrade of a missile-borne product is too many, the use conditions are harsh, and a fault is easily caused, and also solve the problems that the method using MultiBoot and Fallback features is complex and the configuration time is long.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a startup configuration method for missile-borne FPGA online upgrade comprises the following steps:
s1, the upper computer downloading module calls the bit stream file to be upgraded;
s2, starting a PROMGEN tool to generate a bit stream upgrade file based on the bit stream file in the step S1;
s3, executing Perl script to generate a quick start mirror image based on the bit stream upgrading file in the step S2, and generating a mirror image file needing upgrading;
s4, sending the image file to be upgraded to an FPGA module of the missile-borne product through a transmission channel;
s5, the FPGA module writes the image file to be upgraded to a Flash memory of the missile-borne product;
s6, finishing the rapid start configuration of the image file to be upgraded based on the Flash programming algorithm to obtain an upgraded image file and a G image bit stream file;
s7, checking the integrity of the upgrade image file based on a CRC32 algorithm;
and S8, restarting the missile-borne product, and completing the configuration of the FPGA module.
Further, the FPGA module and the upper computer downloading module in step S5 are connected by an interface cable, and the FPGA module and the Flash memory are communicatively connected to each other.
Further, the transmission channel in step S4 is one of a serial port, a network port, a USB disk, and an SD card.
Further, the image file fast boot configuration requiring upgrading in step S6 includes the following steps:
a1, dividing a Flash memory into three areas, namely a quick start frame header area, a G bit stream mirror image storage area and an upgrade bit stream mirror image storage area, wherein the quick start frame header area comprises a key switch word and a start skip sequence list;
a2, reading from the Flash memory address A0, obtaining the key switch word of the quick start frame header area, and executing the step A3 or the step A4 according to the value of the key switch word;
a3, if the keyword is 'ON', it indicates that the configuration of the upgrade bit stream mirror image is executed, according to the start jump sequence table of the quick start frame header region, jump to the address A1 of the upgrade bit stream mirror image storage region, and then load the bit stream file, to obtain the upgrade mirror image file;
a4, if the key switch word is OFF, indicating to execute the configuration of the G image file, ignoring the start jump sequence table of the quick start frame header region, continuously reading the address data of the Flash memory, and loading the bit stream file from the G bit stream image storage region to obtain the G image bit stream file.
Further, the generation of the upgrade image file in step a3 includes the following steps:
b1, generating a bit stream file of the FPGA module, and distributing the bit stream file in an upgrading area in the Flash memory;
b2, filling the rest part of the upgrading area with null characters;
b3, calculating the complement of CRC32 according to step B1 and step B2, and putting the complement of CRC32 into the last 32 bits of the upgrade area to generate an upgrade image file.
Further, the Flash programming algorithm in step S6 includes the following steps:
c1, erasing the sector containing key switch words in the quick start frame header region;
c2, erasing the area of the image file which needs to be upgraded in the quick start frame header area;
c3, programming the image file to be upgraded to the area of the Flash memory to be upgraded;
c4, confirming that the image file needing to be upgraded is correctly written through a CRC32 algorithm;
and C5, confirming whether the check code of the CRC32 algorithm is correct, if so, programming the key switch word to enable the key switch word to be in an 'ON' state, and if not, failing to program, and exiting.
Further, the checking of the integrity of the upgrade image file based on the CRC32 algorithm in step S7 includes the steps of:
d1, starting a programming logic in the FPGA module to read data in an upgrading area, wherein the data in the upgrading area comprises a CRC32 complement code;
d2, performing CRC32 calculation on the data of the upgrade area and the CRC32 complement code in the upgrade area to obtain a CRC32 calculated value;
d3, judging whether the CRC32 calculated value is matched with a known constant stored in the FPGA module; if yes, confirming that the upgrade image file has integrity; and if not, confirming that the upgrade image file does not have integrity.
Compared with the prior art, the startup configuration method for the missile-borne FPGA online upgrade has the following advantages:
(1) according to the starting configuration method for the missile-borne FPGA online upgrading, the FPGA program can be upgraded online by utilizing the interface of the missile-borne product under the condition that an external interface is not increased, so that the product volume and the cost are greatly reduced; the method is completed without a special downloader, professional software and professionals, is simple to use and maintain and easy to operate, and reduces the risk of test failure; the starting time is short, and the missile-borne data acquisition is not easy to lose.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic diagram illustrating connection of modules in a configuration starting method according to an embodiment of the present invention;
fig. 2 is a schematic block diagram of an implementation of a boot configuration method according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating the generation of an FPGA configuration file according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a configuration for fast starting an image file to be updated according to an embodiment of the present invention;
FIG. 5 is a flow chart of an FPGA of a Flash programming algorithm according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a method for implementing fast start-up online upgrade based on a UART interface according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a state flow of the SpiFlashPro sub-module according to the embodiment of the present invention.
Description of reference numerals:
1. the upper computer downloads the module; 2. a product is missile-borne; 21. an FPGA module; 22. and a Flash memory.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art through specific situations.
The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The noun explains:
FPGA: fpga (field Programmable Gate array) is a product of further development on the basis of Programmable devices such as PAL (Programmable array logic) and GAL (general array logic). The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
A Flash memory: the Flash memory is a Non-Volatile (Non-Volatile) memory, which belongs to a memory device.
PROMGen tool: prommen is a convenient prometheus profile generation tool that can help us generate and manage prometheus profiles, while allowing for the configuration of case alert rules and notification options. Developed based on python.
CRC 32: in the field of data storage and data communication, a crc (cyclic Redundancy check) check utility library has to adopt means for detecting errors in order to ensure the correctness of data. Among many error detection measures, CRC is the most well-known one. The CRC is collectively referred to as a cyclic redundancy check.
Perl: perl, a functionally rich computer programming language, which runs on over 100 computer platforms, is widely used, originally developed for text processing, and is now used for a variety of tasks including system management, Web development, Web programming, GUI development, and the like.
As shown in fig. 1 to 7, a start configuration method for missile-borne FPGA online upgrade includes the following steps:
s1, the upper computer downloading module 1 calls a bit stream file needing to be upgraded;
s2, starting a PROMGEN tool to generate a bit stream upgrade file based on the bit stream file, and proceeding to the step S3;
s3, executing a Perl script to generate a quick start mirror image based on the bit stream upgrading file;
s4, generating an image file to be upgraded after the quick start image is completed;
s5, sending the image file to be upgraded to the FPGA module 21 in the missile-borne product 2 through a transmission channel;
s6, the FPGA module 21 writes the image file to be upgraded to the Flash memory 22;
s7, finishing the rapid start configuration of the image file to be upgraded based on the Flash programming algorithm of the FPGA module 21 to obtain an upgraded image file and a G image bit stream file;
s8, checking the integrity of the upgrade image file based on the CRC32 algorithm;
and S9, restarting the missile-borne product 2, and completing the configuration of the FPGA module 21.
The starting configuration method has the following advantages:
can complete the on-line upgrade of the FPGA program by utilizing the interface of the missile-borne product under the condition of not increasing an external interface, thereby greatly reducing the volume and the cost of the product,
the method is completed without a special downloader, professional software and professionals, is simple to use and maintain and easy to operate, and reduces the risk of failure of the test.
The starting time is short, and the missile-borne data acquisition is not easy to lose.
The method puts the burden of programming error and interrupt recovery on the adjustment of a programming algorithm, and completes the whole solution based on a special configuration header. The method is powerful, compatible with many configuration setting variants and highly reliable.
In this embodiment, this patent mainly comprises host computer download module 1, missile-borne product 2 two parts. The upper computer downloading module 1 is connected with the missile-borne product 2 through an interface cable. As shown in fig. 1.
The generation of the new FPGA configuration file is mainly performed by a developer on site or remotely, and a specific operation flow is shown in fig. 3.
The method comprises the steps of preparing a bit stream file to be upgraded, starting a PROMGen tool, generating a bit stream upgrade file (in a mcs format) to be a normal FPGA module 21 programming operation step, generating a quick start mirror image by a Perl script, generating an initial mcs storage mirror image file and an upgrade mcs mirror image file after the execution is finished, and selecting one of the mirror image files according to the requirement of the initial state of a system or whether the upgrade is required.
The initial mcs storage image file is mainly a complete initial image and mainly comprises the following three parts:
quickly starting a frame header;
a G bitstream file;
upgrading the bitstream file, a copy of the given bitstream file;
the initial mcs memory image file is mainly used for initial programming of the Flash memory 22.
The upgrade mcs image file mainly contains a given bitstream file, and the integrity of this bitstream file is mainly completed by the CRC32 check code.
The FPGA module 21 is connected with the upper computer downloading module 1 through an interface cable, and the FPGA module 21 is in communication connection with the Flash memory 22.
The transmission channel in step S5 is one of a serial port, a network port, a USB disk, and an SD card. In the present embodiment, the kind of the transmission channel is not limited to the above channel.
The image file quick boot configuration requiring the upgrade in step S8 includes the steps of:
a1, dividing a Flash memory into three areas, namely a quick start frame header area, a G bit stream mirror image storage area and an upgrade bit stream mirror image storage area, wherein the quick start frame header area comprises a key switch word and a start skip sequence list;
a2, reading from address A0 of Flash memory 22, obtaining the key switch word of the fast start frame header region, and executing step A3 or step A4 according to the value of the key switch word;
a3, if the keyword is "ON", it indicates that the configuration of the upgrade bit stream mirror image is executed, according to the start jump sequence table of the quick start frame header region, it jumps to the address A1 of the upgrade bit stream mirror image storage region, and then loads the bit stream file to obtain the upgrade mirror image file;
a4, if the key switch word is OFF, indicating to execute the configuration of the G image file, ignoring the start jump sequence table of the quick start frame header region, continuously reading the address data of the Flash memory 22, and loading the bit stream file from the G bit stream image storage region to obtain the G image bit stream file.
The generation of the upgrade image file in step a3 includes the steps of:
b1, generating a bit stream file of the FPGA module 21, and distributing the bit stream file in an upgrading area in the Flash memory 22;
b2, filling the rest part of the upgrading area with null characters;
b3, calculating the complement of CRC32 according to step B1 and step B2, and putting the complement of CRC32 into the last 32 bits of the upgrade area to generate an upgrade image file.
In this embodiment, fig. 4 illustrates a configuration method for performing upgrade quick start of an mcs file (an image file that needs to be upgraded). The configuration method for fast start is to divide the Flash memory 22 into three areas, namely a fast start frame header area, a G bit stream mirror image storage area and an upgrade bit stream mirror image storage area. Wherein, the frame head region of the quick start frame comprises an important switch word and a start jump sequence table.
The key switch word is a key for rapidly starting the configuration method, the key switch word is always in an "ON" or "OFF" state, when the key switch word is in the "ON" state, the FPGA module 21 loads the upgrade image file, and when the key switch word is in the "OFF" state, the FPGA module 21 loads the G image file. The key is a set of specific values and is determined to be in the "ON" state only if the key contains a set of accurate, predetermined values, and the presence or absence of the key determines whether the FPGA module 21 configuration logic is to execute the boot jump sequence.
Value of key switch word
| Configuration modes | BPI Flash starting mode | SPI Flash start mode |
| Value of key switch word | 0x000000BB | 0XAA995566 |
The fast reading starting configuration method comprises the following steps:
step 1, reading from a Flash memory address A0 to obtain a key switch word for quickly starting a frame header. Executing step 2 or step 3 according to the value of the key switch word;
and 2, if the key switch word is 'on', the configuration of upgrading the bit stream image is executed. According to the starting jump sequence of the quick starting frame header, jumping to an address A1 of an upgrading bit stream mirror image storage area, and then loading a bit stream file;
and 3, if the key switch word is OFF, indicating that the configuration of the G image file is executed. And ignoring the starting jump sequence of the quick starting frame header, continuously reading the address data of the Flash memory 21, and loading the bit stream file from the G bit stream mirror image storage area.
The reliability of the method for quickly starting the programming of the Flash memory 21 is mainly determined by the programming process of the upgrading bit stream. The reliability of the Flash memory 21 programming process mainly needs the following conditional measures:
the key must be in the "OFF" state before attempting to edit the updated bitstream file, leaving the key at any value other than "ON".
When the update bit stream is verified to be free of problems, the key switch word can be turned ON and is in an 'ON' state.
To ensure integrity under all conditions, the G-image file and the second part of the fast-start header are not edited under burn-in conditions.
Thus, upgrading the bitstream file of the image file region is performed only when the key switch word is in the "ON" state. The above conditions 1 and 2 ensure that the start skip sequence may not be performed if the upgrade image file region does not contain the correct bitstream file, and the condition 3 ensures that the G image bitstream file can be safely loaded when the key switch word is "OFF".
The Flash programming algorithm in step S7 includes the steps of:
c1, erasing the sector containing key switch words in the quick start frame header region;
c2, erasing the area of the image file which needs to be upgraded in the quick start frame header area;
c3, programming the image file to be upgraded to the area of the Flash memory 22 to be upgraded;
c4, confirming that the image file needing to be upgraded is correctly written through a CRC32 algorithm;
and C5, confirming whether the check code of the CRC32 algorithm is correct, if so, programming the key switch word to enable the key switch word to be in an 'ON' state, and if not, failing to program, and exiting.
Checking the integrity of the upgrade image file based on the CRC32 algorithm in step S8 includes the steps of:
d1, starting a programming logic in the FPGA module 21 to read data in an upgrading area, wherein the data in the upgrading area comprises a CRC32 complement code;
d2, performing CRC32 calculation on the data of the upgrading area and the CRC32 complement code in the data to obtain a CRC32 calculated value;
d3, judging whether the CRC32 calculated value is matched with a known constant stored in the FPGA module 21; if yes, confirming that the upgrade image file has integrity; and if not, confirming that the upgrade image file does not have integrity.
In this embodiment, the algorithm for rapidly starting the Flash programming is mainly completed by the FPGA logic, and the flow of the Flash programming algorithm is as shown in fig. 5.
Programming of the Flash memory 22 requires two operations, first an erase operation to reset the memory data bits to the 1 state, and then a programming operation to change the data bits from the 1 state to the 0 state. Since the modification of the Flash memory 22 requires an erase operation and the erase operation affects the partitioning of the entire Flash memory 22, the partitioning architecture of the Flash memory 22 determines the location of the fast read boot portions in the Flash memory 22. The specific positions are as follows:
firstly, quickly starting a frame header;
the first part of the quick start frame header, namely the key switch word, is positioned in an erasable area, such as a first sector;
a second part of the fast start frame header, which is located after the first part but is not in the same partition as the first part, such as in a second sector;
g image file is positioned behind the frame head of the fast reading starting frame in the memory;
the upgrade image file is located in an erasable area of itself, but does not share an erasable partition with the G-image to avoid destroying the integrity of the G-image file during upgrade operations.
The robustness and reliability of the fast boot configuration scheme depends on whether the fast boot programming reliably detects the authenticity of the upgrade image file. To confirm the correctness of the upgrade image file in Flash memory 22, the integrity of the upgrade image file is confirmed using a CRC32 check. The specific method comprises the following steps:
generating a bit stream file of the FPGA by adopting an FPGA special tool (the prior art);
padding the remainder of the upgrade area with a null character of 0 xFFFFFFFF;
the complement of CRC32 is calculated according to step 1 and step 2.
The upgraded image file is distributed in a fixed area in the Flash memory 22, and according to the partition architecture of the Flash memory 22, for the convenience of erasing and programming, the starting end and the ending end of the boundary of the update area are erasable ends of the distribution area, specifically based on a Flash memory chip manual. When the upgrade image file generates an mcs-formatted file, a CRC32 check calculates the entire upgrade image file except for the last 32 bits, and the calculated CRC32 complement is placed on the last 32 bits of the upgrade region, such that the integrity of the entire upgrade file is protected by the CRC32 check code. To validate the image file programmed into Flash memory 22, the FPGA internal fast boot programming logic reads the data of the entire upgrade area, including the complement of CRC32, and performs a CRC32 calculation. When the CRC32 calculated value matches a known constant, the integrity of the upgrade image file is confirmed to be good.
In this embodiment, the upper computer downloading module 1, the FPGA module 21, and the Flash memory 22 are all the prior art.
Example 1
In practical applications, UART is the most used and most convenient interface protocol. The method can be quickly upgraded and applied on the missile-borne product on line, so that the number of interface contacts can be greatly reduced, and the use and maintenance are convenient. FIG. 6 is a method for implementing rapid start of online upgrade based on UART.
The upper computer sending software module (i.e. the upper computer downloading module 1) mainly sends the upgrade image file to the FPGA module 21 through a serial port, each frame of data is 515 bytes, the first three bytes are frame headers, and the last 512 bytes are upgrade image valid data. After the software starts to load, click the start programming button, and send a start command 0xEB9000 first, until receiving 0xAABB sent by the FPGA module 21, start sending the upgrade image file. After each frame of data is sent, the next frame of data can be sent after the 0 xABB command is received, and the header of each frame of data is 0xEB9001, and the header of the last frame of data is 0xEB 9002.
In this embodiment, mainly include the UART submodule piece, FIFO submodule piece, SpiFlashIn interface submodule piece, SpiFlashPro submodule piece in the FPGA module 21, the UART submodule piece, FIFO submodule piece, SpiFlashIn interface submodule piece, SpiFlashPro submodule piece are prior art, and the UART submodule piece realizes serial ports transmit-receive protocol by the FPGA logic, receives the data that host computer software sent, exports next-level FIFO buffer. After the data of one frame is received, a0 xABB command is sent to indicate that the data is received completely and ready to receive the next frame.
The FIFO submodule mainly realizes the functions of data buffering and bit width conversion of the upgrade image file.
The SpiFlashin interface submodule mainly realizes the function of data interaction between the FPGA module 21 and the Spi Flash memory 22 according to the SPI interface time sequence.
The SpiFlashPro sub-module is mainly used for programming state conversion, realizes quick start of a programming algorithm, and sends instructions and data to the Flash memory 22 and receives data and the like by using the SpiFlashIn sub-module. FIG. 7 is a SpiFlashPro sub-module state flow diagram.
The CRC32 check polynomial is:
G(x) = x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
the constant value is 0xC704DD 7B. Pl tools can be used to generate verilog implementation code for CRC 32.
Based on the principle description and the operation method, the programming of the upgrade image file is quickly started, the FPGA is electrified again, and the G image file or the upgrade image file can be loaded and started according to the state of the key switch word.
The method can be applied according to actual conditions, saves the number of the core wires of the programming interface, can be operated by common personnel, is convenient to maintain and use, reduces the fault risk caused by disassembly, and has high reliability.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (3)
1. A startup configuration method for missile-borne FPGA online upgrade is characterized by comprising the following steps: the method comprises the following steps:
s1, the upper computer downloading module (1) calls a bit stream file needing to be upgraded;
s2, starting a PROMGEN tool to generate a bit stream upgrade file based on the bit stream file in the step S1;
s3, executing a Perl script to generate a quick start mirror image based on the bit stream upgrading file in the step S2, and generating a mirror image file needing to be upgraded;
s4, sending the image file to be upgraded to the FPGA module (21) of the missile-borne product (2) through a transmission channel;
s5, the FPGA module (21) writes the image file to be upgraded to the Flash memory (22) of the missile-borne product (2);
s6, finishing the rapid start configuration of the image file to be upgraded based on the Flash programming algorithm to obtain an upgraded image file and a G image bit stream file;
the image file fast boot configuration requiring upgrade in step S6 includes the following steps:
a1, dividing a Flash memory (22) into three areas, namely a quick start frame header area, a G bit stream mirror image storage area and an upgrade bit stream mirror image storage area, wherein the quick start frame header area comprises a key switch word and a start skip sequence table;
a2, reading from address A0 of Flash memory (22), obtaining the key switch word of the fast start frame header region, and executing step A3 or step A4 according to the value of the key switch word;
a3, if the keyword is "ON", it indicates that the configuration of the upgrade bit stream mirror image is executed, according to the start jump sequence table of the quick start frame header region, it jumps to the address A1 of the upgrade bit stream mirror image storage region, and then loads the bit stream file to obtain the upgrade mirror image file;
a4, if the key switch word is OFF, the configuration of the G image file is executed, the starting jump sequence table of the fast starting frame head area is ignored, the address data of the Flash memory (22) is continuously read, and the bit stream file is loaded from the G bit stream image storage area to obtain the G image bit stream file;
the generation of the upgrade image file in step a3 includes the steps of:
b1, generating a bit stream file of the FPGA module (21), and distributing the bit stream file in an upgrading area in the Flash memory (22);
b2, filling the rest part of the upgrading area with null characters;
b3, calculating the complement of CRC32 according to the step B1 and the step B2, and putting the complement of CRC32 into the last 32 bits of the upgrading area to generate an upgrading image file;
the Flash programming algorithm in step S6 includes the steps of:
c1, erasing the sector containing key switch words in the quick start frame header region;
c2, erasing the area of the image file which needs to be upgraded in the quick start frame header area;
c3, programming the image file to be upgraded to the area of the Flash memory (22) to be upgraded;
c4, confirming that the image file needing to be upgraded is correctly written through a CRC32 algorithm;
c5, confirming whether the check code of the CRC32 algorithm is correct, if so, programming the key switch word to enable the key switch word to be in an ON state, otherwise, not programming successfully, and exiting;
s7, checking the integrity of the upgrade image file based on a CRC32 algorithm;
checking the integrity of the upgrade image file based on the CRC32 algorithm in step S7 includes the steps of:
d1, the FPGA module (21) internally starts the programming logic to read the data of the upgrading area, and the data of the upgrading area comprises CRC32 complement codes;
d2, performing CRC32 calculation on the data of the upgrading area and the CRC32 complement code in the data to obtain a CRC32 calculated value;
d3, judging whether the CRC32 calculated value is matched with a known constant stored in the FPGA module (21) or not; if yes, confirming that the upgrade image file has integrity; if not, confirming that the upgrade image file does not have integrity;
and S8, restarting the missile-borne product (2) and completing the configuration of the FPGA module (21).
2. The startup configuration method for the on-line upgrade of the missile-borne FPGA according to claim 1, characterized in that: in the step S5, the FPGA module (21) is connected to the upper computer download module (1) through an interface cable, and the FPGA module (21) and the Flash memory (22) are in communication connection with each other.
3. The startup configuration method for the on-line upgrade of the missile-borne FPGA according to claim 1, characterized in that: the transmission channel in step S4 is one of a serial port, a network port, a USB disk, and an SD card.
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