CN115862707B - PSRAM phase calibration method and controller - Google Patents
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Abstract
The invention provides a PSRAM phase calibration method and a controller, wherein the controller comprises the following steps: the system comprises a system control module, an interface control module and a phase calibration module, wherein the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing PSRAM protocol and time sequence; the interface control module comprises a read delay chain and a write delay chain; the write delay chain is used for adjusting the delay relation between the write clock and other signals, and the read delay chain is used for adjusting the phase relation between the STROBE signal and DQ; the phase calibration module uses burst read-write command to complete phase calibration by writing specific data into PSRAM device and then reading and comparing, and according to the result, calculating and adjusting the interface control module read delay chain and write delay chain.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a PSRAM phase calibration method and a controller.
Background
Pseudo-static random access memory (Pseudo Static Random Access Memory, i.e., PSRAM) is architecturally a device that is interposed between dynamic random access memory (Dynamic Random Access Memory, DRAM) and static random access memory (Static Random Access Memory, SRAM). Compared with DDR, the IO voltage of the PSRAM is 2.5V which is lower than DDR and the IO driving capability is weak; in contrast to DDR2, PSRAM non-differential STROBE signals have no ODT function and are not sufficient in signal integrity.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Disclosure of Invention
In view of the above technical problems in the related art, the present invention provides a PSRAM controller, which includes: the system comprises a system control module, an interface control module and a phase calibration module, wherein the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing PSRAM protocol and time sequence;
the interface control module comprises a read delay chain and a write delay chain; the write delay chain is used for adjusting the delay relation between the write clock and other signals, and the read delay chain is used for adjusting the phase relation between the STROBE signal and DQ;
the phase calibration module uses burst read-write command to complete phase calibration by writing specific data into PSRAM device and then reading and comparing, and according to the result, calculating and adjusting the interface control module read delay chain and write delay chain.
Specifically, the read delay chain comprises a two-stage delay chain, wherein one-stage delay chain is formed by connecting standard units with balanced rising and falling edge delay in series, fine adjustment is performed through output of a data selector, and the two-stage delay chain is formed by connecting a plurality of one-stage delay chains in series, and coarse adjustment is performed through output of the data selector.
Specifically, the write delay chain is identical to a one-stage delay chain of the read delay chain.
Specifically, the phase calibration module includes: the system comprises a calibration state machine, a delay calculation module, a read-write detection module and a clock generation module; the calibration state machine controls a calibration flow, including an initial calibration flow and a real-time calibration flow; the read-write detection module is used for judging whether the read-write is correct or not by sending specific burst write and read to the system control module and comparing the read data; the delay calculation unit is used for giving out adjustment of the delay chain according to the calibration state and the result of whether the read data are correct or not; the clock generation module is controlled according to the calibration state machine to realize burr-free frequency raising and lowering of the input original clock.
Specifically, the clock generation module includes: an even number frequency divider, a glitch removing selector.
In a second aspect, another embodiment of the present invention provides a PSRAM phase calibration method, including the steps of:
s1, acquiring PSRAM starting, and firstly performing initial reading calibration;
wherein step S1 comprises: s10, configuring a write delay chain by adopting a register default value, and configuring a read delay chain of STROBE and DQ to 0; s11, reducing the frequency of a working clock; s12, writing a specific number into the PSRAM; s13, recovering the clock frequency; s14, reading a specific number from the PSRAM to obtain readback data; s15, comparing the read-back data with a specific number; s16, if the window is correct, finding the minimum value of the read delay chain window, and executing a step S20; s17, otherwise, increasing the phase between the STROBE and DQ by adding a DQ read delay chain; s18, judging whether the maximum value of the read delay chain is reached; s19, if the maximum value of the delay chain is reached, the scanning is illustrated that the value capable of working cannot be found once, and error reporting and exiting are carried out; s20, reducing the frequency of a working clock; s21, writing a specific number into the PSRAM; s22, recovering the clock frequency; s23, reading a specific number from the PSRAM to obtain readback data; s24, comparing the read-back data with a specific number, S25, if the read-back data is wrong, finding the maximum value of a read delay chain window, and executing a step S28; s26, otherwise, increasing the phase between the STROBE and DQ by adding a DQ read delay chain; s27, judging whether the maximum value of the read delay chain is reached, if so, finding the maximum value of the window of the read delay chain; s28, averaging the minimum value and the maximum value of the window to obtain a calibration value of the read delay chain;
s3, performing initial write calibration;
wherein step S3 comprises: s31, configuring a clock write delay chain to be half of the length of the delay chain, and configuring a signal write delay chain to be 0; s32, writing a specific number into the PSRAM; specific sending write commands write specific numbers into the PSRAM, wherein the specific writing mode is the same as that in the step S1; s33, reading a specific number from the PSRAM to obtain readback data; s34, comparing the read-back data with a specific number, S35, if the read-back data is correct, finding the minimum value of a write delay chain window, and executing S38; s36, otherwise, adding a signal writing delay chain, S37, judging whether the maximum value of the delay chain is reached, if so, exceeding the speed, and carrying out error reporting and exiting; s38, writing a specific number into the PSRAM; s39, reading a specific number from the PSRAM to obtain readback data; s40, comparing the read-back data with a specific number, S41, and if the error occurs, finding the maximum value of the write delay chain window; s42, if the signal writing delay chain is correct, adding the signal writing delay chain; s43, judging whether the maximum value of the delay chain is reached, if so, finding the maximum value of the read delay chain window; s44, averaging the minimum value and the maximum value of the window to obtain a calibration value of the write delay chain;
s5, the calibration value of the read delay chain and the calibration value of the write delay chain are respectively applied to the read delay chain and the write delay chain.
Specifically, the method further comprises the following steps: s3', real-time reading and calibration, specifically: s31', reducing the frequency of a working clock; s32', writing a specific number into the PSRAM; s33', recovering the clock frequency; s34', reading a specific number from the PSRAM to obtain readback data; s35', comparing the read-back data with a specific number, S36', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s37', if wrong, reducing DQ read delay chain; s38', judging whether the DQ read delay chain is smaller than a set range, and if so, recovering the original value of the DQ read delay chain; and performs steps S31'-34'; s391', comparing the read-back data with a specific number, S392', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s393', if wrong, adding DQ read delay chain; s394', judge DQ reads the delay chain to be greater than presuming the scope, S395', if yes, calibrate and fail.
Specifically, the method further comprises the following steps: s4', real-time writing calibration is specifically as follows: s41', writing a specific number into the PSRAM; a specific sending write command writes a specific number into the PSRAM; s42', reading a specific number from the PSRAM to obtain readback data; s43', comparing the read-back data with a specific number, S44', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s45', otherwise, reducing the signal writing delay chain, S46', judging whether the signal writing delay chain is smaller than a set range, S47', if so, recovering the original value of the signal writing delay chain, and executing the steps S41' -S43'; s48', if the delay chain is correct, the delay chain keeps the current value, and the calibration is completed; s49', otherwise, the signal write delay chain is added, S491', and it is judged whether the signal write delay chain is larger than the set range, S492', if so, the calibration fails.
Specifically, the DQ read delay chain is reduced, the DQ read delay chain is increased, the signal write delay chain is reduced, and the signal write delay chain is increased by 1.
According to the PSRAM phase calibration method and the controller, the accuracy of the delay chain is improved through the calibration flow control and the calibration algorithm, and the highest speed of communication with PSRAM equipment is improved. Meanwhile, the invention discloses real-time calibration for compensating equipment delay drift and delay chain drift caused by voltage and temperature in the working process of the chip.
1) The initial reading calibration and the writing calibration are realized, and the reading and writing delay chains are ensured to work at the optimal phase;
2) The initial reading calibration adopts dichotomy acceleration, so that the application waiting time is reduced;
3) And when the device is idle in real time, real-time fine adjustment and calibration are carried out, the influence of phase drift caused by voltage and temperature is compensated, and the stability is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a PSRAM controller provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of STROBE and DQ phases in a read timing sequence according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a read delay chain provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a PSRAM burst write clock and data phase provided by an embodiment of the present invention;
FIG. 5 is a schematic diagram of an overall flow of PSRAM phase calibration provided by an embodiment of the present invention;
FIG. 6 is a schematic diagram of an initial read calibration provided by an embodiment of the present invention;
FIG. 7 is a schematic diagram of an initial write calibration provided by an embodiment of the present invention;
FIG. 8 is a schematic diagram of real-time read calibration provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of real-time write calibration provided by an embodiment of the present invention;
FIG. 10 is a schematic diagram of a read-write detection module and a clock generation module according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a read-write state machine according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a deburring state control provided by an embodiment of the present invention;
FIG. 13 is a schematic diagram of initial read calibration scan minimum dichotomy provided by an embodiment of the invention;
FIG. 14 is a schematic diagram of initial read calibration scan maximum dichotomy provided by an embodiment of the invention;
fig. 15 is a schematic diagram of a calibration state machine according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.
Example 1
Referring to fig. 1, the present embodiment discloses a PSRAM controller, which includes a phase calibration module, a system control module, and an interface control module, wherein the interface control module includes a read delay chain and a write delay chain; the phase calibration module comprises a calibration state machine, a clock generation module, a delay calculation unit and a read-write detection module; the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing PSRAM protocol and time sequence; the write delay chain is used for adjusting the delay relation between a write clock and other signals, and the read delay chain is used for adjusting the phase relation between a STROBE signal and DQ; the phase calibration module uses burst read-write command to write specific data into PSRAM device and then reads and compares the data, and adjusts the delay chain of the interface control module according to the result calculation to complete the phase calibration process.
The phase calibration module is matched with the system control module and the interface control module to complete phase calibration. In fig. 1, the system control module controls the state of the whole PSRAM controller, and supports the functions of power-on initialization flow, reset mode, sleep mode and the like of various PSRAM devices. The interface control module is mainly used for realizing PSRAM protocol and time sequence. The interface state machine receives PSRAM commands, addresses, data and the like provided by the system control module and sends the PSRAM commands, addresses, data and the like according to the time sequence required by PSRAM equipment. The write delay chain is used to adjust the delay relationship between the write clock and other signals, and the read delay chain is used to adjust the phase relationship between the STROBE signal and the DQ.
The phase calibration module uses burst read-write command to write specific data into PSRAM device and then reads and compares the data, and adjusts the delay chain of the interface control module according to the result calculation to complete the phase calibration process. The burst read-write command and data of the phase calibration module are forwarded to the interface control module through the system control module, and the calculated delay result is sent to a delay chain in the interface control module. The phase calibration module is internally provided with four modules: the system comprises a calibration state machine, a delay calculation module, a read-write detection module and a clock generation module. The calibration state machine controls a calibration flow, including an initial calibration flow and a real-time calibration flow; the read-write detection module is used for judging whether the read-write is correct or not by sending specific burst write and read to the system control module and comparing the read data; the delay calculation module internally realizes a delay chain rapid calibration algorithm, and determines the next adjustment direction according to the calibration state and the read-write result; the clock generation module is controlled according to the calibration state machine to realize burr-free frequency raising and lowering of the input original clock.
As shown in FIG. 2, the STROBE and DQ signals are in phase relationship in the read sequence according to the protocol requirements of PSRAM. Although different PSRAM devices differ slightly in timing of STOBE and DQ, the phase relationship between the STOBE and DQ via the board level trace and the on-chip trace cannot be guaranteed, and thus a sufficient sampling window for STORBE sampling DQ cannot be guaranteed. Therefore, it is necessary to adjust the phase between the two using a read delay chain, and in order to ensure that the setup and hold margins of the STROBE and DQ are sufficient at high speeds, it is generally desirable to adjust both to 90 degrees. As shown in fig. 3, in order that the PSRAM controller can correctly sample data at high speed, a two-stage delay chain is designed in the read delay chain. The primary delay chain is formed by serially connecting standard units with balanced rising and falling edge delays, and the fine adjustment effect is achieved through the output of the data selector. The second-stage delay chain is formed by connecting a plurality of first-stage delay chains in series, and achieves a rough adjustment effect through the output of the data selector. As shown in fig. 4, the protocol according to PSRAM requires that the clock and data in the burst write clock be 90 degrees phase, and that there be a sufficient sampling window for the data to be used with the clock signal after reaching the PSRAM device. Therefore, the write delay chain and the first-stage chain in the read delay chain adopt the same structure, and the calibration module ensures that the clock and the data still keep 90-degree phase when being sent to the IO of the chip through fine adjustment delay.
According to the time sequence of the read-write command and the characteristics of the read-write delay chain, initial calibration and real-time calibration are designed in the embodiment. The initial calibration ensures that the read-write delay chain is optimally configured before normal functions run, and the time sequence allowance between the read-write clock and the sampling signal is maximum. The real-time calibration is used for fine tuning the delay chain to offset time sequence changes caused by voltage and temperature fluctuations when the operation is idle. Because the write timing phase remains substantially 90 degrees, only fine-tuning is needed and the read phase needs to be adjusted from 0, the read calibration is performed first to ensure that the read is normal and then the write calibration is performed. As shown in fig. 5, the initial read calibration is performed first after the start-up, then the initial write calibration is performed, and then a waiting state is entered. The real-time calibration is an optional item, is suitable for the application of PSRAM equipment which is not in full load operation, and the chip main system informs the system to start the real-time calibration, and performs reading calibration and writing calibration. In order to ensure that the reading calibration can be performed correctly, the data is written at a low speed in a mode of reducing the frequency of a writing clock in the reading calibration, the correctness of the written data is ensured, and then the reading operation is performed at the original frequency. The detailed flow of each calibration is as follows:
as in fig. 6, the write delay chain will first be configured with register defaults, then the read delay chains for STROBE and DQ will be configured to 0. Then, the clock frequency is reduced, the data is written, the clock frequency is recovered, and the data is read, and the process of reducing the frequency is called reducing the writing and recovering the reading. Comparing the read-back data, and if the comparison result is correct, finding the minimum value of the read delay chain window; otherwise, the phase between STROBE and DQ is increased by adding DQ read delay chain. If the maximum value of the delay chain is reached, the scanning is performed once, and no working value is found, so that error reporting and exiting are performed. After finding the minimum value of the read delay chain window, the process of the down-conversion writing recovery reading is continued. When the first read/write error is found or the delay chain reaches a maximum value, the maximum value of the window is found. Finally, the window minimum and maximum values are averaged and applied as calibration values for the read delay chain.
As in fig. 7, the flow of initial write calibration is similar to the initial read calibration. Because the read calibration has been completed, the down-conversion write is not required to resume the read process. The first step sets the write delay chain of the clock to half to configure the signal write delay chain to 0, ready to scan the delay chain from 0 to maximum. After the minimum and maximum values of the delay chain window are found in sequence, the average value of the minimum and maximum values is used as the calibration value of the final data write delay chain.
The real-time calibration only performs fine tuning, and searches for a proper delay chain value in a range of delay chains that are reduced and increased. First, a scan is made in a reduced direction to find the correct delay for reading and writing. When the reading and writing are not correct after the reading and writing are reduced to a certain value, the direction is changed to the increasing direction for scanning. If a certain value is increased and correct delay of reading cannot be found, the fact that the delay chain is invalid due to external conditions is indicated, and error reporting and exiting are needed. As in fig. 8, the real-time read calibration first performs the process of down-conversion write recovery read. Then comparing the data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, the DQ read delay chain is reduced, and then the down-conversion write recovery read process is performed. If the DQ read delay chain is smaller than the set range, the value before the DQ read delay chain is calibrated in real time is recovered, and then the down-conversion writing recovery reading process is carried out. Continuously comparing the read data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, a DQ read delay chain is added, and the down-conversion writing recovery reading process is repeated. Finally, if the DQ read delay chain is larger than the set range, the calibration fails, otherwise, the value when the read and write are correct is applied to the delay chain.
As in fig. 9, the real-time write calibration first performs a write-read process. Then comparing the read data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, the signal writing delay chain is reduced, and then the writing and reading processes are performed. If the signal writing delay chain is smaller than the set range, the value before the signal writing chain is calibrated in real time is recovered, and then the writing and reading processes are carried out. Continuously comparing the read data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, a signal write delay chain is added, and the write-read process is repeated. Finally, if the signal writing delay chain is larger than the set range, the calibration fails, otherwise, the value when the reading and writing are correct is applied to the delay chain.
The four calibration processes are all processes of comparing the write data with the read data, and the processes are realized by a read-write detection module and a clock generation module. As shown in fig. 10, there are four sub-modules inside: write data, read data, database and read-write state machine. Wherein the state machine controls the clock selection signal of the clock generation module.
In the read-write detection module, the write data module is responsible for generating write data commands, addresses, lengths and requests, and the write data commands, the addresses, the lengths and the requests are transmitted to the interface control module through the system control module to generate write time sequences. The data written to the data module is retrieved from the database by the register configuration, typically with a random number and a 01 data string. Wherein, the 01 data string is a data sequence of 8 bits 0 in odd cycle and 8 bits 1 in even cycle, and the 01 data string is sent to enable each data bit in adjacent cycles of the PSRAM to be flipped. The read data module is responsible for generating read data commands, addresses, lengths and requests, and transmitting the read data commands, addresses, lengths and requests to the interface control module through the system control module to generate burst read time sequences. After the data is read back from the PSRAM device, the read data module compares the returned data with the data in the database one by one to give a correct and error signal.
As shown in fig. 11, the read-write state machine is optionally completed by calibrating the signals of the state machine as follows: clock down- > write data- > clock recovery- > read data or write data- > read data. And the clock source of the clock generation module is controlled by the output selection signal in the clock down-conversion and clock recovery states. The clock generation module includes an even divider and a glitch-removing selector. Because only the effect of reducing the frequency needs to be accomplished in the design, an even division is employed in the divider to simplify the design. The frequency division coefficient of 2,4,6 and 8 times is selected through the register configuration, and the frequency division is realized through the counter. A glitch is generated on the clock line when the divided clock and the original clock are switched, and a glitch removal circuit is provided in the clock selector for the purpose of removing the glitch. As in fig. 12, the following state control is adopted, in which the selector output is turned off first and then the clock source is switched when the clock selection signal is changed. At this time, since the glitch caused by switching the clock is not output, the output glitch is eliminated. After switching, a period of time is required to wait for the selector to output a new clock after the output is turned on.
The delay calculation module is used for providing adjustment of the delay chain according to the different states of the four calibration states and the result of whether the read data are correct or not. In real-time calibration, only fine tuning is needed for the delay chain, so that only + -1 delay chain is needed after each judgment result. In the initialization write calibration, since the transmission delay chain is short, the delay chain is scanned by +1 after each judgment result. For the read delay chain, the delay chain is therefore split into two stages and is relatively long, so a dichotomy implementation is employed.
Referring to fig. 6 and 13, specifically, the adding DQ read delay chain uses the initial read calibration scan minimum bisection method. And after the start, performing the down-conversion writing recovery reading flow, if the comparison result is wrong, indicating that the delay chain is insufficient, adding a second-stage delay chain, and repeating the down-conversion writing recovery reading until the comparison result is correct. And if the comparison result is correct, the value of the scanning chain is shown in the current primary chain, the secondary delay chain is reduced by one, the primary delay chain value is configured to be half of the maximum value, and the adjustment quantity is configured to be 1/4 of the maximum value. Then, continuing to perform down-conversion writing and recovery reading, if the comparison result is wrong, the primary delay chain is the delay chain of the last writing and reading+the adjustment quantity of the last writing and reading, and simultaneously halving the adjustment quantity; if the comparison result is correct, the first-stage delay chain is the last write-read delay chain-last write-read adjustment quantity, and the adjustment quantity is halved. And circulating until the adjustment quantity is smaller than 2, and finding the optimal first-stage delay chain value.
Referring to fig. 14, the initial read calibration scan maximum dichotomy flow is similar to the minimum lookup flow. The difference is that when the secondary delay chain is adjusted, if the writing and reading processes are correct, the secondary delay chain is added until the first time of writing and reading result errors are found, namely the boundary of the maximum delay chain; the delay chain is added when the write-read process is correct when the first-stage delay chain is found by two halves.
As shown in fig. 15, the calibration state machine is as follows, after the initialization starts, the initial read calibration is performed first, the initial write calibration is performed again, and then the completion state is entered. In the completion state, waiting for a real-time calibration command, and after receiving the command, performing real-time reading calibration and then performing real-time writing calibration. The calibration state machine outputs current state signals to the other three modules for calibration of different delay chains and different modes.
The PSRAM controller of the embodiment improves the accuracy of the delay chain through the calibration flow control and the calibration algorithm, and improves the highest speed of communication with the PSRAM device. Meanwhile, the implementation can also perform real-time calibration, and is used for compensating equipment delay drift and delay chain drift caused by voltage and temperature in the working process of the chip.
1) The initial reading calibration and the writing calibration are realized, and the reading and writing delay chains are ensured to work at the optimal phase;
2) The initial reading calibration adopts dichotomy acceleration, so that the application waiting time is reduced;
3) And when the device is idle in real time, real-time fine adjustment and calibration are carried out, the influence of phase drift caused by voltage and temperature is compensated, and the stability is improved.
Example two
The embodiment discloses a PSRAM phase calibration method, which comprises the following steps:
s1, acquiring PSRAM starting, and firstly performing initial reading calibration;
referring to fig. 6, step S1 includes: s10, configuring a write delay chain by adopting a register default value, and configuring a read delay chain of STROBE and DQ to 0; s11, reducing the frequency of a working clock; s12, writing a specific number into the PSRAM; specifically, the specific number may be fixed data set in advance by sending a write command to the PSRAM, and the address may be sent together with fixed data set in advance when writing into the PSRAM, for example, the address may be dynamically allocated or fixed address set in advance. S13, recovering the clock frequency; the recovered clock frequency of the present embodiment means that it is recovered to the high-speed operation clock, that is, the operation clock frequency before the operation clock frequency is lowered. S14, reading a specific number from the PSRAM to obtain readback data (S11-S14 are hereinafter referred to as a process of reducing frequency writing and recovering reading); specifically, a read command is sent to read a specific number from the PSRAM; s15, comparing the read-back data with a specific number, S16, if the read-back data is correct, finding the minimum value of a read delay chain window, and executing a step S20; s17, otherwise, increasing the phase between the STROBE and DQ by adding a DQ read delay chain; s18, judging whether the read delay chain maximum value is reached, S19, if the read delay chain maximum value is reached, indicating that the scanning is performed once, and if the scanning is performed once, no operable value is found, and performing error reporting and exiting. S20, reducing the frequency of a working clock; s21, writing a specific number into the PSRAM; s22, recovering the clock frequency; s23, reading a specific number from the PSRAM to obtain readback data; s24, comparing the read-back data with a specific number, S25, if the read-back data is wrong, finding the maximum value of a read delay chain window, and executing a step S28; s26, otherwise, increasing the phase between the STROBE and DQ by adding a DQ read delay chain; s27, judging whether the maximum value of the read delay chain is reached, if so, finding the maximum value of the window of the read delay chain; s28, averaging the minimum value and the maximum value of the window to obtain a calibration value of the read delay chain;
the present embodiment continues the down-conversion write recovery read process after finding the minimum value of the read delay chain window. When the first read/write error is found or the delay chain reaches a maximum value, the maximum value of the window is found. Finally, the window minimum and maximum values are averaged and applied as calibration values for the read delay chain.
S3, performing initial write calibration;
wherein step S3 comprises: s31, configuring a clock write delay chain to be half of the length of the delay chain, and configuring a signal write delay chain to be 0; specifically, the delay chain length in the embodiment is changed according to the design requirement, but if a certain circuit is designed, the delay chain length is unchanged; the present embodiment may configure the clock write delay chain to half the write delay chain length; s32, writing a specific number into the PSRAM; specific sending write commands write specific numbers into the PSRAM, wherein the specific writing mode is the same as that in the step S1; s33, reading a specific number from the PSRAM to obtain readback data; s34, comparing the read-back data with a specific number, S35, if the read-back data is correct, finding the minimum value of a write delay chain window, and executing S38; s36, otherwise, adding a signal writing delay chain, S37, judging whether the maximum value of the delay chain is reached, if so, exceeding the speed, and carrying out error reporting and exiting; the maximum delay chain value in this embodiment refers to the length of the delay chain in circuit design; therefore, after the delay chain maximum is reached, the delay chain will not be adjusted. The delay chain maximum value is the same as the following. S38, writing a specific number into the PSRAM; s39, reading a specific number from the PSRAM to obtain readback data; s40, comparing the read-back data with a specific number, S41, and if the error occurs, finding the maximum value of the write delay chain window; s42, if the signal writing delay chain is correct, adding the signal writing delay chain; s43, judging whether the maximum value of the delay chain is reached, if so, finding the maximum value of the read delay chain window;
the flow of initial write calibration of this embodiment is similar to initial read calibration. Because the read calibration has been completed, the down-conversion write is not required to resume the read process. The first step sets the write delay chain of the clock to half to configure the signal write delay chain to 0, ready to scan the delay chain from 0 to maximum. After the minimum and maximum values of the delay chain window are found in sequence, the average value of the minimum and maximum values is used as the calibration value of the final data write delay chain.
Referring to fig. 8, further, the PSRAM phase calibration method of the present embodiment further includes: s3', real-time reading and calibration, specifically: s31', reducing the frequency of a working clock; s32', writing a specific number into the PSRAM; s33', recovering the clock frequency; s34', reading a specific number from the PSRAM to obtain readback data; s35', comparing the read-back data with a specific number, S36', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s37', if wrong, reducing DQ read delay chain; s38', judging whether the DQ read delay chain is smaller than a set range, and if so, recovering the original value of the DQ read delay chain; and performs steps S31'-34'; s391', comparing the read-back data with a specific number, S392', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s393', if wrong, adding DQ read delay chain; s394', judge DQ reads the delay chain to be greater than presuming the scope, S395', if yes, calibrate and fail.
The real-time read calibration of this embodiment first performs the down-conversion write recovery read process. Then comparing the data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, the DQ read delay chain is reduced, and then the down-conversion write recovery read process is performed. If the DQ read delay chain is smaller than the set range, the value before the DQ read delay chain is calibrated in real time is recovered, and then the down-conversion writing recovery reading process is carried out. Continuously comparing the read data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, a DQ read delay chain is added, and the down-conversion writing recovery reading process is repeated. Finally, if the DQ read delay chain is larger than the set range, the calibration fails, otherwise, the value when the read and write are correct is applied to the delay chain.
Referring to fig. 9, the present embodiment further includes: s4', real-time writing calibration is specifically as follows: s41', writing a specific number into the PSRAM; specific sending write commands write specific numbers into the PSRAM, wherein the specific writing mode is the same as that in the step S1; s42', reading a specific number from the PSRAM to obtain readback data; s43', comparing the read-back data with a specific number, S44', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s45', otherwise, reducing the signal writing delay chain, S46', judging whether the signal writing delay chain is smaller than a set range, S47', if so, recovering the original value of the signal writing delay chain, and executing the steps S41' -S43'; s48', if the delay chain is correct, the delay chain keeps the current value, and the calibration is completed; s49', otherwise, the signal write delay chain is added, S491', and it is judged whether the signal write delay chain is larger than the set range, S492', if so, the calibration fails.
The real-time write calibration of the present embodiment first performs a write-read process. Then comparing the read data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, the signal writing delay chain is reduced, and then the writing and reading processes are performed. If the signal writing delay chain is smaller than the set range, the value before the signal writing chain is calibrated in real time is recovered, and then the writing and reading processes are carried out. Continuously comparing the read data, if the comparison result is correct, finding out a proper delay value, and completing calibration; if the comparison is wrong, a signal write delay chain is added, and the write-read process is repeated. Finally, if the signal writing delay chain is larger than the set range, the calibration fails, otherwise, the value when the reading and writing are correct is applied to the delay chain.
The real-time calibration of this embodiment only fine-tunes to find out if there is a suitable delay chain value in the reduced and increased range of delay chains. First, a scan is made in a reduced direction to find the correct delay for reading and writing. When the reading and writing are not correct after the reading and writing are reduced to a certain value, the direction is changed to the increasing direction for scanning. If a certain value is increased and correct delay of reading cannot be found, the fact that the delay chain is invalid due to external conditions is indicated, and error reporting and exiting are needed.
In real-time calibration, only fine tuning is needed for the delay chain, so that only + -1 delay chain is needed after each judgment result. In the initialization write calibration, since the transmission delay chain is short, the delay chain is scanned by +1 after each judgment result. For the read delay chain, the delay chain is therefore split into two stages and is relatively long, so a dichotomy implementation is employed.
Fig. 13 is a flow of initial read calibration scan minimum dichotomy. And after the start, performing the down-conversion writing recovery reading flow, if the comparison result is wrong, indicating that the delay chain is insufficient, adding a second-stage delay chain, and repeating the down-conversion writing recovery reading until the comparison result is correct. And if the comparison result is correct, the value of the scanning chain is shown in the current primary chain, the secondary delay chain is reduced by one, the primary delay chain value is configured to be half of the maximum value, and the adjustment quantity is configured to be 1/4 of the maximum value. Then, continuing to perform down-conversion writing and recovery reading, if the comparison result is wrong, the primary delay chain is the delay chain of the last writing and reading+the adjustment quantity of the last writing and reading, and simultaneously halving the adjustment quantity; if the comparison result is correct, the first-stage delay chain is the last write-read delay chain-last write-read adjustment quantity, and the adjustment quantity is halved. And circulating until the adjustment quantity is smaller than 2, and finding the optimal first-stage delay chain value.
The PSRAM phase calibration method of the embodiment improves the accuracy of the delay chain through the calibration flow control and the calibration algorithm, and improves the highest speed of communication with PSRAM equipment. Meanwhile, the implementation can also perform real-time calibration, and is used for compensating equipment delay drift and delay chain drift caused by voltage and temperature in the working process of the chip.
1) The initial reading calibration and the writing calibration are realized, and the reading and writing delay chains are ensured to work at the optimal phase;
2) The initial reading calibration adopts dichotomy acceleration, so that the application waiting time is reduced;
3) And when the device is idle in real time, real-time fine adjustment and calibration are carried out, the influence of phase drift caused by voltage and temperature is compensated, and the stability is improved.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (9)
1. A PSRAM controller, comprising: the system comprises a system control module, an interface control module and a phase calibration module, wherein the system control module is used for controlling the state of the PSRAM controller; the interface control module is used for realizing PSRAM protocol and time sequence;
the method is characterized in that: the interface control module comprises a read delay chain and a write delay chain; the write delay chain is used for adjusting the delay relation between the write clock and other signals, and the read delay chain is used for adjusting the phase relation between the STROBE signal and DQ; the reading delay chain comprises a two-stage delay chain, wherein one-stage delay chain is formed by connecting standard units with balanced rising and falling edge delay in series, fine adjustment is performed through the output of a data selector, and the two-stage delay chain is formed by connecting a plurality of one-stage delay chains in series, and coarse adjustment is performed through the output of the data selector;
the phase calibration module uses burst read-write command to complete phase calibration by writing specific data into PSRAM device and then reading and comparing, and according to the result, calculating and adjusting the interface control module read delay chain and write delay chain.
2. The PSRAM controller of claim 1, wherein the write delay chain is identical to a one-stage delay chain of the read delay chain.
3. The PSRAM controller of claim 2, wherein the phase calibration module comprises: the system comprises a calibration state machine, a delay calculation module, a read-write detection module and a clock generation module; the calibration state machine controls a calibration flow, including an initial calibration flow and a real-time calibration flow; the read-write detection module is used for judging whether the read-write is correct or not by sending specific burst write and read to the system control module and comparing the read data; the delay calculation unit is used for giving out adjustment of the delay chain according to the calibration state and the result of whether the read data are correct or not; the clock generation module is controlled according to the calibration state machine to realize burr-free frequency raising and lowering of the input original clock.
4. A PSRAM controller according to claim 3, wherein the clock generation module comprises: an even number frequency divider, a glitch removing selector.
5. A method for phase calibration of a PSRAM, comprising the steps of:
s1, acquiring PSRAM starting, and firstly performing initial reading calibration;
wherein step S1 comprises: s10, configuring a write delay chain by adopting a register default value, and configuring a read delay chain of STROBE and DQ to 0; s11, reducing the frequency of a working clock; s12, writing a specific number into the PSRAM; s13, recovering the clock frequency; s14, reading a specific number from the PSRAM to obtain readback data; s15, comparing the read-back data with a specific number; s16, if the window is correct, finding the minimum value of the read delay chain window, and executing a step S20; s17, otherwise, increasing the phase between the STROBE and DQ by adding a DQ read delay chain; s18, judging whether the maximum value of the read delay chain is reached; s19, if the maximum value of the delay chain is reached, the scanning is illustrated that the value capable of working cannot be found once, and error reporting and exiting are carried out; s20, reducing the frequency of a working clock; s21, writing a specific number into the PSRAM; s22, recovering the clock frequency; s23, reading a specific number from the PSRAM to obtain readback data; s24, comparing the read-back data with a specific number, S25, if the read-back data is wrong, finding the maximum value of a read delay chain window, and executing a step S28; s26, otherwise, increasing the phase between the STROBE and DQ by adding a DQ read delay chain; s27, judging whether the maximum value of the read delay chain is reached, if so, finding the maximum value of the window of the read delay chain; s28, averaging the minimum value and the maximum value of the window to obtain a calibration value of the read delay chain;
s3, performing initial write calibration;
wherein step S3 comprises: s31, configuring a clock write delay chain to be half of the length of the delay chain, and configuring a signal write delay chain to be 0; s32, writing a specific number into the PSRAM; specific sending write commands write specific numbers into the PSRAM, wherein the specific writing mode is the same as that in the step S1; s33, reading a specific number from the PSRAM to obtain readback data; s34, comparing the read-back data with a specific number, S35, if the read-back data is correct, finding the minimum value of a write delay chain window, and executing S38; s36, otherwise, adding a signal writing delay chain, S37, judging whether the maximum value of the delay chain is reached, if so, exceeding the speed, and carrying out error reporting and exiting; s38, writing a specific number into the PSRAM; s39, reading a specific number from the PSRAM to obtain readback data; s40, comparing the read-back data with a specific number, S41, and if the error occurs, finding the maximum value of the write delay chain window; s42, if the signal writing delay chain is correct, adding the signal writing delay chain; s43, judging whether the maximum value of the delay chain is reached, if so, finding the maximum value of the read delay chain window; s44, averaging the minimum value and the maximum value of the window to obtain a calibration value of the write delay chain;
s5, the calibration value of the read delay chain and the calibration value of the write delay chain are respectively applied to the read delay chain and the write delay chain.
6. The method of claim 5, wherein the method further comprises: s3', real-time reading and calibration, specifically: s31', reducing the frequency of a working clock; s32', writing a specific number into the PSRAM; s33', recovering the clock frequency; s34', reading a specific number from the PSRAM to obtain readback data; s35', comparing the read-back data with a specific number, S36', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s37', if wrong, reducing DQ read delay chain; s38', judging whether the DQ read delay chain is smaller than a set range, and if so, recovering the original value of the DQ read delay chain; and executing the steps S31'-34', S391', comparing the read-back data with a specific number, S392', if the read-back data is correct, keeping the current value of the delay chain, and completing the calibration; s393', if wrong, adding DQ read delay chain; s394', judge DQ reads the delay chain to be greater than presuming the scope, S395', if yes, calibrate and fail.
7. The method of claim 5, wherein the method further comprises: s4', real-time writing calibration is specifically as follows: s41', writing a specific number into the PSRAM; a specific sending write command writes a specific number into the PSRAM; s42', reading a specific number from the PSRAM to obtain readback data; s43', comparing the read-back data with a specific number, S44', if the read-back data is correct, keeping the current value of the delay chain, and completing calibration; s45', otherwise, reducing the signal writing delay chain, S46', judging whether the signal writing delay chain is smaller than a set range, S47', if so, recovering the original value of the signal writing delay chain, and executing the steps S41' -S43'; s48', if the delay chain is correct, the delay chain keeps the current value, and the calibration is completed; s49', otherwise, the signal write delay chain is added, S491', and it is judged whether the signal write delay chain is larger than the set range, S492', if so, the calibration fails.
8. The method of claim 6, wherein the decreasing DQ read delay chain and the increasing DQ read delay chain are decreasing or increasing by 1.
9. The method of claim 7, wherein the decrease signal write delay chain and the increase signal write delay chain are decreased or increased by 1.
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