CN103050146A - High-duty-ratio DDR2 (double data rate) digital delay chain circuit - Google Patents

High-duty-ratio DDR2 (double data rate) digital delay chain circuit Download PDF

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CN103050146A
CN103050146A CN2013100100306A CN201310010030A CN103050146A CN 103050146 A CN103050146 A CN 103050146A CN 2013100100306 A CN2013100100306 A CN 2013100100306A CN 201310010030 A CN201310010030 A CN 201310010030A CN 103050146 A CN103050146 A CN 103050146A
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digital delay
port
stages
clock
selector
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CN103050146B (en
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吕新浩
孙翼
高鹏
马涛
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KUNSHAN HUINING ELECTRIC CO Ltd
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KUNSHAN HUINING ELECTRIC CO Ltd
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Abstract

The invention discloses a high-duty-ratio DDR2 digital delay chain circuit. The high-duty-ratio DDR2 digital delay chain circuit comprises a digital delay unit, a write operation clock digital delay chain, and a read-write operation DQS (data strobe signal) digital delay chain, wherein the digital delay unit consists of a clock inverter and a clock selector; and both of the write operation clock digital delay chain and the read-write operation DQS digital delay chain consist of digital delay units in series connection. The high-duty-ratio DDR2 digital delay chain circuit provided by the invention is realized by selecting a full digital circuit so as not to depend on the chip manufacture process, and can realize high-duty-ratio DDR2 write clock and DQS signals, thereby improving the stability and work frequency of DDR2.

Description

High duty ratio DDR2 digital delay chain circuit
Technical field
The present invention relates to high duty ratio DDR2 digital delay chain circuit, belong to high speed DDR, DDR2, DDR3 Design of Digital Circuit field.
Background technology
Along with the development of integrated circuit and the continuous renewal of technology, the clock frequency of chip improves constantly, the continuous increase of chip data handling capacity, the dutycycle balance of synchronizing clock signals is for guaranteeing that the circuit sequence performance is most important, so that in current design chips, DDR2 need to have more accurate clock accuracy and clock frequency faster.
The conventional digital delay chain circuits generally adopts digital-to-analogue Mixed Design method; be confined under certain special process; the flexible design degree is not high; particularly in Deep submicron chip technique, exist the temperature Inversion Problem; the delayed latch circuit variation obvious effect that traditional digital-to-analogue is mixed, there are larger variation in the DQS signal that obtains and write operation clock, if do not satisfy the sequential requirement of DDR2 standard; in DDR2 read-write process, may produce the situation of reading and writing data mistake.
Existing digital delay unit is a kind of to be comprised of accurate adjustment digital delay unit and coarse adjustment delay cell, and the coarse adjustment unit has adopted the Sheffer stroke gate structure, and the accurate adjustment unit has adopted the rejection gate structure, another kind by impact damper, with the door and selector switch form.Because the technology library device cell itself exists rising edge and negative edge deviation, existing digital delay unit output clock rising edge and negative edge have very large deviation, and this deviation is along with the increase of cascade progression is constantly accumulated, had a strong impact on the dutycycle performance of clock signal, particularly in high speed DDR2 system, may not satisfy the requirement of DDR2 reservoir designs between DQS, the DQ that existing digital delay locked loop circuit produces and the DDR2 storer major clock, cause the reading and writing data mistake, system's cisco unity malfunction.
Summary of the invention
Technical matters: the present invention seeks to solve the technical matters of mentioning in the above-mentioned background, a kind of high duty ratio DDR2 digital delay chain circuit is provided, solve existing DDR2 digital delay chain clock duty cycle problem, improve the frequency of operation of DDR2.
Technical scheme: the object of the invention is to, for the clock duty cycle problem that existing DDR2 digital delay chain circuit produces, the existing lower problem of digital delay chain applying frequency proposes a kind of high duty ratio DDR2 digital delay chain circuit.This circuit is built the digital delay chain based on improved digital delay unit, improve clock duty cycle and system works frequency, the solution that proposes is digital design, not only can improve clock duty cycle and the frequency of operation of DDR2, reduce circuit complexity, and the design of this circuit is not relying on special process.
The present invention includes digital delay unit, clock lock digital delay chain, write operation clock numeral delay chain, write operation DQS digital delay chain and read operation DQS digital delay chain.
Described digital delay unit is to be composed in series by postponing minimum clocked inverter and the less clock selector of rising edge negative edge deviation.The input clock of digital delay unit enters the port B of digital delay unit clock selector, behind the clocked inverter of the output signal of next stage digital delay unit through digital delay at the corresponding levels unit, is connected to clock selector port A at the corresponding levels; When the clock selector switch selects signal to be 1, digital delay at the corresponding levels unit output clock selector switch port B signal, when the selection signal of digital delay at the corresponding levels unit was 0, digital delay at the corresponding levels unit output clock selector switch port A data were to upper level digital delay unit.
Described clock lock digital delay chain is adjusted the digital delay units in series by the identical digital delay unit of N level with the phase place that possesses digital delay unit same circuits structure and is formed.The input end of clock lock digital delay chain is the system clock of DDR2, adopts only hot yard digital delay element number configuration register one_hot_clock_lock_delaycell_num to connect the selection sel port of the clock selector of digital delay cell.The 0th the selection sel port that is connected to the 1st stages of digital delay cell clock selector of one_hot_clock_lock_delaycell_num, the 1st selection sel port that is connected to the 2nd stages of digital delay cell clock selector, by that analogy, the N-1 position is connected to the selection sel port of N stages of digital delay cell clock selector; The DDR2 system clock is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.The output of the 1st stages of digital delay cell is connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit, clock selector B port is connected to the output port of this grade clocked inverter, when the binary value that one_hot_clock_lock_delaycell_num is corresponding is odd number, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described clock lock digital delay chain, when from M stages of digital delay units delay, be that one_hot_clock_lock_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell outputs to phase place and adjusts the digital delay unit; When the binary value that one_hot_clock_lock_delaycell_num is corresponding was odd number, phase place was adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.When the retardation of M stages of digital delay cell during less than a DDR2 system clock cycle, digital delay element number configuration register one_hot_clock_lock_delaycell_num increases, and is cumulative until lock a clock period with this; Otherwise then reduce the quantity of digital delay unit, successively decrease until lock a clock period with this.
Described clock lock digital delay chain is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
Described clock lock digital delay chain is characterized in that, when M is even number, and digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset the clock lock digital chain arrive output C port rising edge and negative edge deviation.After the phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay unit rising edge and the negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset clock lock digital chain clock selector B port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that clock lock digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
Described write operation clock numeral delay chain is characterized in that, adjusts the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of write operation clock numeral delay chain is received the system clock of DDR2, one_hot_write_clk_delaycell_num writes clock to postpone digital delay element number corresponding to 3/4 phase place with respect to the DDR2 system clock, its corresponding scale-of-two lowest order write_clk_delaycell_num_odd is connected to phase place and adjusts the digital delay unit, one_hot_write_clk_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_write_clk_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of first order digital delay unit clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the clock signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when write_clk_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described write operation clock numeral delay chain, it is characterized in that, when from M stages of digital delay units delay, be that one_hot_write_clk_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output postpones the high duty ratio write operation clock of 3/4 phase place with respect to the DDR2 system clock.
Described write operation clock numeral delay chain is characterized in that delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
Described write operation clock numeral delay chain is characterized in that, when M is even number, and digital delay unit rising edge and the negative edge deviation of M-2 stages of digital delay cell clock selector A port to the generation of selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Write operation clock numeral delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset write operation clock digital chain arrive output C port rising edge and negative edge deviation.After the phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M was odd number, the digital delay unit M-1 stages of digital delay cell of having cancelled out each other produced clock selector A port to rising edge and the negative edge deviation of selector switch C port; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Write operation clock numeral delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset write operation clock digital chain clock selector B port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that write operation clock numeral delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
Described write operation DQS digital delay chain is characterized in that, adjusts the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of write operation DQS digital delay chain is received the system clock of DDR2, one_hot_write_dqs_delaycell_num writes clock to postpone digital delay element number corresponding to 1 phase place with respect to the DDR2 system clock, its corresponding binary value lowest order write_dqs_delaycell_num_odd is connected to phase place and adjusts the digital delay unit, one_hot_write_dqs_delaycell_num is connected to the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_write_dqs_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the write operation DQS signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when write_dqs_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described write operation DQS digital delay chain, it is characterized in that, when from M stages of digital delay units delay, be that one_hot_write_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output is with respect to the high duty ratio write operation DQS of 1 phase delay of DDR2 system clock.
Described write operation DQS digital delay chain is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
Described write operation DQS digital delay chain is characterized in that, when M is even number, and digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clocked inverter and selector switch A port produce to output C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Write operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset write operation DQS digital chain arrive output C port rising edge and negative edge deviation.After the phase place adjustment, the write operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay unit rising edge and the negative edge deviation that M-1 stages of digital delay cell clocked inverter and selector switch A port produce to output C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Write operation DQS digital delay chain first order digital delay unit outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset write operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that write operation DQS digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
Described read operation DQS digital delay chain is characterized in that, adjusts the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of read operation DQS digital delay chain is received the system clock of DDR2, one_hot_read_dqs_delaycell_num writes clock to postpone digital delay element number corresponding to 1 phase place with respect to the DDR2 system clock, its corresponding binary value lowest order one_hot_read_dqs_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_read_dqs_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the write operation DQS signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when read_dqs_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described read operation DQS digital delay chain, it is characterized in that, when from M stages of digital delay units delay, be that one_hot_read_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output is with respect to the high duty ratio read operation DQS of DDR2 system clock 1/4 phase delay.
Described read operation DQS digital delay chain is characterized in that, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
Described read operation DQS digital delay chain is characterized in that, when M is even number, and digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset read operation DQS digital chain arrive output C port rising edge and negative edge deviation.After the phase place adjustment, the read operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.When M is odd number, digital delay unit rising edge and the negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset read operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that read operation DQS digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
Beneficial effect: compare with existing technical scheme, the invention has the advantages that:
1. with respect to analog form, digital delay chain circuit described in the present invention be not confined to certain certain chip design technology, be not subject to technique-temperature-voltage influence, having technique-temperature-voltage adaptive and adjust effect and realize definitely flexibly advantage.
2. digital delay chain element of the present invention adopts a clocked inverter and a clock selector to be composed in series, select to postpone minimum clocked inverter and clock selector and be composed in series basic digital delay cell, improved the precision of digital delay chain, the frequency of operation of system can be greatly improved.
3. because device itself exists rising edge and negative edge delay distortion, if directly adopt traditional digital delay element circuit, each impact damper, accumulate through the N level with the rising edge of door, Sheffer stroke gate, selector switch and negative edge delay distortion after, the duty cycle deviations of output clock strengthens, and may cause the output clock cisco unity malfunction.The digital delay chain is comprised of several identical digital delay units in series, and the clock after the digital delay chain postpones is adjusted the digital delay unit by phase place and adjusted phase place, it is advantageous that:
A. when a clock locking digital delay chain clock period of locking numeral delay cell quantity clock_locked_delaycell_num is even number, duty cycle deviations only is that 1 clock selector A port is to the deviation of C port, when clock_locked_delaycell_num is odd number, duty cycle deviations is 0, under equal process conditions, clock duty cycle has approached 1:1.
B. when 3/4 binary value corresponding to DDR2 system clock cycle digital delay element number of write operation clock numeral delay chain input signal one_hot_write_clk_delaycell_num locking is even number, duty cycle deviations only is that 1 clock selector A port is to the deviation of C port, during for odd number, duty cycle deviations is 0.Under equal process conditions, clock duty cycle has approached 1:1.
C. when 1 binary value corresponding to DDR2 system clock cycle digital delay element number of write operation DQS digital delay chain input signal one_hot_write_dqs_delaycell_num locking is even number, duty cycle deviations only is that 1 clock selector A port is to the deviation of C port, during for odd number, duty cycle deviations is 0.Under equal process conditions, clock duty cycle has approached 1:1.
D. when 1/4 binary value corresponding to DDR2 system clock cycle digital delay element number of read operation DQS digital delay chain input signal one_hot_read_dqs_delaycell_num locking is even number, duty cycle deviations only is that 1 clock selector A port is to the deviation of C port, during for odd number, duty cycle deviations is 0.Under equal process conditions, clock duty cycle has approached 1:1.
Description of drawings
Fig. 1 is digital delay of the present invention unit.
Fig. 2 is clock lock digital delay chain circuit of the present invention.
Fig. 3 is write operation clock numeral delay chain circuits of the present invention.
Fig. 4 is write operation DQS digital delay chain circuit of the present invention.
Fig. 5 is read operation DQS digital delay chain circuit of the present invention.
Embodiment
The present invention is described in detail below with reference to the drawings and specific embodiments.This paper is with 128 stages of digital delay chains, the DDR2 system clock cycle is 3.75ns, frequency is 266Mhz, the DDR2 storer is 533Mhz, and DDR2 system configurable phase deviation register bit wide is 8, and every stages of digital delay units delay amount is 0.1ns, it is 11 that clock lock digital delay start of chain postpones progression, as embodiment, described embodiment only is a kind of embodiment of the present invention, is not whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The invention process discloses a kind of high duty ratio DDR2 digital delay chain circuit, comprising: digital delay unit, clock lock digital delay chain, write operation clock numeral delay chain, write operation DQS digital delay chain and read operation DQS digital delay chain.
Described digital delay unit please refer to accompanying drawing 1, is composed in series by postponing minimum clocked inverter and the less clock selector of rising edge negative edge deviation.The input clock of digital delay unit enters the port B of digital delay unit clock selector, behind the clocked inverter of the output signal of next stage digital delay unit through digital delay at the corresponding levels unit, is connected to clock selector port A at the corresponding levels; When the clock selector switch selects signal to be 1, digital delay at the corresponding levels unit output clock selector switch port B signal, when the selection signal of digital delay at the corresponding levels unit was 0, digital delay at the corresponding levels unit output clock selector switch port A data were to upper level digital delay unit.
Described clock lock digital delay chain please refer to accompanying drawing 2, adjusts the digital delay units in series by 128 grades of identical digital delay unit and the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of clock lock digital delay chain is received the system clock of DDR2, adopting solely, the binary value clock_lock_delaycell_num_odd corresponding to digital delay element number configuration register one_hot_clock_lock_delaycell_num of heat code is connected to phase place adjustment digital delay unit, digital delay element number configuration register one_hot_clock_lock_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 1st the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_clock_lock_delaycell_num, the 2nd selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the 128th selection sel port that is connected to delay chain the 128th stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes the 128th stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to 127 stages of digital delay cells is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the clock signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when clock_lock_delaycell_num_odd, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described clock lock digital delay chain, clock lock digital delay chain postpones from the 11st selected stages of digital delay cell, the retardation of 11 stages of digital delay cells is during less than a DDR2 system clock cycle, the DDR22 system controller increases the quantity of selected digital delay unit, cumulative until lock a clock period with this, the digital delay element number of this example clock period of locking is the clock period to measure whole divided by the digital delay cell delay, be 3.75/0.1=38, owing to there are the factors such as wire delay, the digital delay element number selects 37.
Described clock lock digital delay chain, when from the 37th stages of digital delay units delay, be that the 36th of one_hot_clock_lock_delaycell_num is 1, the 36th stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, clock selector sel port from the 1st grade to the 37th stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from the 36th stages of digital delay cell, be input to the 35th stages of digital delay cell clocked inverter, be input to the 35th stages of digital delay cell clock selector A mouth through behind the phase inverter, the 35th stages of digital delay cell output signal is connected to the 34th stages of digital delay cell clocked inverter, be input to the 34th stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit.
Described clock lock digital delay chain, delayed clock outputs to selector switch C port from the 37th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 36th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 35th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 36 clocked inverters and clock selector A port to selector switch C port delay.
Described clock lock digital delay chain, digital delay unit rising edge and the negative edge deviation that 36 grades of clocked inverters and clock selector A port produce to selector switch C port number delay cell of having cancelled out each other; Amounting to the deviation that produces through 37 stages of digital delay cells is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset clock lock digital chain clock selector B port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that clock lock digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
Described write operation clock numeral delay chain please refer to accompanying drawing 3, adjusts the digital delay units in series by 128 grades of identical digital delay unit and the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of write operation clock numeral delay chain is received the system clock of DDR2, write_clk_delaycell_num_odd is connected to phase place and adjusts the digital delay unit, one_hot_write_clk_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 1st the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_write_clk_delaycell_num, the 2nd selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the 128th selection sel port that is connected to delay chain the 128th stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes the 128th stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to 127 stages of digital delay cells is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the clock signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when write_clk_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described write operation clock numeral delay chain, when from the 28th stages of digital delay units delay, be that the 27th of one_hot_write_clk_delaycell_num is 1, the 28th stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, clock selector sel port from the 1st grade to the 27th stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from the 28th stages of digital delay cell, be input to the 27th stages of digital delay cell clocked inverter, be input to the 27th stages of digital delay cell clock selector A mouth through behind the phase inverter, the 27th stages of digital delay cell output signal is connected to the 26th stages of digital delay cell clocked inverter, be input to the 26th stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, the output high duty ratio is with respect to the write operation clock of 3/4 phase place of DDR2 system clock.
Described write operation clock numeral delay chain, delayed clock outputs to selector switch C port from the 28th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 27th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 26th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 27 clocked inverters and clock selector A port to selector switch C port delay.
Described write operation clock numeral delay chain, digital delay unit 26 grades of clocked inverters and clock selector A port rising edge and the negative edge deviation to the generation of selector switch C port number delay cell of having cancelled out each other; Amounting to the deviation that produces through 28 stages of digital delay cells is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum.Write operation clock numeral delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset write operation clock digital chain arrive output C port rising edge and negative edge deviation.After the phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.
Described write operation DQS digital delay chain please refer to accompanying drawing 4, adjusts the digital delay units in series by 128 grades of identical digital delay unit and the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of write operation DQS digital delay chain is received the system clock of DDR2, one_hot_write_dqs_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 1st the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_write_dqs_delaycell_num, the 2nd selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the 128th selection sel port that is connected to delay chain the 128th stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes the 128th stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to 127 stages of digital delay cells is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the write operation DQS signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when the digital delay cell quantity of write operation DQS is odd number, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described write operation DQS digital delay chain, the 36th of one_hot_write_dqs_delaycell_num is 1, the 37th stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, clock selector sel port from the 1st grade to the 36th stages of digital delay cell is 0, selects this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from the 37th stages of digital delay cell, be input to the 36th stages of digital delay cell clocked inverter, be input to the 36th stages of digital delay cell clock selector A mouth through behind the phase inverter, the 36th stages of digital delay cell output signal is connected to the 35th stages of digital delay cell clocked inverter, be input to the 35th stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output high duty ratio write operation DQS.
Described write operation DQS digital delay chain, delayed clock outputs to selector switch C port from the 37th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 36th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 35th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 36 clocked inverters and clock selector A port to selector switch C port delay.
Described write operation DQS digital delay chain, digital delay unit rising edge and the negative edge deviation that 36 stages of digital delay cell clock selector A ports produce to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through 37 stages of digital delay cells is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Write operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset write operation DQS digital chain clock selector A port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that write operation DQS digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
Described read operation DQS digital delay chain please refer to accompanying drawing 5, adjusts the digital delay units in series by 128 grades of identical digital delay unit and the one-level phase place that possesses digital delay unit same circuits structure and forms.The input end of read operation DQS digital delay chain is received the system clock of DDR2, one_hot_read_dqs_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_read_dqs_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the 127th selection sel port that is connected to delay chain the 128th stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes the 128th stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to 127 stages of digital delay cells is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of first order digital delay unit clock selector adjusts the digital delay unit, the output of the 128th stages of digital delay cell clock selector is connected to the input end of the 127th stages of digital delay cell clocked inverter, the output of the 127th stages of digital delay cell clock selector is connected to the input end of the 126th stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter.Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the write operation DQS signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when the digital delay cell quantity of write operation DQS is odd number, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
Described read operation DQS digital delay chain, the 8th of one_hot_read_dqs_delaycell_num is 1, the 9th stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the clock selector sel port of the first order to the 8 stages of digital delay cells, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal.After the DDR2 system clock postpones through a clock selector from the 9th stages of digital delay cell, be input to the 8th stages of digital delay cell clocked inverter, be input to the 8th stages of digital delay cell clock selector A mouth through behind the phase inverter, the 8th stages of digital delay cell output signal is connected to the 7th stages of digital delay cell clocked inverter, be input to the 7th stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of first order digital delay unit, first order digital delay unit output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, the output high duty ratio is with respect to the read operation DQS of 1/4 phase place of DDR2 system clock.
Described read operation DQS digital delay chain, its delayed clock outputs to selector switch C port from the 9th stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through the 8th grade of clocked inverter and clock selector A port to selector switch C port delay, again through the 7th grade of clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to through 8 clocked inverters and clock selector A port to selector switch C port delay.
Described read operation DQS digital delay chain, digital delay unit rising edge and the negative edge deviation that 8 stages of digital delay cell clock selector A ports produce to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through 9 stages of digital delay cells is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation.Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset read operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation.After the phase place adjustment, rising edge clock and negative edge deviation that read operation DQS digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.

Claims (23)

1. a high duty ratio DDR2 digital delay chain circuit is characterized in that: comprise digital delay unit, clock lock digital delay chain, write operation clock numeral delay chain, write operation DQS digital delay chain and read operation DQS digital delay chain.
2. high duty ratio DDR2 digital delay chain circuit according to claim 1 is characterized in that: described digital delay unit is to be composed in series by postponing minimum clocked inverter and the less clock selector of rising edge negative edge deviation; Described digital delay chain is to be formed by a plurality of digital delay units in series.
3. require described high duty ratio DDR2 digital delay chain circuit according to right 2, it is characterized in that, the input clock of digital delay at the corresponding levels unit enters the port B of digital delay unit clock selector, behind the clocked inverter of the output signal of next stage digital delay unit through digital delay at the corresponding levels unit, be connected to clock selector port A at the corresponding levels; When the clock selector switch selects signal to be 1, digital delay at the corresponding levels unit output clock selector switch port B signal, when the selection signal of digital delay at the corresponding levels unit was 0, digital delay at the corresponding levels unit output clock selector switch port A data were to upper level digital delay unit.
4. high duty ratio DDR2 digital delay chain circuit according to claim 1, it is characterized in that: described clock lock digital delay chain, adjust the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and form.
5. high duty ratio DDR2 digital delay chain circuit according to claim 4, it is characterized in that: the input end of described clock lock digital delay chain is the system clock of DDR2, adopt the binary value lowest order clock_lock_delaycell_num_odd corresponding to digital delay element number configuration register one_hot_clock_lock_delaycell_num of only heat code to be connected to phase place adjustment digital delay unit, digital delay element number configuration register one_hot_clock_lock_delaycell_num is as the selection sel port of the clock selector of digital delay unit; The 0th the selection sel port that is connected to the 1st stages of digital delay cell clock selector of one_hot_clock_lock_delaycell_num, the 1st selection sel port that is connected to the 2nd stages of digital delay cell clock selector, by that analogy, the N-1 position is connected to the selection sel port of N stages of digital delay cell clock selector; The DDR2 system clock is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter; The output of the 1st stages of digital delay cell is connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit, clock selector B port is connected to the output port of this grade clocked inverter, clock_lock_delaycell_num_odd is 1 o'clock, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
6. high duty ratio DDR2 digital delay chain circuit according to claim 5, it is characterized in that: described clock lock digital delay chain, when from M stages of digital delay units delay, be that one_hot_clock_lock_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal; After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell outputs to phase place and adjusts the digital delay unit; Clock_lock_delaycell_num_odd is 1 o'clock, and phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data; When the retardation of M stages of digital delay cell during less than a DDR2 system clock cycle, clock lock phase detector and clock lock digital delay chain controller increase the quantity of selected digital delay unit, and be cumulative until lock a clock period with this; Otherwise then reduce the quantity of digital delay unit, successively decrease until lock a clock period with this.
7. high duty ratio DDR2 digital delay chain circuit according to claim 6, it is characterized in that: described clock lock digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
8. high duty ratio DDR2 digital delay chain circuit according to claim 6, it is characterized in that: described clock lock digital delay chain, when M is even number, digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset the clock lock digital chain arrive output C port rising edge and negative edge deviation; After the phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay unit rising edge and the negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Clock lock digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset clock lock digital chain clock selector B port to output C port rising edge and negative edge deviation; After the phase place adjustment, rising edge clock and negative edge deviation that clock lock digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
9. high duty ratio DDR2 digital delay chain circuit according to claim 1, it is characterized in that: described write operation clock numeral delay chain, adjust the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and form.
10. high duty ratio DDR2 digital delay chain circuit according to claim 9, it is characterized in that: the input end of described write operation clock numeral delay chain is received the system clock of DDR2, adopting solely, the binary value lowest order write_clk_delaycell_num_odd corresponding to digital delay element number configuration register one_hot_write_clk_delaycell_num of heat code is connected to phase place adjustment digital delay unit, one_hot_write_clk_delaycell_num is as the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_write_clk_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of first order digital delay unit clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter; Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the clock signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when write_clk_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
11. high duty ratio DDR2 digital delay chain circuit according to claim 10, it is characterized in that: described write operation clock numeral delay chain, when from M stages of digital delay units delay, be that one_hot_write_clk_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal; After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output postpones the high duty ratio write operation clock of 3/4 phase place with respect to the DDR2 system clock.
12. high duty ratio DDR2 digital delay chain circuit according to claim 11, it is characterized in that: described write operation clock numeral delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
13. high duty ratio DDR2 digital delay chain circuit according to claim 11, it is characterized in that: described write operation clock numeral delay chain, when M is even number, digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Write operation clock numeral delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset write operation clock digital chain arrive output C port rising edge and negative edge deviation; After the phase place adjustment, the rising edge clock of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M was odd number, the digital delay unit M-1 stages of digital delay cell of having cancelled out each other produced clock selector A port to rising edge and the negative edge deviation of selector switch C port; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Write operation clock numeral delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset write operation clock digital chain clock selector B port to output C port rising edge and negative edge deviation; After the phase place adjustment, rising edge clock and negative edge deviation that write operation clock numeral delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
14. high duty ratio DDR2 digital delay chain circuit according to claim 1, it is characterized in that: described write operation DQS digital delay chain, adjust the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and form.
15. high duty ratio DDR2 digital delay chain circuit according to claim 14, it is characterized in that: the input end of described write operation DQS digital delay chain is received the system clock of DDR2, adopting solely, the binary value lowest order write_dqs_delaycell_num_odd corresponding to digital delay element number configuration register one_hot_write_dqs_delaycell_num of heat code is connected to phase place adjustment digital delay unit, one_hot_write_dqs_delaycell_num is connected to the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_write_dqs_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter; Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the write operation DQS signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when write_dqs_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
16. high duty ratio DDR2 digital delay chain circuit according to claim 15, it is characterized in that: described write operation DQS digital delay chain, when from M stages of digital delay units delay, be that one_hot_write_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal; After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output is with respect to the high duty ratio write operation DQS of 1 phase delay of DDR2 system clock.
17. high duty ratio DDR2 digital delay chain circuit according to claim 16, it is characterized in that: described write operation DQS digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
18. high duty ratio DDR2 digital delay chain circuit according to claim 16, it is characterized in that: described write operation DQS digital delay chain, when M is even number, digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clocked inverter and selector switch A port produce to output C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Write operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset write operation DQS digital chain arrive output C port rising edge and negative edge deviation; After the phase place adjustment, the write operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay unit rising edge and the negative edge deviation that M-1 stages of digital delay cell clocked inverter and selector switch A port produce to output C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Write operation DQS digital delay chain first order digital delay unit outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset write operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation; After the phase place adjustment, rising edge clock and negative edge deviation that write operation DQS digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
19. high duty ratio DDR2 digital delay chain circuit according to claim 1, it is characterized in that: described read operation DQS digital delay chain, adjust the digital delay units in series by the identical digital delay unit of N level with the one-level phase place that possesses digital delay unit same circuits structure and form.
20. high duty ratio DDR2 digital delay chain circuit according to claim 19, it is characterized in that: the input end of described read operation DQS digital delay chain is received the system clock of DDR2, adopt binary value lowest order one_hot_read_dqs_delaycell_num corresponding to only hot yard digital delay element number configuration register one_hot_read_dqs_delaycell_num as the selection sel port of the clock selector of digital delay unit, the 0th the selection sel port that is connected to delay chain the 1st stages of digital delay cell clock selector of one_hot_read_dqs_delaycell_num, the 1st selection sel port that is connected to delay chain the 2nd stages of digital delay cell clock selector, by that analogy, the N position is connected to the selection sel port of delay chain N stages of digital delay cell clock selector; The DDR2 system clock of input is connected to the B port of each stages of digital delay cell clock selector, the A port that removes N stages of digital delay cell clock selector is connected to fixes 0, clock selector A port from the 1st stages of digital delay cell to N-1 stages of digital delay cell is connected to the output of digital delay at the corresponding levels unit clocked inverter, receiving phase place except the output terminal of the 1st stages of digital delay cell clock selector adjusts the digital delay unit, the output of N stages of digital delay cell clock selector is connected to the input end of N-1 stages of digital delay cell clocked inverter, the output of N-1 stages of digital delay cell clock selector is connected to the input end of N-2 stages of digital delay cell clocked inverter, by that analogy, the output of the 2nd stages of digital delay cell clock selector is connected to the input end of the 1st stages of digital delay cell clocked inverter; Be connected to clocked inverter input port and the clock selector A port that phase place is adjusted the digital delay unit through the write operation DQS signal after postponing, clock selector B port is connected to the output port of this grade clocked inverter, when read_dqs_delaycell_num_odd is 1, phase place is adjusted digital delay unit output clock selector switch B port data, on the contrary outlet selector A port data.
21. high duty ratio DDR2 digital delay chain circuit according to claim 20, it is characterized in that: described read operation DQS digital delay chain, when from M stages of digital delay units delay, be that one_hot_read_dqs_delaycell_num M-1 position is 1, M stages of digital delay cell clock selector sel port is 1, select this stages of digital delay cell clock selector B port as this stages of digital delay cell output signal, be 0 from the 1st grade of clock selector sel port to M-1 stages of digital delay cell, select this stages of digital delay cell clock selector A port as this stages of digital delay cell output signal; After the DDR2 system clock postpones through a clock selector from M stages of digital delay cell, be input to M-1 stages of digital delay cell clocked inverter, be input to M-1 stages of digital delay cell clock selector A mouth through behind the phase inverter, M-1 stages of digital delay cell output signal is connected to M-2 stages of digital delay cell clocked inverter, be input to M-2 stages of digital delay cell clock selector A mouth through behind the phase inverter, by that analogy, until inhibit signal arrives the output C port of the clock selector of the 1st stages of digital delay cell, the 1st stages of digital delay cell output clock is input to phase place and adjusts the digital delay unit, through the phase place adjustment, output is with respect to the high duty ratio read operation DQS of DDR2 system clock 1/4 phase delay.
22. high duty ratio DDR2 digital delay chain circuit according to claim 21, it is characterized in that: described read operation DQS digital delay chain, delayed clock outputs to selector switch C port from M stages of digital delay cell clock selector B port, and output clock exists 1 clock selector B port rising edge and negative edge deviation; Then through M-1 level clocked inverter and clock selector A port to selector switch C port delay, again through M-2 level clocked inverter and clock selector A port to selector switch C port delay, by that analogy, amount to M-1 clocked inverter of process and clock selector A port to selector switch C port delay.
23. high duty ratio DDR2 digital delay chain circuit according to claim 21, it is characterized in that: described read operation DQS digital delay chain, when M is even number, digital delay unit rising edge and the negative edge deviation that M-2 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port, a clocked inverter and a clock selector A port to selector switch C port rising edge and negative edge deviation sum; Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch A port data, and clocked inverter and the selector switch A port of having offset read operation DQS digital chain arrive output C port rising edge and negative edge deviation; After the phase place adjustment, the read operation DQS rising edge of output and negative edge deviation are that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; When M is odd number, digital delay unit rising edge and the negative edge deviation that M-1 stages of digital delay cell clock selector A port produces to selector switch C port of having cancelled out each other; Amounting to the deviation that produces through M stages of digital delay cell is that 1 clock selector B port is to selector switch C port rising edge and negative edge deviation; Read operation DQS digital delay chain the 1st stages of digital delay cell outputs to phase place and adjusts digital delay unit clock selector B port and clocked inverter input port, phase place is adjusted digital delay unit output clock selector switch B port data, has offset read operation DQS digital chain clock selector B port to output C port rising edge and negative edge deviation; After the phase place adjustment, rising edge clock and negative edge deviation that read operation DQS digital delay chain postpones are 0, and the output clock dutycycle has reached 1:1.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113325744A (en) * 2021-04-25 2021-08-31 北京时代民芯科技有限公司 DDR3 storage protocol-oriented calibration controller
CN115862707A (en) * 2022-11-25 2023-03-28 湖南兴芯微电子科技有限公司 PSRAM phase calibration method and controller

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1677863A (en) * 2004-03-29 2005-10-05 富士通株式会社 Digital DLL device, digital DLL control method, and digital DLL control program
US20060209618A1 (en) * 2005-03-03 2006-09-21 Promos Technologies Inc. Efficient register for additive latency in DDR2 mode of operation
CN1866739A (en) * 2005-05-17 2006-11-22 三星电子株式会社 Delay circuit and semiconductor device including same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1677863A (en) * 2004-03-29 2005-10-05 富士通株式会社 Digital DLL device, digital DLL control method, and digital DLL control program
US20060209618A1 (en) * 2005-03-03 2006-09-21 Promos Technologies Inc. Efficient register for additive latency in DDR2 mode of operation
CN1866739A (en) * 2005-05-17 2006-11-22 三星电子株式会社 Delay circuit and semiconductor device including same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113325744A (en) * 2021-04-25 2021-08-31 北京时代民芯科技有限公司 DDR3 storage protocol-oriented calibration controller
CN115862707A (en) * 2022-11-25 2023-03-28 湖南兴芯微电子科技有限公司 PSRAM phase calibration method and controller
CN115862707B (en) * 2022-11-25 2024-03-12 湖南兴芯微电子科技有限公司 PSRAM phase calibration method and controller

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