CN113178223A - Data training method of memory, computer device and computer readable storage medium - Google Patents
Data training method of memory, computer device and computer readable storage medium Download PDFInfo
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Abstract
The invention provides a data training method of a memory, a computer device and a computer readable storage medium, wherein the method comprises the steps of reading test data from a plurality of DQ pins, and carrying out XOR calculation on the test data and target data; setting the delay parameter as a minimum value, gradually changing the delay parameter, and calculating the left and right boundaries of the DQ eye pattern according to the different and identical result of the test data and the target data under the current delay parameter and the different and identical result of the test data and the target data under the last delay parameter; and gradually adjusting the reference voltage, and calculating the upper and lower boundaries of the DQ eye diagram according to the similarity result of the test data and the target data under the current reference voltage and the similarity result of the test data and the target data under the previous reference voltage. The invention also provides a computer device and a computer readable storage medium for realizing the method. According to the invention, the error DQ pins are quickly identified by performing XOR calculation on a plurality of DQ signals in parallel, so that the data training time can be reduced.
Description
Technical Field
The invention relates to the technical field of data reading and writing of a memory, in particular to a data training method of the memory, a computer device for realizing the method and a computer readable storage medium.
Background
Most of the electronic devices currently have a volatile memory, such as a DRAM, and when the host controller reads and writes data from and to the volatile memory, the data needs to be read through a plurality of pins of the volatile memory. For example, the DRAM is provided with 32 data pins, and the host controller can read and write data with the DRAM through the 32 data pins.
When the main controller and the DRAM perform data reading and writing, a synchronous clock signal, that is, a DQS signal, is usually set for each Byte (Byte), a signal formed on each data pin DQ of the DRAM becomes a DQ signal, and a Byte usually includes 8 DQ signals, as shown in fig. 1, after one data pin is subjected to thousands of data reading and writing, data read and written for many times are superimposed on one DQ pin to form a DQ eye diagram, which is usually in a hexagonal shape, in fig. 1, a horizontal axis represents time, a vertical axis represents voltage, Teye is eye width obtained by software data training of the DQ signal, and Veye is eye height obtained by software data training of the DQ signal.
In general, data sampled by the main controller on the data pin is correct data when the DQS signal passes through the DQ eye pattern, and erroneous data if the DQS signal does not pass through the DQ eye pattern. In practical application, different DRAM particles of the same manufacturer or DRAM particles of different manufacturers have a large difference in the phase relationship between the DQS signal and the DQ signal under different power supply conditions or due to factors such as differences in PCB material, and the phase interference of the factors on the DQS signal and the DQ signal is larger as the clock frequency increases. Therefore, in order to reduce the interference of various external factors and ensure the performance and stability of DRAM access, it is necessary to ensure the phase synchronization of the DQs signal and the DQ signal through data training of the DQ signal. In general, an important task for data training of DQ signals is to calculate the eye height and eye width of a DQ eye pattern, i.e., to calculate the left and right boundaries and the upper and lower boundaries of the DQ eye pattern.
Currently, there are three common methods for data training of DRAM: the first is through the data training function of hardware state machine control, the second is through the oscilloscope snatchs the wave form and carries on the DQS signal and the DQ signal phase place assessment, the third is through the method of software control to carry on the data training.
The first method has two drawbacks: firstly, the hardware state machine is complex in design and occupies a large area, so that the cost of a chip is increased; secondly, expansibility and adaptability are poor, hardware is often redesigned aiming at a new application scene, cost is high, and time consumption is long.
The second method also has two drawbacks: the first is that the method can only be used for evaluation in a development stage and cannot provide the most suitable parameters for each electronic product; the second is that it is currently popular to integrate the SOC and DRAM particles together on a package, and to connect them inside the package, and the oscilloscope will not be able to acquire the desired waveform.
The third method is the mainstream method, but has the defects of low training efficiency and long time consumption, and the current training time is mainly consumed in three aspects: the first is that all DQ signals are trained in series, and the total time consumption is longer due to the fact that the number of data pins is large; secondly, the eye height and eye width of the DQ eye pattern are adjustable in many gears, and the time spent in gear-by-gear is long; thirdly, the speed of data comparison by software is slow, for example, when 1MB of data is read and written, the time of data comparison occupies 40% to 50%, so most of the time is consumed in data comparison, and the average bandwidth in the training process is low.
Disclosure of Invention
A first object of the present invention is to provide a data training method of a memory capable of improving software training efficiency.
The second objective of the present invention is to provide a computer device for implementing the data training method of the memory.
A third object of the present invention is to provide a computer-readable storage medium for implementing the data training method of the above memory.
In order to achieve the first object of the present invention, the data training method of the memory provided by the present invention includes writing target data into a preset memory space of the memory, and reading test data from the preset memory space through a plurality of DQ pins of the memory; the method comprises the following steps of reading test data from a plurality of DQ pins in parallel, and judging whether the test data is the same as target data or not: carrying out XOR calculation on the test data and the target data, and determining the similarities and differences between the test data and the target data according to the results of the XOR calculation; setting the delay parameter as a minimum value, gradually changing the delay parameter, and calculating the left and right boundaries of the DQ eye pattern according to the different and identical result of the test data and the target data under the current delay parameter and the different and identical result of the test data and the target data under the last delay parameter; and gradually adjusting the reference voltage, and calculating the upper and lower boundaries of the DQ eye diagram according to the similarity result of the test data and the target data under the current reference voltage and the similarity result of the test data and the target data under the previous reference voltage.
According to the scheme, when the data of the memory is trained, a plurality of DQ signals can be read once, for example, 32 DQ signals are read, and the test data corresponding to the plurality of DQ signals can be compared simultaneously in an exclusive-or calculation mode, so that which DQ signals are wrong is determined, delay parameters of all DQ signals can be synchronously adjusted, DQ pins corresponding to the wrong signals are judged, the effect of parallel training of all DQ pins is achieved, and the data training time can be greatly reduced.
Preferably, the writing the target data into the preset storage space of the memory comprises: writing target data at a first clock frequency during a data reading direction test; reading test data from a preset memory space through a plurality of DQ pins of a memory comprises: reading test data from a preset storage space at a second clock frequency; wherein the first clock frequency is lower than the second clock frequency.
Therefore, the target data can be written in the memory correctly by writing the target data at a lower clock frequency, and the clock frequency is adjusted to a higher actual working clock frequency in the reading direction test process, so that the accuracy of the test result can be ensured.
Optionally, writing the target data into the preset storage space of the memory includes: and circularly writing the target data into the preset storage space for multiple times during data writing test.
It can be seen that, at the time of the write test, if one of the written target data is erroneous, the same error of all the target data is the same. Because errors in the reading and writing process are accumulated step by step, when data comparison is carried out, whether errors occur in the previous data reading and writing process can be known only by comparing the last written test data with the target data fragment, the data comparison time is greatly reduced, and the data training efficiency is improved.
In a further aspect, the delay parameter has a plurality of adjustment steps; gradually changing the delay parameter includes: and changing the delay parameter by using the maximum adjustment gear, returning the previous delay parameter when the test data under the current delay parameter is the same as the target data, reducing the adjustment gear by one gear, adjusting the delay parameter, and judging the difference between the test data under the delay parameter after the adjustment of the reduced gear and the target data.
Therefore, the delay parameters are changed by adjusting the gear maximally in the initial stage of the test, so that the efficiency of data training can be improved, and the time required by gear adjustment is greatly reduced.
More preferably, the calculating the left and right boundaries of the DQ eye pattern according to the difference and identity result of the test data and the target data under the current delay parameter and the difference and identity result of the test data and the target data under the previous delay parameter includes: and if the different and identical result of the test data and the target data under the current delay parameter is different from the different and identical result of the test data and the target data under the last delay parameter, and the adjusting gear of the current delay parameter is the minimum gear, determining that the current delay parameter corresponds to the left boundary or the right boundary of the DQ eye diagram.
Therefore, when the data comparison result is turned, the read left and right boundaries of the DQ eye pattern are not immediately confirmed, whether the gear of the current delay parameter is the minimum gear or not needs to be determined, and if the gear of the delay parameter is not the minimum gear, the left and right boundaries of the DQ eye pattern need to be determined after the gear of the delay parameter is set to the minimum gear, so that the accuracy of the searched boundary of the DQ eye pattern is ensured.
In a preferred embodiment, calculating the left and right boundaries of the DQ eye pattern comprises: the left and right boundaries of the DQ eye pattern in the data read direction are calculated, and then the left and right boundaries of the DQ eye pattern in the data write direction are calculated.
Therefore, for the data reading direction and the data writing direction, the left boundary and the right boundary of the DQ eye pattern are respectively calculated, and the accuracy of finding the DQ eye pattern boundaries in two different directions can be ensured.
Further, the gradually adjusting the reference voltage comprises: setting the reference voltage as a minimum value, and if the test data is different from the target data under the current reference voltage, increasing the reference voltage according to a preset amplitude; if the test data is the same as the target data at the current reference voltage and the test data is different from the target data at the previous voltage, it is determined that the current reference voltage corresponds to the lower boundary of the DQ eye pattern.
Therefore, the lower boundary of the DQ eye diagram is obtained by gradually adjusting the reference voltage, so that the calculation of the lower boundary of the DQ eye diagram can be more accurate.
Further, after confirming the lower boundary of the DQ eye diagram, continuing to adjust the reference voltage; if the test data is different from the target data at the current reference voltage and the test data is the same as the target data at the previous voltage, it is determined that the current reference voltage corresponds to the upper boundary of the DQ eye pattern.
Therefore, the upper boundary and the lower boundary of the DQ eye pattern can be realized by gradually adjusting the reference voltage, the upper boundary and the lower boundary of the DQ eye pattern can be determined by calculating the similarities and differences between the target data and the test data under different reference voltages, and the upper boundary and the lower boundary of the DQ eye pattern can be accurately calculated.
In order to achieve the second object, the present invention provides a computer device comprising a processor and a program memory, wherein the program memory stores a computer program, and the computer program realizes the steps of the data training method of the memory when being executed by the processor.
To achieve the third objective, the present invention provides a computer-readable storage medium having a computer program stored thereon, where the computer program is executed by a processor to implement the steps of the data training method of the memory.
Drawings
FIG. 1 is a schematic diagram of a DQ eye and DQS signals.
FIG. 2 is a flow chart of an embodiment of a method for data training of a memory of the present invention.
FIG. 3 is a diagram illustrating a host controller writing data to a memory according to an embodiment of the data training method for a memory of the present invention.
FIG. 4 is a flow chart of calculating the DQ eye left and right boundaries in an embodiment of a data training method for a memory of the present invention.
FIG. 5 is a diagram illustrating calculation of the DQ eye left and right boundaries in an embodiment of the data training method for a memory according to the invention.
FIG. 6 is a flow chart of calculating the upper and lower bounds of the DQ eye in an embodiment of the data training method of the memory of the present invention.
FIG. 7 is a diagram illustrating calculation of upper and lower boundaries of a DQ eye in an embodiment of a data training method for a memory according to the invention.
The invention is further explained with reference to the drawings and the embodiments.
Detailed Description
The data training method of the memory is applied to a main controller, preferably, the main controller is in direct communication with the memory, for example, the memory is a DRAM (dynamic random access memory) provided with a plurality of data pins, namely DQ pins, and the main controller writes data into the DRAM through the DQ pins and reads data from the DRAM. Preferably, the main controller is provided with a processor and a program memory, the program memory stores a computer program, and the processor implements the data training method of the memory by executing the computer program.
The embodiment of the data training method of the memory comprises the following steps:
the main idea of this embodiment is to perform data training of a Dynamic Random Access Memory (DRAM) by a software control method, which also becomes DQ training, that is, on the premise of not depending on a hardware training state machine of the DRAM, a main controller such as a CPU sends a read-write command to DRAM particles according to a certain algorithm and performs data comparison to obtain an optimal phase relationship between a DQs signal and a DQ signal in a data read direction and a data write direction, respectively, and provides optimization in three aspects for a problem of long software training time, that is, optimization in three aspects of parallelization testing, reduction of adjustment steps, and reduction of data comparison time, so as to meet the increasing requirements of access rate, stability, and compatibility of current electronic equipment to the DRAM.
In this embodiment, the actual DQ eye width and the actual DQ eye height of the DQ signal need to be calculated, and the phase of the DQs signal and the phase of the DQ signal are adjusted accordingly, so as to ensure that the sampling phase of the DQs signal to the DQ signal is optimal. In the present embodiment, independent data training is performed for each of the write direction and the read direction of DRAM data.
When the main controller performs data training in a software training mode, data reading/writing access and data comparison are needed to be performed on the DRAM, and then the sampling phases of the DQS signal and the DQ signal are judged, so that the DRAM needs to write in one data. Referring to fig. 2, step S1 is executed to write the target data into the preset memory space of the memory. As shown in fig. 3, the main controller 20 has a storage area 21 and a buffer area 22, the storage area 21 stores target data, that is, data for comparison, and a preset storage space 26 is provided in the memory 25, and when the main controller 20 needs to write data into the memory 25, the data stored in the storage area 21 is first written into the buffer area 22, and then the data in the buffer area 22 is written into the preset storage space 26 of the memory 25.
Specifically, the clock frequency for writing data into the memory 25 by the main controller 20 is set to a lower clock frequency, for example, to the first clock frequency, so that the data path is insensitive to the phase relationship between the DQS signal and the DQ signal, and at this time, the main controller 20 can perform normal read and write access to the data in the memory 25. Then, the main controller 20 writes a certain amount of data, i.e., the target data, into the predetermined storage space 26 of the memory 25, and the length of the certain amount of data is usually determined. After the data is written, the main controller increases the clock frequency for reading and writing the data, for example, to the actually used clock frequency, where the frequency is the second clock frequency, and the second clock frequency is higher than the first clock frequency.
After writing the target data, step S2 is executed, and the main controller 20 reads the test data from the predetermined storage space 26. After the target data is written into the predetermined memory space 26, the main controller 20 reads the data of the predetermined memory space 26 through a plurality of DQ pins of the memory 25, and the read data is test data. The present embodiment calculates the boundary of the DQ eye pattern by comparing target data with test data.
Next, step S3 is executed to calculate the left and right boundaries of the DQ eye pattern in the read direction. Referring to fig. 4, step S11 is first executed to initialize the delay parameter of the DQ signal in the data reading direction, specifically, to set the delay parameter DQn _ del of the DQ signal in the data reading direction to the minimum value. Meanwhile, the adjustment gear of the delay parameter is set, and the adjustment gear of the delay parameter of the embodiment has a plurality of, for example, three gears, which are 1, 4 and 8 respectively, that is, the maximum gear is 8. Each adjustment of the delay parameter is 1 unit when the adjustment gear of the delay parameter is 1, 4 units when the adjustment gear of the delay parameter is 4, and 8 units when the adjustment gear of the delay parameter is 8. In the initial stage, the adjustment gear of the delay parameter is set to the maximum gear.
Then, step S12 is executed, and the main controller 20 reads the test data of the memory 25 and determines whether the read data is correct for the DQ signal of each DQ pin individually. Specifically, by performing an exclusive or calculation on the target data and the test data, when the calculation result of the exclusive or calculation is not 0, it indicates that the data BIT (BIT) indicates that the data comparison of the corresponding DQ pin is erroneous. Therefore, the error condition of the data bit corresponding to each DQ pin can be obtained. For example, if the number of DQ pins of the memory 25 is 32, the target data is 0x12345678, and the read test data is 0x92345670, the result of the xor calculation is 0x8000008, and thus the data of the 4 th DQ pin and the 32 th DQ pin can be found to be erroneous by comparison, that is, the result of the xor calculation is binary 1.
In this embodiment, after the main controller 20 reads the data of 32 DQ pins from the memory 25 each time, the exclusive or calculation may be performed on the data of 32 DQ pins at the same time, that is, the data comparison condition of each DQ pin may be obtained synchronously, so that the delay parameters of all DQ signals may be adjusted at the same time, and the training of all DQ signals is performed in parallel, thereby greatly saving the training time.
In step S12, it is necessary to record the data comparison result of each DQ pin under the current delay parameter, for example, DQn _ now, and to obtain the data comparison result under the previous delay parameter, for example, DQn _ last. If the comparison result of the target data and the test data is 0, namely the XOR calculation result of the target data and the test data is 0, the target data and the test data are the same; if the comparison result of the target data and the test data is 1, that is, the exclusive or calculation result of the target data and the test data is 1, it indicates that the target data is different from the test data. If the current alignment is the first alignment, DQn _ last is directly set to 1.
Then, step S13 is executed to determine the difference and identity between the target data and the test data under the current delay parameter and the difference and identity between the target data and the test data under the previous delay parameter, specifically, determine whether DQn _ now is 1 and DQn _ last is 0, if the conditions are met, step S14 is further executed to determine whether the adjustment gear of the current delay parameter is the minimum gear, if so, step S15 is executed to confirm that the left boundary of the DQ eye diagram is read.
If it is confirmed in step S14 that the currently adjusted gear of the delay parameter is not the minimum gear, it is necessary to perform step S19, to go back to the last delay parameter and decrease the adjusted gear of the delay parameter, and to perform step S20 to increase the delay parameter by the adjusted gear of the decreased delay parameter, and then to perform step S12.
If the determination result in the step S13 is no, step S16 is executed to determine whether DQn _ now is 0 and DQn _ last is 1, if the conditions are met, step S17 is further executed to determine whether the adjustment gear of the current delay parameter is the minimum gear, if yes, step S18 is executed to confirm that the right boundary of the DQ eye diagram is read. Then, step S21 is executed, the adjustment range of the delay parameter is set to the maximum adjustment range, and then step S20 is executed.
If it is confirmed in step S17 that the shift position of the current delay parameter is not the minimum shift position, it is necessary to perform step S19, go back to the last delay parameter and decrease the shift position of the delay parameter, perform step S20 to increase the delay parameter by the decreased delay parameter, and then perform step S12.
If the determination result in the step S16 is no, that is, the determination condition in the step S13 or step S16 is not satisfied, then step S20 is executed, the delay parameter is adjusted according to the original adjustment gear, for example, the delay parameter is adjusted according to the maximum gear, the delay parameter is continuously increased, the process returns to the step S12, the difference and agreement result between the target data and the test data under the current delay parameter and the difference and agreement result between the target data and the test data under the previous delay parameter are compared again, until the left boundary and the right boundary of all DQ eye diagrams are found.
Referring to fig. 5, the present embodiment obtains the left and right boundaries of the DQ eye pattern in the data reading direction by bisection. Specifically, step a1 is in an initial state, where the rising edges of the DQ eye pattern and the DQs signal do not overlap, so the main controller 20 cannot acquire correct data, and the result of the xor calculation is 1. Therefore, it is necessary to increase the delay parameter and increase the delay parameter by the maximum gear, and the position of the DQ eye pattern after increasing the delay parameter is shown in step a2, at this time, the rising edges of the DQ eye pattern and the DQs signal still do not overlap, so the delay parameter continues to be increased by the maximum gear.
At step A3, since the rising edge of the DQS signal overlaps the DQ eye pattern, the correct DQn signal is acquired, but since the adjustment step of the delay parameter is not the minimum step, the previous delay parameter needs to be moved back, and the adjustment step of the delay parameter needs to be reduced, for example, to the minimum step, at step a4, the delay parameter is adjusted at the reduced minimum step, and the delay parameter is adjusted at the adjusted step. In step a5, since the rising edge of the DQS signal overlaps the DQ eye pattern, and the correct DQn signal is acquired, and the shift of the delay parameter is the minimum shift, the right boundary DQn _ right of the DQ eye width is read. The DQn signal represents a DQ signal read by any one DQ pin of the 32 DQ pins, and DQn _ right represents a right boundary of a DQ eye pattern corresponding to one DQ pin. The DQ signal at any one DQ pin is used in the same way to calculate the left and right boundaries.
After calculating the right boundary of the DQ eye pattern, the left boundary of the DQ eye pattern also needs to be calculated, and in step a6, the adjustment gear of the delay parameter needs to be set to the maximum gear, and the delay parameter needs to be continuously added, as in steps a7 and A8. Since the rising edge of the DQS signal does not overlap the DQ eye pattern any more at step A8, correct data cannot be acquired, but since the adjustment step of the delay parameter is not the minimum step, it is necessary to move back to the previous delay parameter and decrease the adjustment step of the delay parameter, for example, to the minimum step, at step a9, the delay parameter is adjusted by decreasing to the minimum step, and the delay parameter is adjusted by the adjusted step.
In step a10, since the rising edge of the DQS signal no longer overlaps the DQ eye pattern and the shift of the delay parameter is the minimum shift, the left boundary DQn _ light of the DQ eye width is read. At this point, a scan of the DQ eye width is completed. Therefore, compared with the conventional method of scanning from left to right by using a single dispensing gear, the method of the embodiment can save more than half of scanning time and greatly reduce the time required by data training.
It should be noted that, in this embodiment, the left and right boundaries of the DQ eye diagram calculated by software are the boundaries corresponding to the dashed line Teye in fig. 1, and the upper and lower boundaries of the DQ eye diagram are the boundaries corresponding to the dashed line Veye in fig. 1, that is, the left and right boundaries, and the upper and lower boundaries form a rectangular frame, and only when the DQs signal passes through the rectangular frame, the main controller 20 can acquire a correct signal.
To this end, step S3 is completed, and then step S4 is executed to calculate the upper and lower boundaries of the DQ eye pattern in the data reading direction. Referring to fig. 6, step S31 is executed to initialize the reference voltage DQ _ vref of the DQ signal in the data reading direction, in this embodiment, all DQ pins share the same reference voltage. In the initial state, the reference voltage DQ _ vref of the DQ signal is set to a minimum value, and the reference voltage is continuously adjusted in the subsequent test process, specifically, the reference voltage is gradually increased.
Then, step S32 is executed, the main controller 20 reads the data in the preset memory space of the memory 25, obtains the test data, performs xor calculation on the test data and the target data, and determines whether the DQ signal of the corresponding DQ pin is correct according to the data bit. For example, the data comparison result of each DQ pin at the current reference voltage is recorded, for example, DQn _ now, and the data comparison result at the previous reference voltage needs to be obtained, for example, DQn _ last. If the comparison result of the target data and the test data is 0, namely the XOR calculation result of the target data and the test data is 0, the target data and the test data are the same; if the comparison result of the target data and the test data is 1, that is, the exclusive or calculation result of the target data and the test data is 1, it indicates that the target data is different from the test data. If the current alignment is the first alignment, DQn _ last is directly set to 1.
Next, step S33 is executed to determine the difference and identity result between the target data and the test data at the current reference voltage and the difference and identity result between the target data and the test data at the previous reference voltage, specifically, determine whether DQn _ now is 1 and DQn _ last is 0, if the condition is satisfied, confirm that the upper boundary of the DQ eye diagram is read, and end the eye-height scan of the DQ eye diagram. If the result of the determination in step S33 is no, step S35 is performed to determine whether DQn _ now is 0 and DQn _ last is 1, if this condition is satisfied, it is confirmed that the lower boundary of the DQ eye pattern is read, step S37 is performed to continue increasing the reference voltage, and step S32 is returned to.
If the determination result of step S35 is NO, step S37 is also performed to continue increasing the reference voltage, and the process returns to step S32.
Referring to fig. 7, in step a11, the reference voltage for the sampling of the DQ signal is set to the minimum value, and since the reference voltage is lower than the lower eye height limit of the DQ eye pattern, i.e., lower than the lower edge of Veye, the correct signal cannot be acquired, and the reference voltage is not the lower edge of the DQ eye pattern. After increasing the reference voltage, at step a12, the correct signal can be acquired and it is determined that the lower edge of the DQ eye pattern is read.
Subsequently, continuing to increase the reference voltage, at step a13, the correct signal can still be read, but increasing the reference voltage again, at step a14, the correct reference voltage cannot be read, and step a13 is considered to read the upper edge of the DQ eye pattern. Therefore, the sampling reference voltage of the DQ signal is adjusted from small to large by adjusting the reference voltage of the DQ signal, and the eye height data of the DQ signal is finally obtained by combining the comparison result of the target data corresponding to the DQ signal and the test data.
Up to this point, the eye width and eye height scanning of the DQ eye pattern in the read direction is completed, and then step S5 is executed to calculate the left and right boundaries of the DQ eye pattern in the data write direction. The eye width data training process of the DQ eye pattern in the data writing direction is basically the same as the eye width data training process of the DQ eye pattern in the data reading direction, and is different in that the data reading direction is to read data prestored in the memory 25 through the main controller 20 and perform data comparison, and when the data training in the data writing direction is performed, because the optimal sampling position of the DQ signal in the data reading direction is obtained through training, the data training in the data writing direction is to cyclically read and write a small piece of data into the memory 25 through the main controller 20, that is, the written target data is cyclically written, and the data volume is small. And finally, comparing the read data with the written data to judge the left and right boundaries of the written DQ eye pattern.
For example, when data is written, the target data size of each write is 1KB, and the target data size of the total write is 1MB, the main controller 20 writes 1KB of data to the predetermined storage space 26 1024 times in a loop.
Compared with the traditional data training method, the scheme of writing a large data into the memory 25 every time and completely comparing the whole data is adopted, in the embodiment, a small data is repeatedly written and read for many times in a circulating way and is finally compared with the target data, so that the data comparison time and the bubbles between commands of writing, reading and accessing the memory 25 can be greatly reduced, and the access pressure is increased. The error results of data reading and writing are accumulated, and since the data used in the middle process is the middle data left by the last reading and writing except the first written data in the reading and writing process is the known data, the error information in the previous reading and writing process can be retained, and finally after the number of times of reading and writing required by the test is reached, the error can be known whether the previous reading and writing process has errors or not by comparing the test data read for the last time with the target data.
As shown in FIG. 3, a small piece of target data is written into the buffer 22 of the host controller 20, and then the target data is written into the memory 25 in a loop, the more times the target data is written, the more reliable the test result is. And finally, reading the data stored in the memory 25, and performing exclusive-or calculation with the target data stored in the main controller 20 to obtain a data comparison result of each data bit. For example, 1MB of data needs to be written into the memory 25, with the method of the present embodiment, if 1MB of data is divided into 1KB of data to be rewritten 1024 times, the conventional method needs to compare 1MB of data, but the method of the present embodiment only needs to compare 1KB of data, which can save more than 99% of data comparison time, greatly reduce data comparison time, and improve data training efficiency.
Finally, step S6 is executed to calculate the upper and lower boundaries of the DQ eye pattern in the data writing direction, and the specific calculation method is the same as the calculation method of the upper and lower boundaries of the DQ eye pattern in the data reading direction, and is not described again.
It can be seen that the present embodiment reduces the data training time of the memory by three aspects: the method comprises the steps that data are read from a plurality of DQ pins at the same time and are subjected to XOR calculation, the signal comparison results of the plurality of DQ pins can be calculated in parallel once, delay parameters are adjusted rapidly through bisection, the time for calculating the left and right boundaries of a DQ eye diagram can be reduced greatly, and the third aspect is that during testing in the data writing direction, the data comparison time is reduced in a mode of circularly writing data, and the data training efficiency is improved.
The embodiment of the computer device comprises:
the computer device of this embodiment may be a main controller on an electronic device, and the computer device includes a processor, a program memory, and a computer program stored in the program memory and running on the processor, and when the processor executes the computer program, the processor implements the steps of the data training method of the memory.
For example, a computer program may be partitioned into one or more modules that are stored in a program memory and executed by a processor to implement the various modules of the invention. One or more of the modules may be a series of computer program instruction segments capable of performing certain functions, which are used to describe the execution of the computer program in the terminal device.
The Processor may be a Central Processing Unit (CPU), or may be other general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being the control center of the terminal device and connecting the various parts of the entire terminal device using various interfaces and lines.
The program memory may be used to store computer programs and/or modules, and the processor may perform various functions by operating on or executing the computer programs and/or modules stored in the program memory, as well as by invoking data stored in the program memory. The program memory may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program (such as a sound playing function, an image playing function, etc.) required by at least one function, and the like; the storage data area may store data created according to use of the electronic device, and the like. Additionally, the program memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
Computer-readable storage medium embodiments:
the computer program stored in the computer device may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, all or part of the processes in the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium and used by a processor to implement the steps of the data training method of the memory.
Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, recording medium, U.S. disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution media, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, in accordance with legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunications signals.
Finally, it should be emphasized that the present invention is not limited to the above-mentioned embodiments, such as the change of data of DQ pins, or the change of the number of times of cyclically writing data and the data amount of each writing data in the data writing direction test, and the like, and these changes should be included in the protection scope of the present invention.
Claims (10)
1. A method of data training of a memory, comprising:
writing target data into a preset storage space of a memory, and reading test data from the preset storage space through a plurality of DQ pins of the memory;
the method is characterized in that:
reading the test data from a plurality of the DQ pins, and judging whether the test data is the same as the target data: carrying out XOR calculation on the test data and the target data, and determining the difference and the sameness of the test data and the target data according to the result of the XOR calculation;
setting the delay parameter as a minimum value, gradually adjusting the delay parameter, and calculating left and right boundaries of a DQ eye diagram according to the similarity result of the test data and the target data under the current delay parameter and the similarity result of the test data and the target data under the previous delay parameter;
gradually adjusting the reference voltage, and calculating the upper and lower boundaries of the DQ eye diagram according to the difference and identity result of the test data and the target data under the current reference voltage and the difference and identity result of the test data and the target data under the previous reference voltage.
2. The data training method of the memory according to claim 1, wherein:
writing the target data into a preset storage space of the memory comprises: writing the target data at a first clock frequency during a data reading direction test;
reading test data from the preset memory space through a plurality of DQ pins of the memory comprises: reading test data from the preset storage space at a second clock frequency;
wherein the first clock frequency is lower than the second clock frequency.
3. The data training method of the memory according to claim 1, wherein:
writing the target data into a preset storage space of the memory comprises: and circularly writing the target data into the preset storage space for multiple times during the test of the data writing direction.
4. A data training method for a memory according to any one of claims 1 to 3, wherein:
the delay parameter has a plurality of adjustment steps;
gradually changing the delay parameter includes: and changing the delay parameter by using the maximum adjusting gear, returning the previous delay parameter when the test data is the same as the target data under the current delay parameter, reducing the adjusting gear by one gear, adjusting the delay parameter, and judging the difference between the test data and the target data under the delay parameter after the gear is reduced and adjusted.
5. The data training method of the memory according to claim 4, wherein:
calculating left and right boundaries of a DQ eye diagram according to a difference and identity result of the test data and the target data under a current delay parameter and a difference and identity result of the test data and the target data under a previous delay parameter comprises:
and if the difference and identity result of the test data and the target data under the current delay parameter is different from the difference and identity result of the test data and the target data under the previous delay parameter, and the adjustment gear of the current delay parameter is the minimum gear, determining that the current delay parameter corresponds to the left boundary or the right boundary of the DQ eye diagram.
6. A data training method for a memory according to any one of claims 1 to 3, wherein:
calculating the left and right boundaries of the DQ eye pattern includes:
the left and right boundaries of the DQ eye pattern in the data read direction are calculated, and then the left and right boundaries of the DQ eye pattern in the data write direction are calculated.
7. A data training method for a memory according to any one of claims 1 to 3, wherein:
gradually adjusting the reference voltage includes:
setting the reference voltage as a minimum value, and if the test data is different from the target data under the current reference voltage, increasing the reference voltage according to a preset amplitude;
if the test data is the same as the target data at the current reference voltage and the test data is different from the target data at the previous voltage, it is determined that the current reference voltage corresponds to the lower boundary of the DQ eye.
8. The data training method of the memory according to claim 7, wherein:
after confirming the lower boundary of the DQ eye diagram, continuing to adjust the reference voltage;
if the test data is different from the target data at a current reference voltage and the test data is the same as the target data at a previous voltage, it is determined that the current reference voltage corresponds to an upper boundary of the DQ eye.
9. Computer arrangement, characterized in that it comprises a processor and a program memory, said program memory storing a computer program which, when executed by the processor, carries out the steps of the method for data training of a memory according to any one of claims 1 to 8.
10. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program, when being executed by a processor, realizes the steps of the data training method of the memory according to any one of claims 1 to 8.
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