CN114283876A

CN114283876A - DDR signal quality test method, test device and test equipment

Info

Publication number: CN114283876A
Application number: CN202111603654.XA
Authority: CN
Inventors: 邓冏; 蒋增城
Original assignee: Shandong Dai Microelectronics Co ltd
Current assignee: Shandong Dai Microelectronics Co ltd
Priority date: 2021-12-24
Filing date: 2021-12-24
Publication date: 2022-04-05

Abstract

The application provides a DDR signal quality test method, a test device and test equipment, wherein the method comprises the following steps: obtaining a de-skew value of a DDR (double data rate) signal to be detected of a chip in a light-load working mode, and taking the de-skew value as an initial central value of window scanning of the DDR signal to be detected; controlling the de-skew value to change by taking the initial central value as a center until the chip cannot normally work to obtain a window boundary value; and determining the window size of the DDR signal to be measured according to the window boundary value. The method adjusts the de-skew value of the DDR signal to determine the maximum value and the minimum value of the de-skew value, so that the window size of the DDR signal is obtained, the larger the window of the DDR signal is, the better the signal quality of the DDR signal is, operations such as wire scraping and welding of a signal wire are not needed, the testing operation is simplified, and the problem that the DDR signal quality testing method in the prior art is too complex is solved.

Description

DDR signal quality test method, test device and test equipment

Technical Field

The application relates to the field of chip testing, in particular to a method and a device for testing DDR signal quality, a computer readable storage medium and testing equipment.

Background

With the fact that the SOC is more and more complex, the application of the DDR is more and more extensive, the DDR signal quality is an important guarantee of the stability of the SOC, the important representation of the DDR high-speed signal quality is the quality of an eye diagram, on one hand, the result of the DDR training eye integrated by the DDR PHY of the chip can only partially reflect the quality of the DDR signal eye diagram under light load of the system, and the eye diagram result of the actual work of the system has larger deviation with the result under light load; on the other hand, even if the eye pattern is measured under a heavy load of the system, the eye pattern measurement itself has various problems, such as different chips, PCB (Printed Circuit Board), DDR particles, and different application scene eye pattern qualities are different, the measurement result of the eye pattern is greatly affected by the measurement point of the eye pattern, the eye pattern requires much time and effort to perform measurement and result analysis, when the eye pattern is measured, the DDR signal lines need to be measured and positioned one by one, the PCB needs to be subjected to operations such as wire scraping and welding, and the operations more or less adversely affect the PCB.

Disclosure of Invention

The present application mainly aims to provide a method, a device, a computer-readable storage medium, and a device for testing DDR signal quality, so as to solve the problem that the method for testing DDR signal quality in the prior art is too complex.

According to an aspect of an embodiment of the present invention, there is provided a method for testing DDR signal quality, including: obtaining a de-skew value of a DDR (double data rate) signal to be detected of a chip in a light-load working mode, and taking the de-skew value as an initial central value of window scanning of the DDR signal to be detected; controlling the de-skew value to change by taking the initial central value as a center until the chip cannot normally work to obtain a window boundary value; and determining the window size of the DDR signal to be measured according to the window boundary value.

Optionally, the controlling the initial central value to change until the chip cannot work normally to obtain a window boundary value includes: controlling the de-skew value of the DDR signal to be detected to increase progressively from the initial central value until the chip cannot work normally, and obtaining the maximum value of a window; and controlling the de-skew value of the DDR signal to be detected to be decreased from the initial central value until the chip can not work normally, and obtaining the minimum value of the window.

Optionally, the step of controlling the de-skew value of the DDR signal to be tested to increase from the initial central value until the chip cannot work normally to obtain a maximum window value includes: controlling the de-skew value of the DDR signal to be tested to increase progressively from an initial central value to obtain a test intermediate value; determining whether the chip normally works under the condition that the de-skew value is the test intermediate value within first preset time; and under the condition that the chip works normally, controlling the de-skew value of the DDR signal to be tested to continuously increase from the test intermediate value until the chip cannot work normally, and determining the current test intermediate value as the maximum value of the window.

Optionally, when the chip cannot work normally, the method further includes: and controlling the chip to restart.

Optionally, before obtaining a de-skew value of a DDR to-be-detected signal of a chip in a light-load operating mode, and taking the de-skew value as an initial central value of window scanning of the DDR to-be-detected signal, the method further includes: and controlling the chip to enter a light-load working mode, wherein the light-load working mode is a working mode in which the load factor of the chip is smaller than a first preset value.

Optionally, after a de-skew value of a DDR to-be-detected signal of a chip in a light-load operating mode is obtained, and the de-skew value is used as an initial central value of window scanning of the DDR to-be-detected signal, the de-skew value is controlled to change with the initial central value as a center until the chip cannot normally operate, and before a window boundary value is obtained, the method further includes: and controlling the chip to enter a heavy-load working mode, wherein the heavy-load working mode is a working mode in which the load rate of the chip is greater than a second preset value, and the second preset value is greater than or equal to the first preset value.

Optionally, the chip cannot normally work, that is, a target serial port does not respond within a second preset time and/or the chip has a system error, and the target serial port is the serial port of the chip receiving the de-skew value.

According to another aspect of the embodiments of the present invention, there is also provided a device for testing DDR signal quality, including: the device comprises an acquisition unit, a data acquisition unit and a data processing unit, wherein the acquisition unit is used for acquiring a de-skew value of a DDR (double data rate) signal to be detected of a chip in a light-load working mode, and the de-skew value is used as an initial central value of window scanning of the DDR signal to be detected; the control unit is used for controlling the de-skew value to change by taking the initial central value as a center until the chip cannot normally work to obtain a window boundary value; and the determining unit is used for determining the window size of the DDR signal to be measured according to the window boundary value.

According to still another aspect of embodiments of the present invention, there is also provided a computer-readable storage medium including a stored program, wherein the program executes any one of the methods.

According to another aspect of the embodiments of the present invention, there is also provided a test apparatus, including a memory and a processor, where the memory stores a program, and the processor is configured to execute the program, where the program executes any one of the methods.

In the embodiment of the invention, in the DDR signal quality testing method, firstly, a de-skew value of a DDR signal to be tested of a chip in a light load working mode is obtained, and the de-skew value is used as an initial central value of window scanning of the DDR signal to be tested; then controlling the de-skew value to change by taking an initial central value as a center until the chip cannot normally work to obtain a window boundary value; and finally, determining the window size of the DDR signal to be measured according to the window boundary value. The larger the window of the DDR signal to be tested is, the better the signal quality of the DDR signal is, and compared with the prior art that the signal line is connected with a signal line for eye pattern measurement through an oscilloscope, the test method does not need to carry out operations such as signal line scraping and welding on a PCB, avoids the damage of the scraping and welding operations on the PCB of the chip in the test process, avoids the influence of different welding points on the test result, simplifies the test process, and improves the test accuracy.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 shows a schematic diagram of a DDR signal quality test method according to an embodiment of the application;

FIG. 2 shows a schematic diagram of a DDR signal quality test device according to an embodiment of the application;

fig. 3 shows a flow diagram for auto-scanning DDR windows according to an embodiment of the present application.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As mentioned in the background, the DDR signal quality testing method in the prior art is too complex, and in order to solve the above problems, the present application provides a testing method, a testing apparatus, a computer readable storage medium and a testing device for DDR signal quality.

According to an embodiment of the application, a DDR signal quality testing method is provided.

Fig. 1 is a flowchart of a method for testing DDR signal quality according to an embodiment of the present application. As shown in fig. 1, the method comprises the steps of:

s101, obtaining a de-skew value of a DDR (double data rate) signal to be detected of a chip in a light load working mode, and taking the de-skew value as an initial central value of window scanning of the DDR signal to be detected;

specifically, each DDR signal is internally provided with a delay chain, a de-skew value is a value of the delay chain, the configuration is to perform time sequence matching, in practical application, the de-skew value is stored in an internal register of a chip, the de-skew value stored in the internal register of the chip can be read through a serial port, and the obtained de-skew value of the DDR signal to be detected of the chip in a light load working mode is used as an initial central value of window scanning of the DDR signal to be detected.

S102, controlling the de-skew value to change by taking an initial central value as a center until the chip cannot normally work to obtain a window boundary value;

specifically, the de-skew value inside the chip can be changed by changing the value of the chip register, that is, the de-skew value is controlled to change by taking the initial central value as the center until the chip cannot normally work when the de-skew value changes to a certain value, and the value can be used as a window boundary value.

And step S103, determining the window size of the DDR signal to be measured according to the window boundary value.

Specifically, the window size of the DDR signal to be measured can be determined according to the window boundary value, and the window size can represent the signal quality of the DDR signal.

In the DDR signal quality test method, firstly, a de-skew value of a DDR signal to be tested of a chip in a light load working mode is obtained, and the de-skew value is used as an initial central value of window scanning of the DDR signal to be tested; then controlling the de-skew value to change by taking an initial central value as a center until the chip cannot normally work to obtain a window boundary value; and finally, determining the window size of the DDR signal to be measured according to the window boundary value. The larger the window of the DDR signal to be tested is, the better the signal quality of the DDR signal is, and compared with the prior art that the signal line is connected with a signal line for eye pattern measurement through an oscilloscope, the test method does not need to carry out operations such as signal line scraping and welding on a PCB, avoids the damage of the scraping and welding operations on the PCB of the chip in the test process, avoids the influence of different welding points on the test result, simplifies the test process, and improves the test accuracy.

It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.

In a specific embodiment of the present application, the Chip may be an SOC (System on Chip, SOC for short).

In an embodiment of the application, the controlling the initial central value to change until the chip cannot work normally to obtain a window boundary value includes: controlling the de-skew value of the DDR signal to be detected to increase progressively from the initial central value until the chip cannot work normally, and obtaining the maximum value of a window; and controlling the de-skew value of the DDR signal to be detected to be decreased from the initial central value until the chip can not work normally, and obtaining the minimum value of the window. Specifically, the window boundary value includes a window maximum value and a window minimum value, and a difference between the window maximum value and the window minimum value is calculated to obtain a window size of the DDR signal.

In an embodiment of the application, controlling the de-skew value of the DDR signal to be tested to be increased from the initial central value until the chip cannot normally work to obtain a maximum window value includes: controlling the de-skew value of the DDR signal to be tested to increase progressively from an initial central value to obtain a test intermediate value; determining whether the chip normally works under the condition that the de-skew value is the test intermediate value within first preset time; and under the condition that the chip works normally, controlling the de-skew value of the DDR signal to be tested to continuously increase from the test intermediate value until the chip cannot work normally, and determining the current test intermediate value as the maximum value of the window.

In this embodiment, of course, the de-skew value of the DDR signal to be tested may be controlled to decrease from the initial central value to obtain a test intermediate value; determining whether the chip normally works under the condition that the de-skew value is the test intermediate value within first preset time; under the condition that the chip works normally, controlling the de-skew value of the DDR signal to be tested to continuously decrease from the test intermediate value until the chip can not work normally, determining the current test intermediate value as the minimum value of a window, for example, after increasing or decreasing the de-skew value by a variation value, determining whether the chip normally operates within a first predetermined time, under the condition that the chip can work normally, the change value is continuously increased or decreased until the chip can not work normally within a first preset time after the change value is increased or decreased, therefore, the test intermediate value can be completely configured to be effective in the chip, the SOC can be ensured to work for a period of time under the configuration, the output of the chip is not abnormal or hung up, and the change values increased or decreased each time can be the same or different.

In the actual application process, the above variation value may be 1, but is not limited to 1, and may also be other feasible values, which may be specifically adjusted according to the actual application.

In another embodiment of the present application, when the chip cannot work normally, the method further includes: and controlling the chip to restart. For example, after the de-skew value of the DDR signal to be detected is controlled to increase from the initial central value until the chip cannot work normally and the window maximum value is obtained, the chip is controlled to restart, and after the de-skew value of the DDR signal to be detected is controlled to decrease from the initial central value until the chip cannot work normally and the window minimum value is obtained, the chip is controlled to restart.

Specifically, in the practical application process, the power switch of the SOC can be controlled through the programmable single chip microcomputer, because the DDR is a key unit of the system, in the process of scanning DDR signals, the system can be hung up when a signal boundary is scanned, and the SOC cannot automatically recover to work in this time, the single chip microcomputer is needed to control the power switch to enable the SOC to be powered off again, and the SOC is powered on to be started again.

In an embodiment of the application, the chip cannot normally work as a target serial port does not respond within a second preset time and/or the chip has a system error, the target serial port is the serial port of the chip receiving the de-skew value, and the chip is controlled to restart subsequently under the condition that the chip does not respond within the second preset time or the chip has the system error or the chip does not respond within the second preset time and the chip has the system error, so that the chip is further ensured to resume normal work as soon as possible.

In another embodiment of the application, before obtaining a de-skew value of a DDR signal to be tested of a chip in a light load operating mode and using the de-skew value as an initial central value of window scanning of the DDR signal to be tested, the method further includes: and controlling the chip to enter a light-load working mode, wherein the light-load working mode is a working mode in which the load factor of the chip is smaller than a first preset value. In this embodiment, when the initial central value of the window scanning of the DDR signal to be measured is determined, the chip is controlled to perform the light load mode, so that it is ensured that the read initial central value of the DDR signal does not exceed the boundary value, and the chip entering the heavy load mode with the initial central value does not fail to operate normally.

In order to ensure that the test can be performed quickly and the test result is reliable, in another embodiment of the present application, after a de-skew value of a DDR to-be-tested signal of a chip in a light-load operating mode is obtained and is used as an initial central value of window scanning of the DDR to-be-tested signal, the de-skew value is controlled to change with the initial central value as a center until the chip cannot work normally and a window boundary value is obtained, and the method further includes: and controlling the chip to enter a heavy-load working mode, wherein the heavy-load working mode is a working mode in which the load rate of the chip is greater than a second preset value, and the second preset value is greater than or equal to the first preset value.

In the practical application process, after the single chip microcomputer is started or the SOC is restarted, the single chip microcomputer can utilize interfaces such as a serial port and the like to automatically carry out operations such as video playing, games or browsers and the like, control the chips to carry out a heavy-load working mode, test the DDR signal quality in the SOC heavy-load working mode, can quickly test, quickly locate a problem signal and do not damage a PCB, and test in the SOC heavy-load working mode can ensure the reliability of a test result.

It should be noted that, in an actual application process, the DDR signal to be tested includes a plurality of signals, for example, an AC (Address & Command) signal and a DQ (DQ/DQs/DQSB) signal, and each DDR signal to be tested is sequentially tested by the above method, so that the window size of all DDR signals to be tested can be obtained to represent the signal quality of each DDR signal to be tested.

In a specific embodiment of the application, all DDR signals to be tested may be configured according to a preset sequence, and then all DDR signals to be tested are tested according to the preset sequence, specifically, after the test of the first DDR signal to be tested is completed according to the above-mentioned test method, it is determined whether there is any untested DDR signal to be tested, if so, the de-skew value of the untested DDR signal to be tested of the chip in the light load operating mode is obtained as the initial central value of the window scan of the untested DDR signal to be tested, the next round of test is started until all DDR signals to be tested are tested, the flow is confirmed to be finished, and a test report is output.

The embodiment of the present application further provides a device for testing DDR signal quality, and it should be noted that the device for testing DDR signal quality according to the embodiment of the present application may be used to execute the method for testing DDR signal quality according to the embodiment of the present application. The DDR signal quality test device provided in the embodiment of the present application is described below.

Fig. 2 is a schematic diagram of a DDR signal quality testing device according to an embodiment of the present application. As shown in fig. 2, the apparatus includes:

the obtaining unit 10 is configured to obtain a de-skew value of a DDR to-be-detected signal of a chip in a light-load working mode, and use the de-skew value as an initial central value of window scanning of the DDR to-be-detected signal;

the first control unit 20 is used for controlling the de-skew value to change by taking an initial central value as a center until the chip cannot work normally to obtain a window boundary value;

and the determining unit 30 is configured to determine the window size of the DDR signal to be tested according to the window boundary value.

In the DDR signal quality testing device, an acquisition unit acquires a de-skew value of a DDR signal to be tested of a chip in a light load working mode, and the de-skew value is used as an initial central value of window scanning of the DDR signal to be tested; the control unit controls the de-skew value to change by taking an initial central value as a center until the chip cannot normally work to obtain a window boundary value; and the determining unit determines the window size of the DDR signal to be measured according to the window boundary value. The larger the window size of the DDR signal to be tested is, the better the signal quality of the DDR signal is, and compared with the prior art that the signal line is connected with a signal line for eye pattern measurement through an oscilloscope, the test method does not need to carry out operations such as signal line scraping and welding on the PCB, avoids damage of the scraping and welding operations of the PCB of the chip in the test process, avoids influences of different welding points on the test result, simplifies the test process, and improves the test accuracy.

In an embodiment of the application, the control unit includes a first control module and a second control module, where the first control module is configured to control a de-skew value of the DDR signal to be tested to increase from the initial central value until the chip cannot normally operate, so as to obtain a maximum window value; the second control module is used for controlling the de-skew value of the DDR signal to be detected to be decreased from the initial central value until the chip can not work normally, and the minimum value of the window is obtained. Specifically, the window boundary value includes a window maximum value and a window minimum value, and a difference between the window maximum value and the window minimum value is calculated to obtain a window size of the DDR signal.

In an embodiment of the application, the first control module includes a first control submodule, a determination submodule and a second control submodule, wherein the first control submodule is configured to control a de-skew value of the DDR signal to be tested to increase from an initial central value, so as to obtain a test intermediate value; determining whether the chip normally works under the condition that the de-skew value is the test intermediate value within first preset time; and the second control submodule is used for controlling the de-skew value of the DDR signal to be tested to continuously increase from the test intermediate value under the condition that the chip normally works until the chip cannot normally work, and determining the current test intermediate value as the maximum value of the window.

In this embodiment, of course, the de-skew value of the DDR signal to be tested may be controlled to decrease from the initial central value to obtain a test intermediate value; determining whether the chip normally works under the condition that the de-skew value is the test intermediate value within first preset time; and under the condition that the chip works normally, controlling the de-skew value of the DDR signal to be tested to continuously decrease from the test intermediate value until the chip cannot work normally, and determining the current test intermediate value as the window minimum value.

In order to ensure that the chip can resume normal operation again, in another embodiment of the present application, when the chip cannot operate normally, the apparatus further includes a second control unit, where the second control unit is configured to control the chip to restart. For example, after the de-skew value of the DDR signal to be detected is controlled to increase from the initial central value until the chip cannot work normally and the window maximum value is obtained, the chip is controlled to restart, and after the de-skew value of the DDR signal to be detected is controlled to decrease from the initial central value until the chip cannot work normally and the window minimum value is obtained, the chip is controlled to restart.

In another embodiment of the application, the device further includes a third control unit, where the third control unit is configured to control the chip to enter a light-load working mode before obtaining a de-skew value of the DDR signal to be tested in the light-load working mode of the chip and taking the de-skew value as an initial central value of window scanning of the DDR signal to be tested, where the light-load working mode is a working mode in which a load factor of the chip is smaller than a first predetermined value.

In order to ensure that the test can be performed quickly and the test result is reliable, in another embodiment of the present application, the device further includes a fourth control unit, where the fourth control unit is configured to, after obtaining a de-skew value of a DDR signal to be tested of a chip in a light-load operating mode, and taking the de-skew value as an initial central value of window scanning of the DDR signal to be tested, control the de-skew value to change around the initial central value until the chip cannot work normally, and before obtaining a window boundary value, control the chip to enter a heavy-load operating mode, where the heavy-load operating mode is an operating mode in which a load factor of the chip is greater than a second predetermined value, and the second predetermined value is greater than or equal to the first predetermined value.

In order to make the technical solutions of the present application more clearly understood and more obvious to those skilled in the art, the following description is given with reference to specific embodiments:

example 1

As shown in fig. 3, the method for testing the DDR signal quality includes the following specific steps:

step 1: the programmable single chip microcomputer is used for controlling a power switch of the SOC (namely a chip), because DDR is a key unit of a system, the system is hung dead when a signal boundary is scanned in the process of scanning DDR signals, and the SOC cannot automatically recover to work at the time, and the single chip microcomputer is required to control the power switch to enable the SOC to be powered off and powered on again to recover starting;

step 2: reading DDR signals by using interfaces such as serial ports of the SOC and the like, reading de-skew values of the DDR signals, automatically updating the values to a script, and taking the values as initial central values of DDR window scanning;

and step 3: the single chip microcomputer controls an SOC power switch, monitors the result printed by the SOC serial port at regular time, such as the fact that the serial port has no response for a long time or keywords with system errors occur, and restarts the SOC;

and 4, step 4: after the single chip microcomputer starts or restarts the SOC, the SOC automatically performs operations such as video playing, games or browsers and the like by using interfaces such as a serial port and the like, and enters a heavy-load working mode;

and 5: executing addition and subtraction operations of DDR signals from a central value according to a preset sequence of the script, confirming signals of next operation according to a script execution result, for example, assuming that a first test signal is DQ0 in a write direction, sequentially subtracting 1 (namely a change value) from left, then encountering system hang-up, obtaining a left boundary of DQ0 in the write direction, after SOC restarts, determining a right boundary of DQ0 in the write direction in the next test according to the measured result by the script, namely sequentially adding 1 from right until the system hang-up obtains a right boundary of DQ0 in the write direction, after SOC restarts again, determining a left boundary of DQ1 in the write direction in the next test according to the measured result by the script, sequentially executing according to the preset sequence of the script until all DDR signals are tested, and completing all test jumps to step 7;

step 6: the method comprises the steps of updating the value of a signal to be tested through interfaces such as a serial port of the SOC, and the like, and updating the configuration of the DDR signal to the SOC by subtracting 1 from the central value or adding 1 to the right according to a fixed time interval, wherein a certain time interval (namely first preset time) is needed, so that the configuration can be guaranteed to be completely applied to the SOC, and the configuration can be proved to be effective DDR configuration only by running for at least a period of time, abnormal output or hang-up of the SOC system cannot be caused, and the reliability of a test result is guaranteed. If the serial port does not respond for a long time or the keyword or de-skew value with system error is added to the maximum value or reduced to the minimum value, returning to the step 3 to restart the SOC;

and 7: the SOC finishes scanning all windows and collects the printing results;

and 8: and automatically processing the printing result by using the script, and outputting the boundary values of all the signals to be tested of the DDR to an Excel table.

Example 2

The eye pattern measurement is limited by instrument test conditions, so that the measurement cannot be carried out at high and low temperature limit temperatures, when a DDR problem needs to be positioned when a high and low temperature limit temperature system is abnormal, the eye pattern measurement cannot be carried out, the window is dynamically scanned through a script without temperature limitation, and DDR window scanning can be carried out under any temperature condition. For example, the PCB high-low temperature copying machine has low-temperature hanging limit, the DDR stability problem can be known through preliminary investigation, and what kind of DDR or what signal has a problem needs to be further positioned at the time, so that stable and accurate positioning can be performed in the following modes:

for example, the low-temperature copying machine comprises 10 PCB boards, one board 6 is always hung at low temperature, and the other 9 boards are normal at low temperature;

the method comprises the steps that 10 pieces of DDR window information of a PCB are sequentially obtained by utilizing an automatic script dynamic scanning window, the obtained window information is shown in a table 1, only a small part of scanning results is extracted from the table 1 as an example, a register represents DDR signals, each signal corresponds to a unique register, the read value is a test value of the DDR signal in a light-load working mode and is pre-configured in the register to serve as an initial central value of the test window, the maximum value is a window maximum value obtained by scanning in a heavy-load working mode, the minimum value is a window minimum value obtained by scanning in the heavy-load working mode, the window maximum value subtracts the window minimum value to obtain a window size value, and the window central value is a central value of the window obtained by scanning in the heavy-load working mode.

TABLE 1

Register with a plurality of registers	Reading value	Maximum value	Minimum value	Window size	Center value of window
						0x1e6c2fdc	0x9	0xe	0x2	12	8
0x1e6c2ccc	0x11	0x17	0xb	12	17
						0x1e6c2d20	0x13	0x18	0xd	11	18.5
0x1e6c2e4c	0x15	0x1a	0xf	11	20.5
						0x1e6c2ea0	0x17	0x1b	0x13	8	23
0x1e6c2cc8	0x1a	0x1e	0x15	9	25.5
						0x1e6c2d1c	0x1a	0x1e	0x15	9	25.5
0x1e6c2e48	0x1a	0x1e	0x18	6	27
						0x1e6c2e9c	0x1a	0x1d	0x16	7	25.5

Firstly, performing comparative analysis according to window information results of 10 PCBs as an example in Table 1, finding that a window in a DDR signal of a board 6 is obviously smaller than DDR signals of other PCBs through the comparative analysis, so that the situation that the board 6 has a problem can be determined, then comparing all the DDR signals of the board 6 with DDR signals of other boards one by one, knowing that a window value of a certain DDR signal is obviously smaller than other PCBs, and determining that the DDR signal has a problem, finally comparing the DDR signals of the board 6 and other PCBs at normal temperature, comparing the window sizes of the DDR signal of the board 6 and other DDR signals of the board 6, and finally positioning to obtain a specific problem causing the window size of the DDR signal, so that a specific reason of system abnormality can be obtained. Therefore, the final test result can be quickly obtained according to the test method, the problem of which DDR signal is abnormal in the system can be quickly positioned according to the test result, and the test efficiency of the chip system is improved.

The DDR signal quality testing device comprises a processor and a memory, wherein the acquisition unit, the first control unit, the determination unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.

The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. The kernel can be set to be one or more than one, and the problem that a DDR signal quality testing method in the prior art is too complex is solved by adjusting kernel parameters.

The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.

An embodiment of the present invention provides a computer-readable storage medium, on which a program is stored, where the program, when executed by a processor, implements the method for testing DDR signal quality.

The embodiment of the invention provides a test device, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein the processor at least realizes the following steps when executing the program:

s102, controlling the de-skew value to change by taking the initial central value as a center until the chip can not work normally to obtain a window boundary value;

The electronic device herein may be a server, a PC, a PAD, a mobile phone, etc.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit may be stored in a computer-readable storage medium if it is implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a computer-readable storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned computer-readable storage media comprise: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

in the method, the device and the equipment for testing the DDR signal quality, firstly, a de-skew value of a DDR signal to be tested of a chip in a light load working mode is obtained, and the de-skew value is used as an initial central value of window scanning of the DDR signal to be tested; then controlling the de-skew value to change by taking an initial central value as a center until the chip cannot normally work to obtain a window boundary value; and finally, determining the window size of the DDR signal to be measured according to the window boundary value. The larger the window size of the DDR signal to be tested is, the better the signal quality of the DDR signal is, and compared with the prior art that the signal line is connected with a signal line for eye pattern measurement through an oscilloscope, the test method does not need to carry out operations such as signal line scraping and welding on the PCB, avoids damage of the scraping and welding operations of the PCB of the chip in the test process, avoids influences of different welding points on the test result, simplifies the test process, and improves the test accuracy.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A DDR signal quality test method is characterized by comprising the following steps:

obtaining a de-skew value of a DDR (double data rate) signal to be detected of a chip in a light-load working mode, and taking the de-skew value as an initial central value of window scanning of the DDR signal to be detected;

controlling the de-skew value to change by taking the initial central value as a center until the chip cannot normally work to obtain a window boundary value;

and determining the window size of the DDR signal to be measured according to the window boundary value.

2. The method of claim 1, wherein the controlling the initial central value to change until the chip fails to work normally to obtain a window boundary value comprises:

controlling the de-skew value of the DDR signal to be detected to increase progressively from the initial central value until the chip cannot work normally, and obtaining the maximum value of a window;

and controlling the de-skew value of the DDR signal to be detected to be decreased from the initial central value until the chip can not work normally, and obtaining the minimum value of the window.

3. The method as claimed in claim 2, wherein controlling the de-skew value of the DDR signal under test to increase from the initial central value until the chip fails to operate normally, and obtaining a maximum window value comprises:

controlling the de-skew value of the DDR signal to be tested to increase progressively from an initial central value to obtain a test intermediate value;

determining whether the chip normally works under the condition that the de-skew value is the test intermediate value within first preset time;

and under the condition that the chip works normally, controlling the de-skew value of the DDR signal to be tested to continuously increase from the test intermediate value until the chip cannot work normally, and determining the current test intermediate value as the maximum value of the window.

4. The method of claim 1, wherein when the chip is not operating properly, the method further comprises:

and controlling the chip to restart.

5. The method as claimed in claim 1, before obtaining a de-skew value of a DDR signal under test of a chip in a light load operation mode, and using the de-skew value as an initial central value of a window scan of the DDR signal under test, the method further comprises:

and controlling the chip to enter a light-load working mode, wherein the light-load working mode is a working mode in which the load factor of the chip is smaller than a first preset value.

6. The method as claimed in claim 5, wherein after obtaining a de-skew value of a DDR test signal of a chip in a light load operation mode, and using the de-skew value as an initial central value of a window scan of the DDR test signal, the method further comprises controlling the de-skew value to change around the initial central value until the chip fails to operate normally, and before obtaining a window boundary value:

and controlling the chip to enter a heavy-load working mode, wherein the heavy-load working mode is a working mode in which the load rate of the chip is greater than a second preset value, and the second preset value is greater than or equal to the first preset value.

7. The method according to any one of claims 1 to 6, wherein the chip fails to work normally, and the target serial port is a serial port of the chip receiving the de-skew value and has no response within a second preset time and/or the chip has a system error.

8. A DDR signal quality testing apparatus, comprising:

the device comprises an acquisition unit, a data acquisition unit and a data processing unit, wherein the acquisition unit is used for acquiring a de-skew value of a DDR (double data rate) signal to be detected of a chip in a light-load working mode, and the de-skew value is used as an initial central value of window scanning of the DDR signal to be detected;

the first control unit is used for controlling the de-skew value to change by taking the initial central value as a center until the chip cannot normally work to obtain a window boundary value;

and the determining unit is used for determining the window size of the DDR signal to be measured according to the window boundary value.

9. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored program, wherein the program performs the method of any one of claims 1 to 7.

10. A test device comprising a memory storing a program and a processor for executing the program, wherein the program when executed performs the method of any one of claims 1 to 7.