CN114090354A

CN114090354A - Memory module screening method and testing device

Info

Publication number: CN114090354A
Application number: CN202111342711.3A
Authority: CN
Inventors: 黄学楼
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-02-25

Abstract

The invention provides a memory module screening method and a testing device, wherein the memory module screening method comprises the following steps: uniformly selecting a plurality of entity blocks to be tested from a plurality of entity surfaces of entity grains to be tested; carrying out erasure test on a plurality of entity blocks to be tested one by one, and constructing a bad block table for recording the erasure test result; and performing write-read test on the passed entity blocks to be tested one by one according to the result of the erase test in the bad block table, and recording the result of the write-read test in the bad block table. Therefore, the physical crystal grains of the memory module can be rapidly screened and detected before being packaged into the memory module, whether the current physical crystal grains can meet the use standard of a subsequently used memory storage device or not is rapidly identified, and if the current physical crystal grains do not meet the use standard, the current physical crystal grains can be blocked before being packaged, so that the subsequent packaging cost is saved, and the loss is reduced.

Description

Memory module screening method and testing device

Technical Field

The present invention relates to memory management technologies, and in particular, to a method for screening memory modules and a test apparatus.

Background

The crystal grain of the memory module is determined to generate bad blocks in the production process because of the manufacturing process and the storage principle, the crystal grain packaged into the memory module is selected differently based on different actual terminal products, and in the prior art, whether the current crystal grain can meet the use standard of a subsequently used memory storage device or not can not be identified quickly before the crystal grain is packaged into the memory module, so that the packaged memory module has uneven quality, good chips and poor chips are mixed together for use, and great risk is brought to a user of the memory module.

Disclosure of Invention

The invention provides a memory module screening method and a memory module testing device, and aims to solve the technical problems that whether current crystal grains can meet the use standard of a subsequently used memory storage device or not can not be quickly identified before the crystal grains are packaged into a memory module, so that the packaged memory module has uneven quality and brings great risk to a memory module user in the prior art.

An embodiment of the present invention provides a memory module screening method for a memory storage device, wherein the memory storage device comprises a memory module, the memory module comprises at least one physical die, the physical die comprises a plurality of physical faces, each of the physical faces comprises a plurality of physical blocks, each of the physical blocks comprises a plurality of physical pages, the memory module screening method comprises: uniformly selecting a plurality of entity blocks to be tested from a plurality of entity surfaces of entity grains to be tested; performing erasure test on the plurality of entity blocks to be tested one by one, and constructing a bad block table for recording the erasure test result; and performing write-read tests on the solid blocks to be tested, the result of which is the passing of the erase test in the bad block table, one by one, and recording the result of the write-read tests in the bad block table.

The embodiment of the invention further provides a testing device, which comprises a memory controller, wherein the memory controller is electrically connected with the memory module, and the memory controller is used for executing the memory module screening method.

Based on the above, first, a plurality of solid blocks to be tested are uniformly selected from a plurality of solid faces of the solid grains to be tested. Then, a plurality of entity blocks to be tested are subjected to an erasure test one by one, and a bad block table for recording the result of the erasure test is constructed. And finally, performing write-read tests on the passed entity blocks to be tested one by one according to the result of the erase test in the bad block table, and recording the write-read test result in the bad block table. Therefore, the physical crystal grains of the memory module can be rapidly screened and detected before being packaged into the memory module, whether the current physical crystal grains can meet the use standard of a subsequently used memory storage device or not is rapidly identified, and if the current physical crystal grains do not meet the use standard, the current physical crystal grains can be blocked before being packaged, so that the subsequent packaging cost is saved, and the loss is reduced.

Drawings

FIG. 1 is a schematic diagram of a memory test system according to an embodiment of the invention;

FIG. 2 is a diagram illustrating a physical die within a memory module according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating uniform picking of a plurality of solid blocks to be tested on a plurality of solid faces of a solid die to be tested according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a newly created bad block table according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a bad block table after an erase test is completed, according to an embodiment of the invention;

FIG. 6 is a diagram illustrating a bad block table after the write-read test ends according to an embodiment of the invention;

FIG. 7 is a flow chart illustrating a memory module screening method according to an embodiment of the invention.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic diagram of a memory test system according to an embodiment of the invention. Referring to fig. 1, a memory test system 10 includes a host 11, a memory storage device 12 and a test device 13. The host 11 may be any type of computer system. For example. The host 11 may be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, and a digital camera. The memory storage device 12 is used to store data from the host 11 or the test device 13. For example, the memory storage device 12 may include a solid state disk, a U-disk, a memory card, or other type of non-volatile storage device. The host 11 may be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCI Express), a Universal Serial Bus (USB), or other types of connection interfaces. Thus, the host 11 may store data to the memory storage device 12 and/or read data from the memory storage device 12.

The test apparatus 13 includes a memory controller 131, and the memory storage apparatus 12 includes a memory module 121. The memory module 121 is used for storing data. The memory module 121 may include a rewritable nonvolatile memory module. The memory module 121 includes a memory cell array. The memory cells in the memory module 121 store data in the form of voltages. For example, the memory module 121 may include a Single Level Cell (SLC) NAND flash memory module, a Multi-Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

The memory controller 131 is electrically connected to the memory module 121. The memory controller 131 may be used to control the memory storage device 12. For example, the memory controller 131 can control the host 11 and the memory module 121 for data access and data management. For example, the memory controller 131 may include a Central Processing Unit (CPU), or other Programmable general purpose or special purpose microprocessor, Digital Signal Processor (DSP), Programmable Logic controller (ASIC), Programmable Logic Device (PLD), or other similar Device or combination thereof.

In one embodiment, memory controller 131 is also referred to as a flash memory controller. In one embodiment, the memory module 121 is also referred to as a flash memory module. The memory module 121 can receive a sequence of instructions from the memory controller 131 and access the memory cells according to the sequence of instructions.

FIG. 2 is a diagram illustrating a physical die within a memory module according to an embodiment of the invention. Referring to fig. 2, the memory module 121 includes a plurality of physical dies 2 and is used for non-volatile data storage. For example, each physical die 2 includes a plurality of physical faces 21, each physical face 21 includes a plurality of physical blocks 211, and each physical block 211 includes a plurality of physical pages 2111. For example, the solid grain 2 in fig. 3 includes 2 solid faces 21, each solid face 21 includes 18 solid blocks 211, and each solid block 211 includes 10 solid pages 2111. Further, the solid crystal grains 2 may be divided into 4 or 8 solid planes 21 having other sizes. Multiple physical pages 2111 in one physical block 211 may be programmed simultaneously to store data. In addition, the stored data of all the physical pages 2111 in one physical block 211 can be erased at the same time.

Referring to fig. 3, which is a schematic diagram illustrating a plurality of physical blocks to be tested uniformly selected among a plurality of physical surfaces 21 of a physical die to be tested according to an embodiment of the present invention, in an embodiment, a memory controller 131 may uniformly select a plurality of physical blocks 211 among a plurality of physical surfaces 21 of a physical die 2 to be tested as a plurality of physical blocks 211(i) to be tested. i can be any positive integer between 1 and A, and A can be any positive integer greater than 1. Each of the physical blocks to be tested 211(1) - (211A) includes a plurality of physical pages.

In one embodiment, the memory controller 121 may select the physical blocks 211(i) to be tested in units of physical planes 21, and a plurality of preset positions of each physical plane 21. At least one block 211(i) to be tested is selected from each preset position to obtain a plurality of blocks 211(1) - (211A) to be tested. This is done to make the selected solid block 211(i) to be tested more representative and to further reflect the quality characteristics of the solid die 2 to be tested. Referring to fig. 2, the solid die 2 to be tested is divided into two solid surfaces 21, and the plurality of solid blocks 211(1) to 211(a) to be tested in fig. 3 are selected from the two solid surfaces 21, and the selected solid blocks 211(1) to 211(a) to be tested are also uniformly distributed in each solid surface 21, i.e. the selected solid blocks 211(i) to be tested are as representative as possible in the corresponding solid surface 21.

In an embodiment, the plurality of predetermined positions may include any combination of the front region of the solid surface 21, the middle region of the solid surface 21, the rear region of the solid surface 21, the left region of the solid surface 21, and the right region of the solid surface 21. That is, the entity blocks 211 in the front, middle, rear, left and right positions of the entity plane 21 are selected, not limited to the entity blocks 211 in a certain area or certain areas of the entity plane 21. The aforementioned plurality of preset positions may further include any combination of all preset columns of the entity surface 21 and all preset rows of the entity surface 21, where the preset columns may be even columns or odd columns or some multiple number of columns of the current entity surface 21; the predetermined rows may also be even or odd rows or some multiple of rows of the current physical surface 21, so that the selected physical blocks 211(i) to be tested are representative in position in the corresponding physical surface 21.

In an embodiment, the electrical connection between the physical die to be tested and the testing device 13 is specifically that probe pins on the testing device are connected to a lead frame of the physical die to be tested, and pins of the lead frame of the physical die to be tested are connected to PADs (PAD) in the physical die to be tested through a wire bonding process, so as to electrically connect the testing device 13 and the physical die to be tested, thereby facilitating subsequent operations.

Fig. 4 is a schematic diagram of a newly created bad block table according to an embodiment of the present invention. Referring to fig. 5, a bad block table is constructed, and the test data and the quality information of the entity blocks to be tested 211(1) to 211(a) can be recorded in a list form, the sequence numbers 211(1) to 211(a) are the sequence of the entity blocks to be tested in the bad block table, the first square after each sequence number 211(i) is used for recording the result of the erase test of the subsequent corresponding entity block to be tested 211(i), and the second square after each sequence number 211(i) is used for recording the result of the write-read test of the subsequent corresponding entity block to be tested 211 (i). Fig. 4 is a schematic diagram for convenience of explaining the operation principle of the bad block table of the present application, and is not an actual representation of the bad block table.

Fig. 5 is a schematic diagram of a bad block table after the erase test ends according to the embodiment of the present invention. Referring to fig. 5, in an embodiment, the memory controller 131 may perform erase tests on the plurality of entity blocks 211(1) to be tested 211(a) one by one, and record the result of the erase test of each entity block 211(i) to be tested in the constructed bad block table. The process of recording the result of the erase test of each entity block 211(i) to be tested in the bad block table may be to perform the erase test while recording the result of the erase test, that is, after each entity block 211(i) to be tested is tested, the result of the erase test of the corresponding entity block 211(i) to be tested is recorded.

Referring to fig. 5, in an embodiment, after the memory controller 131 issues the erase command to the plurality of to-be-tested entity blocks 211(1) to 211(a), the plurality of to-be-tested entity blocks 211(1) to 211(a) are erased one by one according to the erase command, and when the current to-be-tested entity blocks 211(1) to 211(a) are successfully erased, the result of the erase test of the current to-be-tested entity block 211(i) is recorded as pass (which may be marked as 1) in the bad block table. And when the erase test of the physical block to be tested currently occurs, recording the result of the erase test of the physical block to be tested 211(i) currently as not passing (which can be marked as 0) in the bad block table. Specifically, if the erase error occurs in the current physical block to be tested, the physical block to be tested 211(i) in which the erase error occurs may be marked, and the physical address information of the physical block to be tested 211(i) may be recorded in the bad block table. Illustratively, the flag may be a value other than 0xFF written to the first byte of the data area and free area of the first page of the physical block 211(i) to be tested and a value other than 0xFF written to the first byte of the data area and free area of the last page.

Fig. 6 is a schematic diagram of a bad block table after the write-read test ends according to an embodiment of the present invention. Referring to fig. 6, in an embodiment, the memory controller 131 may perform write-read tests on the entity blocks 211(i) to be tested that pass the erase test in the bad block table one by one, and record the write-read test result of the corresponding entity block 211(i) to be tested in the bad block table. The write-read test is to write data into the erasable entity block 211(i) to be tested, read the data, and compare the written data with the read data to obtain the corresponding result of the write-read test. Thus, when the memory controller 131 performs the write-read test on the physical block to be tested 211(i), only the physical block to be tested 211(i) in the bad block table whose erase test result is passed is tested. This is because the physical block to be tested 211(i) in the bad block table which has failed as a result of the erase test is determined to be a bad block, and further write-read test is not required. I.e. for the entity block to be tested 211(i) in fig. 6 for which the result of the erase test is failed (i.e. the first square is marked 0), the second square does not need to record the result of the write-read test.

In an embodiment, referring to fig. 6, after the data write instruction is issued to the entity block to be tested 211(i) which passes the erase test result in the bad block table, the memory controller 131 performs the data write operation on the current entity block to be tested 211(i) according to the data write instruction, so as to write the preset data. Then, after sending a data reading comparison instruction to the entity block to be tested 211(i) which has performed the data writing operation, performing a data reading comparison operation on the entity block to be tested 211(i) which has performed the data writing operation according to the data reading comparison instruction, so as to read the stored data in the entity block to be tested 211(i) which has performed the data writing operation and compare the stored data with the preset data. Finally, if the comparison result is inconsistent, the result of the write-read test of the current entity block 211(i) to be tested is recorded as failed (which may be marked as 0) in the bad block table. If the comparison result is consistent, the result of the write-read test of the current entity block 211(i) to be tested is recorded as pass (which may be marked as 1) in the bad block table.

Specifically, the control module of the testing apparatus includes a correction unit, which can be used for writing preset data in the testing apparatus into the solid block 211(i) to be tested and accurately storing the preset data, and generally, the correction capability is used to express that the written data can be accurately stored into the solid page of the solid block 211(i) to be tested, such as 4bit, 8bit, and 16bit, which represents the correction capability of the correction unit and represents that data errors of 4bit, 8bit, and 16bit can be realized. The correction unit generally employs ECC correction, and when data is written into the physical block 211(i) to be tested, the corresponding ECC code is also saved. When the data just stored is read back again, the stored ECC code is compared with the ECC code generated when the data was read. If the two codes are not the same, they are decoded to determine which bit in the data is incorrect.

In practice, there will be a threshold number of error bits per block, i.e. ECC correction capability, due to the presence of ECC. If the ECC correction capability is 16 bits, then a number of block error bits below this number may be considered to pass the test and may be used. Therefore, the above writing and reading test may specifically be to perform writing and reading operations on the entity block to be tested, determine a first bit flipping number in a current page in the entity block to be tested, determine whether the first bit flipping number exceeds a first preset threshold, if the first bit flipping number exceeds the first preset threshold, read original data of the current page for multiple times, determine a second bit flipping number of the current page according to multiple reading results, determine whether the second bit flipping number exceeds a second preset threshold, and if the second bit flipping number exceeds the second preset threshold, record the entity block to be tested where the current page is located as failing in the writing and reading test.

Therefore, the read storage data refers to corrected data. The correction unit can correct the written preset data to be accurately stored in the corresponding physical page, so that the stored data read from the physical page is the same as the written preset data, which indicates that the physical page, the corresponding page and the physical block to be tested 211(i) can perform data reading and writing operations, and further indicates that the corresponding physical block to be tested 211(i) is available. If the read storage data and the written preset data are different, the entity block to be tested 211(i) in which the error occurs is marked, and the physical address information of the entity block to be tested 211(i) is recorded in the bad block table.

In an embodiment, the predetermined data writing mode includes a multi-plane write mode, a DDR write mode and a cache write mode when the data write operation is performed. The multi-entity-plane writing method is to write data in the entity pages 2111 of the entity blocks 211 in the entity planes 21 in parallel, and specifically, access the entity planes 21 in a single channel through an interleave algorithm to improve the NAND performance algorithm. Specifically, in order to improve the performance of the memory module 121, the solid die 3 in the embodiment is designed with multiple solid planes 21 to improve the performance. One solid crystal grain 3 is divided into 2 solid surfaces 21, and the solid blocks 211 in the 2 solid surfaces 21 are single-double cross-numbered; when data is read from or written to each physical surface 21 individually, the performance of the memory module 121 can be improved by the ping-pong operation. The DDR write mode is to write data at a frequency of 100 MHZ. The cache write method specifically sets 1 physical block 21 for each physical surface 21 to serve as a data cache, and illustratively, the capacity of the physical block 21 is 2048 bytes for two physical surfaces 21, and then the cache capacity needs to be set to 4096 bytes (here, the test apparatus is limited).

In an embodiment, after the operation of recording the result of the write-read test in the bad block table, the memory controller 131 may obtain the entity block yield of the entity die 211(i) to be tested according to the bad block table, and perform quality classification on the entity die to be tested according to the entity block yield. Specifically, the memory controller 131 may calculate the ratio of the write-read test result in the bad block table to the passed physical block 211(i) to be tested (this is because only the write-read test result is the passed physical block 211(i) to be tested, and the erase test result is also the passed physical block 211(i) to be tested is finally determined to be usable), and after obtaining the physical block yield of the current physical die to be tested, the physical die to be tested is divided into sufficient physical dies or semi-sufficient physical dies or 1/4 physical dies according to the range of the physical block yield. The above-mentioned range of intervals can be divided in an adjustable manner according to the use criteria of the memory storage device to be used subsequently. Illustratively, the yield of the solid block is 93% or more of enough solid grains, 60-93% of half-volume solid grains and 60% or less of 1/4 solid grains.

Since there may be a problem that an erasure error may occur when the entity blocks to be tested 31 that pass the write-read test are erased again in some cases, in an embodiment, the memory controller 131 may perform a secondary erasure test on the entity blocks to be tested that pass the write-read test in the bad block table one by one after the operation of recording the result of the write-read test in the bad block table, and record the result of the secondary erasure test in the bad block table. Thus, the test accuracy can be further improved.

FIG. 7 is a flow chart illustrating a memory module screening method according to an embodiment of the invention. Referring to fig. 7, in step S301, a plurality of solid blocks to be tested are uniformly selected from a plurality of solid surfaces of a solid die to be tested. In step S302, an erase test is performed on a plurality of entity blocks to be tested one by one, and a bad block table for recording the result of the erase test is constructed. In step S303, the erase test result in the bad block table is that the passed entity blocks to be tested are subjected to a write-read test one by one, and the result of the write-read test is recorded in the bad block table.

However, the steps in fig. 7 have been described in detail above, and are not described again here. It is to be noted that, the steps in fig. 7 can be implemented as a plurality of program codes or circuits, and the invention is not limited thereto. In addition, the method of fig. 7 may be used with the above exemplary embodiments, or may be used alone, and the invention is not limited thereto.

In summary, after a plurality of solid blocks to be tested are uniformly selected from a plurality of solid surfaces of the solid grains to be tested, the plurality of solid blocks to be tested are firstly subjected to an erasure test one by one, and a bad block table for recording the result of the erasure test is constructed. And then, performing write-read tests on the solid blocks to be tested, which pass the erase test result in the bad block table one by one, and recording the write-read test result in the bad block table. Therefore, the test frequency of the solid blocks in the solid crystal grains to be tested can be greatly reduced while the final screening test result is not influenced as much as possible, and the test efficiency is greatly improved. And the physical crystal grains of the memory module can be rapidly screened and detected before being packaged into the memory module, whether the current physical crystal grains can meet the use standard of a subsequently used memory storage device or not is rapidly identified, and if the current physical crystal grains do not meet the use standard, the current physical crystal grains can be blocked before the physical crystal grains are not packaged, so that the subsequent packaging cost is saved, and the loss is reduced.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory module screening method for a memory storage device, wherein the memory storage device comprises a memory module, the memory module comprises at least one physical die, the physical die comprises a plurality of physical planes, each of the physical planes comprises a plurality of physical blocks, each of the physical blocks comprises a plurality of physical pages, the memory module screening method comprises:

uniformly selecting a plurality of entity blocks to be tested from a plurality of entity surfaces of entity grains to be tested;

performing erasure test on the plurality of entity blocks to be tested one by one, and constructing a bad block table for recording the erasure test result;

and performing write-read tests on the solid blocks to be tested, the result of which is the passing of the erase test in the bad block table, one by one, and recording the result of the write-read tests in the bad block table.

2. The method of claim 1, wherein the act of uniformly picking a plurality of physical blocks to be tested from a plurality of physical faces of a physical die to be tested comprises:

selecting the solid blocks to be tested at a plurality of preset positions of each solid surface by taking the solid surfaces as units;

and selecting at least one solid block to be tested from each preset position to obtain a plurality of solid blocks to be tested.

3. The memory module screening method of claim 2, wherein the plurality of predetermined locations includes any combination of a front region of the solid surface, a middle region of the solid surface, a rear region of the solid surface, a left region of the solid surface, and a right region of the solid surface; or the preset positions comprise any combination of all preset columns of the entity surface and all preset rows of the entity surface.

4. The memory module screening method of claim 1, wherein the operation of performing an erase test on the plurality of physical blocks to be tested one by one and constructing a bad block table for recording the result of the erase test comprises:

sending an erasing command to the entity blocks to be tested;

erasing the entity blocks to be tested one by one according to the erasing command;

if the current entity block to be tested is successfully erased, recording the result of the erasure test of the current entity block to be tested as passing in the constructed bad block table;

if the current entity block to be tested has an error in erasure, recording the result of the erasure test of the current entity block to be tested as failing in the constructed bad block table.

5. The method for screening memory modules according to claim 1, wherein the operation of performing write-read tests on the physical blocks to be tested whose result of the erase test in the bad block table is passed one by one, and recording the result of the write-read test of the corresponding physical block to be tested in the bad block table comprises:

sending a data writing instruction to the entity block to be tested, which passes the erasing test result in the bad block table;

performing data writing operation on the current entity block to be tested according to the data writing instruction so as to write preset data;

sending a data reading comparison instruction to the entity block to be tested after the data writing operation is executed;

performing data reading comparison operation on the entity block to be tested which has performed the data writing operation according to the data reading comparison instruction so as to read the stored data in the entity block to be tested which has performed the data writing operation and compare the stored data with the preset data;

if the comparison result is inconsistent, recording the result of the write-read test of the current entity block to be tested as failing in the bad block table;

and if the comparison result is consistent, recording the result of the write-read test of the entity block to be tested as pass in the bad block table.

6. The method for screening memory modules as claimed in claim 1, wherein the writing of the predetermined data includes a multi-physical-plane writing method, a DDR writing method, and a cache writing method.

7. The memory module screening method of any one of claims 1 to 6, further comprising, after the operation of recording the result of the write-read test in the bad block table:

and obtaining the entity block yield of the entity grain to be tested at present according to the bad block table, and performing quality division on the entity grain to be tested according to the entity block yield.

8. The method as claimed in claim 7, wherein obtaining the physical block yield of the physical die to be tested according to the bad block table, and performing quality classification on the physical die to be tested according to the physical block yield comprises:

calculating the proportion of the write-read test result in the bad block table to the passed entity block to be tested to obtain the entity block yield of the current entity grain to be tested;

and dividing the entity grains to be tested into enough entity grains or semi-capacity entity grains or 1/4 entity grains according to the range of the yield of the entity blocks.

9. The memory module screening method according to claim 1, further comprising, after the operation of recording the result of the write-read test in the bad block table:

and performing secondary erasure test on the solid blocks to be tested, which pass the write-read test result in the bad block table, one by one, and recording the secondary erasure test result in the bad block table.

10. A testing apparatus comprising a memory controller, the memory controller being electrically connected to a memory module, the memory controller being configured to perform the memory module screening method of any one of claims 1 to 9.