CN107845406A - A kind of method and apparatus for testing memory - Google Patents
A kind of method and apparatus for testing memory Download PDFInfo
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- CN107845406A CN107845406A CN201610835169.8A CN201610835169A CN107845406A CN 107845406 A CN107845406 A CN 107845406A CN 201610835169 A CN201610835169 A CN 201610835169A CN 107845406 A CN107845406 A CN 107845406A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The present invention relates to technical field of integrated circuits, because time complexity is larger when more particularly to a kind of method and apparatus for testing memory is to solve to test memory present in prior art, caused by the testing time it is longer, the problem of number of operations is more.The embodiment of the present invention, reads the first numerical value in the memory cell according to first order, and second value is write to the memory cell of memory according to the first order of setting；The first order according to setting reads the second value in the memory cell；The second order according to setting reads the second value in the memory cell, and the first numerical value is write to the memory cell of memory according to the second order of setting；The second order according to setting reads the first numerical value in the memory cell.The embodiment of the present invention saves multiple steps during read-write, and time complexity is significantly reduced compared to prior art, and then shortens the testing time, reduces number of operations, further improves power consumption.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of method and apparatus for testing memory.
Background technology
MBIST (Memory Build-in Self Test, memory built in self test of sram) is exclusively used in memory test
Structure, it is possible to achieve a variety of testing algorithms.The algorithm of especially MARCH series uses extensive in MBIST.The algorithm of MARCH series,
It is that the one kind proposed according to storage failure model has compared with high fault coverage, relatively low implementation complexity, detects relatively convenient
Algorithm.
MARCH algorithms are the sequences being made up of MARCH elements, and its basic thought is to carry out reading 0 to each address repeatedly
Or write 0, read 1 or write 1 operation, to ensure to occur 00,01,10,11 these four situations in the test patterns between each two byte extremely
Less respectively once.And in order to check the reading and writing sequential fault of high and low address, enter respectively row address be incremented by and two kinds of decreasing addresses
Operation.
The complexity of testing algorithm is the concept of a description performance such as test of heuristics time length at present, general MARCH
The complexity of algorithm is described as O (mn), and m is the reading and writing number of operations in each stepping unit, and n is the number of memory cell.It is multiple
N numerical value and the scale of holder and structure are closely bound up in miscellaneous degree.In the case where n is certain, with m increase, algorithm is held
The growth rate of row time O (mn) and m growth rate are directly proportional.So m is smaller, the time complexity of algorithm is lower, the effect of algorithm
Rate is higher, and m improvement is with regard to particularly important.
Such as one block size be 1MB sp8192x32w4 memories, unit number 8192*32*4=1048276, operation
The time complexity that single MARCH C algorithms take is 11534336.If memory is 4GB DDR, unit number 4G=4*
The time complexity that 1024=4096M=4096*1048276, operation single MARCH C algorithm take is 47244640256.This
The difference of single is also simply operated, if with same algorithm multi-pass operation, time complexity can be bigger.
In summary, because time complexity is larger when testing memory at present, cause the testing time longer, number of operations
It is more.
The content of the invention
The present invention provides a kind of method and apparatus for testing memory, to solve to test storage present in prior art
Because time complexity is larger during device, the problem of testing time is longer, and number of operations is more is caused.
The embodiments of the invention provide a kind of method for testing memory, this method includes：
Operation is written and read to the memory cell in memory according to following read-write process；
The test result of the memory is generated according to the result of read-write operation；
The read-write process is：
Read the first numerical value in the memory cell according to first order, and according to setting the first order by
Two numerical value write the memory cell of memory；
The first order according to setting reads the second value in the memory cell；
The second order according to setting reads the second value in the memory cell, and will according to the second order of setting
First numerical value writes the memory cell of memory；
The second order according to setting reads the first numerical value in the memory cell.
Before the first numerical value during the memory cell is read according to first order, in addition to：
First numerical value is write to the memory cell of memory according to address ascending order or descending.
After the second order according to setting reads the first numerical value in the memory cell, in addition to：
The first numerical value in the memory cell is read according to address ascending order or descending.
Optionally, if first numerical value is 0, the second value is 1；
If first numerical value is 1, the second value is 0.
Optionally, if first order is address ascending order, second order is address descending；
If first order is address descending, second order is address ascending order.
A kind of equipment for testing memory provided in an embodiment of the present invention, the equipment include：
Read-write operation module, for being written and read operation to the memory cell in memory according to following read-write process；
Read the first numerical value in the memory cell according to first order, and according to setting the first order by
Two numerical value write the memory cell of memory；
The first order according to setting reads the second value in the memory cell；
The second order according to setting reads the second value in the memory cell, and will according to the second order of setting
First numerical value writes the memory cell of memory；
The second order according to setting reads the first numerical value in the memory cell.
The read-write operation module is additionally operable to：
Before the first numerical value during the memory cell is read according to first order, according to address ascending order or descending
By the memory cell of the first numerical value write-in memory.
The read-write operation module is additionally operable to：
After second order according to setting reads the first numerical value in the memory cell, according to address ascending order or
Descending reads the first numerical value in the memory cell.
Optionally, if first numerical value is 0, the second value is 1；
If first numerical value is 1, the second value is 0.
Optionally, if first order is address ascending order, second order is address descending；
If first order is address descending, second order is address ascending order.
The embodiment of the present invention writes the first numerical value according to address ascending order or descending the memory cell of memory；According to described
First order reads the first numerical value in the memory cell, and second value is write into memory according to the first order of setting
Memory cell；The first order according to setting reads the second value in the memory cell；According to the second order of setting
Read the second value in the memory cell, and the first numerical value is write to the storage list of memory according to the second order of setting
Member；The second order according to setting reads the first numerical value in the memory cell；According to described in address ascending order or descending reading
The first numerical value in memory cell.
Because the embodiment of the present invention saves multiple steps during the read-write of test memory, in number of memory cells one
In the case of fixed, time complexity is significantly reduced compared to prior art, and then shortens the testing time, reduces operation time
Number, further improves power consumption.
Brief description of the drawings
Technical scheme in order to illustrate the embodiments of the present invention more clearly, make required in being described below to embodiment
Accompanying drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, without having to pay creative labor, it can also be obtained according to these accompanying drawings
His accompanying drawing.
Fig. 1 is the method flow schematic diagram that the embodiment of the present invention tests memory；
Fig. 2 is fault detect schematic diagram of the embodiment of the present invention；
Fig. 3 is the complete method schematic flow sheet that the embodiment of the present invention tests memory；
Fig. 4 is the device structure schematic diagram of the first test memory of the embodiment of the present invention；
Fig. 5 is the device structure schematic diagram of second of test memory of the embodiment of the present invention.
Embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, the present invention is made below in conjunction with accompanying drawing into
One step it is described in detail, it is clear that the described embodiment only a part of embodiment of the present invention, rather than whole implementation
Example.Based on the embodiment in the present invention, what those of ordinary skill in the art were obtained under the premise of creative work is not made
All other embodiment, belongs to the scope of protection of the invention.
As shown in figure 1, the method for test memory of the embodiment of the present invention includes：
Step 100, according to following read-write process operation is written and read to the memory cell in memory；
Step 101, the test result according to the result of the read-write operation generation memory；
The read-write process is：
Read the first numerical value in the memory cell according to first order, and according to setting the first order by
Two numerical value write the memory cell of memory；
The first order according to setting reads the second value in the memory cell；
The second order according to setting reads the second value in the memory cell, and will according to the second order of setting
First numerical value writes the memory cell of memory；
The second order according to setting reads the first numerical value in the memory cell.
The embodiment of the present invention saves multiple steps during the read-write of test memory, certain in number of memory cells
In the case of, time complexity is significantly reduced compared to prior art, and then the testing time is shortened, reduce number of operations,
Further improve power consumption.
The principle that the embodiment of the present invention carries out fault detect to memory is by the way that the physical fault of memory is converted into
Logic fault, according to the feature of logic fault, failure is covered by corresponding read-write operation order, so as to realize detection.
Most common failure in memory has：
Persistent fault：The one or more of one or more units in array are shown as to be fixed as " 1 " or " 0 ".
Unit open failure：Showing as the storage content of some unit can not correctly obtain, it is possible to which result has randomness.
State Transferring failure：Upward translation exception can not change to " 1 " from " 0 ", and downward translation exception can not change to from " 1 "
“0”。
Coupling fault：The saltus step of some memory cell causes the logical value of other memory cell that unexpected change occurs.
Address decoding failure：Some memory cell can not be chosen by any address, or some memory cell can be more
Choose individual address.
Read and write logic fault：Some memory cell can not be correctly written in or read data.
The conventional detection method of storage failure has：
Persistent fault：1 reading 1 is write to some unit, writes 0 reading 0.
Unit open failure：A certain unit is repeatedly read, whether the result more repeatedly read is consistent.
State Transferring failure：0 is write to a certain units alternately, writes 1, compare reading data whether with last time write-in
Data are consistent.
Coupling fault：0 is write to some unit or writes 1, reads the data of adjacent cells.
Address decoding failure：0 is write to some unit or writes 1, reads the data of whole units.
Read and write logic fault：1 reading 1 is write to some unit, writes 0 reading 0.
The main feature operation of holder is exactly the read-write to memory cell, and read operation is whether write operation is correct
One kind performance, the correctness of write operation could be preferably detected only on the basis of read operation is correct.Based on this, the present invention is real
The read-write that example carries out 0 and 1 according to order above is applied, if vicious place, it is possible to failure is detected, so this hair
The read-write process of bright embodiment not only covers several failures above, and effectively controls complexity and the behaviour of MBIST realizations
Make number, also enhance the detection of Read fault.
The scheme of the embodiment of the present invention individually adds the reading of a reverse sequence on the basis of memory cell is read every time
Operation, whether consistent, and then detect a variety of Read faults if can so detect the data read every time.
Optionally, if first numerical value is 0, the second value is 1；
If first numerical value is 1, the second value is 0.
Optionally, if first order is address ascending order, second order is address descending；
If first order is address descending, second order is address ascending order.
Address ascending order is to carry out read or write according to the order of address from low to high；
Address descending is to carry out read or write according to the order of address from high to low.
The complete test process of the embodiment of the present invention can be divided into M0~M5.
Below using the first numerical value as 0, second value 1, the first order is address ascending order, and the second order is that address descending is
Example illustrates to the solution of the present invention.
M0：Initialization, 0 is write to whole ram cell, the sequence of addresses of operation is ascending order or descending；
M1：In a manner of the ascending order of address, the value of each unit is read, whether the value for checking reading is 0, and to the unit
Write 1；
M2：In a manner of the ascending order of address, the value of each unit is read, whether the value for checking reading is 1；
M3：In a manner of the descending of address, the value of each unit is read, whether the value for checking reading is 1, and to the unit
Write 0；
M4：In a manner of the descending of address, the value of each unit is read, whether the value for checking reading is 0；
M5：The value of each unit is read, the sequence of addresses of operation is ascending order or descending.
Wherein, persistent fault can be detected by M1, M2, M3, M4；Unit open failure can be by M1, M2, M3 and M3, M4, M5 inspection
Go out；Coupling fault can be by M1, M2, M3 and M3, M4, M5 detection；State Transferring failure can be by M1, M2 and M3, M4 detections；Translate address
Code failure can be detected by the continuous ascending orders of MARCH units, descending；Reading and writing logic fault can be by M1, M2 and M3, M4 detection.
Specifically it may refer to Fig. 2.
As shown in figure 3, the complete method of test memory of the embodiment of the present invention includes：
Step 300, the memory cell that the first numerical value is write to according to address ascending order or descending memory；
Step 301, read according to first order the first numerical value in the memory cell；
Step 302, according to setting the first order by second value write memory memory cell；
Step 303, read according to the first order of setting second value in the memory cell；
Step 304, read according to the second order of setting second value in the memory cell；
Step 305, according to setting the second order by the first numerical value write memory memory cell；
Step 306, read according to the second order of setting the first numerical value in the memory cell；
Step 307, according to address ascending order or descending read the first numerical value in the memory cell.
Based on same inventive concept, a kind of equipment for testing memory is additionally provided in the embodiment of the present invention, because this sets
The standby principle solved the problems, such as is similar to the method for test memory of the embodiment of the present invention, therefore the implementation side of may refer to of the equipment
The implementation of method, repeat part and repeat no more.
As shown in figure 4, the equipment of the first test memory of the embodiment of the present invention includes：
Read-write operation module 400, for being written and read operation to the memory cell in memory according to following read-write process；
Test module 401, for generating the test result of the memory according to the result of read-write operation；
The read-write process is：
Read the first numerical value in the memory cell according to first order, and according to setting the first order by
Two numerical value write the memory cell of memory；
The first order according to setting reads the second value in the memory cell；
The second order according to setting reads the second value in the memory cell, and will according to the second order of setting
First numerical value writes the memory cell of memory；
The second order according to setting reads the first numerical value in the memory cell.
The read-write operation module 400 is additionally operable to：
Before the first numerical value during the memory cell is read according to first order, according to address ascending order or descending
By the memory cell of the first numerical value write-in memory.
The read-write operation module 400 is additionally operable to：
After second order according to setting reads the first numerical value in the memory cell, according to address ascending order or
Descending reads the first numerical value in the memory cell.
Optionally, if first numerical value is 0, the second value is 1；
If first numerical value is 1, the second value is 0.
Optionally, if first order is address ascending order, second order is address descending；
If first order is address descending, second order is address ascending order.
As shown in figure 5, the equipment of second of test memory of the embodiment of the present invention includes：
Controller 50 is used for scheme according to embodiments of the present invention and transfers the more wheel data of Data Generator generation, and according to this
The scheme control data maker formation sequence 0 and sequence 1 of inventive embodiments；
Comparator 51 is called to be used for the normal data for the data and Data Generator write-in for exporting memory according to control
It is compared；
Data Generator 52 is used for according to control formation sequence 0 and sequence 1, and writes in memory 53；
Memory 53 is used for data storage；
Row decoder 54 is used for the translation of the row address read and write；
Column decoder 55 is used for the translation of the column address read and write.
It can be seen from the above：First numerical value is write memory by the embodiment of the present invention according to address ascending order or descending
Memory cell, read the first numerical value in the memory cell according to first order, and according to the first order of setting
By the memory cell of second value write-in memory；The first order according to setting reads the second number in the memory cell
Value；The second order according to setting reads the second value in the memory cell, and according to setting the second order by first
Numerical value writes the memory cell of memory；The second order according to setting reads the first numerical value in the memory cell, according to
Address ascending order or descending read the first numerical value in the memory cell.Because the embodiment of the present invention is in the read-write of test memory
During save multiple steps, in the case where number of memory cells is certain, significantly reduces the time compared to prior art and answer
Miscellaneous degree, and then the testing time is shortened, reduce number of operations, further improve power consumption.
Above by reference to representing according to the method, apparatus (system) of the embodiment of the present application and/or the frame of IC products
Figure and/or flow chart describe the application.It should be understood that block diagram and/or flowchart illustration can be realized by hardware description language
A block and block diagram and/or the block of flowchart illustration combination.Can be by function mould that these hardware description languages are realized
Block is supplied to universal integrated circuit, application specific integrated circuit and/or other hardware design modules or system for being integrated with memory, with
The related module of MBIST functions is produced, creates the side for realizing function/action specified in block diagram and/or flow chart block
Method.
Correspondingly, the application can also be implemented with hardware and/or software (including firmware, resident software, microcode etc.).More
Further, the application can take the form that IC chip uses or IC Hardware description language uses, and it has
There is the hardware identification code realized in integrated circuits, needing to use for system is combined by the level of hardware, control and data flow.
In the application context, integrated circuit can be used or hardware description language workable for mode, can be hardware description language, soft
Part language, netlist, textual form test vector etc. use the use of the Related product flow of this method, or combined command performs system
System, device or equipment use.
Obviously, those skilled in the art can carry out the essence of various changes and modification without departing from the present invention to the present invention
God and scope.So, if these modifications and variations of the present invention belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising including these changes and modification.
Claims (10)
- A kind of 1. method for testing memory, it is characterised in that this method includes：Operation is written and read to the memory cell in memory according to following read-write process；The test result of the memory is generated according to the result of read-write operation；The read-write process is：The first numerical value in the memory cell is read according to first order, and is counted according to the first order of setting by second The memory cell of value write-in memory；The first order according to setting reads the second value in the memory cell；The second order according to setting reads the second value in the memory cell, and according to setting the second order by first Numerical value writes the memory cell of memory；The second order according to setting reads the first numerical value in the memory cell.
- 2. the method as described in claim 1, it is characterised in that described to read the memory cell according to first order In the first numerical value before, in addition to：First numerical value is write to the memory cell of memory according to address ascending order or descending.
- 3. the method as described in claim 1, it is characterised in that described to read the memory cell according to the second order of setting In the first numerical value after, in addition to：The first numerical value in the memory cell is read according to address ascending order or descending.
- 4. the method as described in claims 1 to 3 is any, it is characterised in that if first numerical value is 0, second number It is worth for 1；If first numerical value is 1, the second value is 0.
- 5. the method as described in claims 1 to 3 is any, it is characterised in that described if first order is address ascending order Second order is address descending；If first order is address descending, second order is address ascending order.
- 6. a kind of equipment for testing memory, it is characterised in that the equipment includes：Read-write operation module, for being written and read operation to the memory cell in memory according to following read-write process；Test module, for generating the test result of the memory according to the result of read-write operation；The read-write process is：The first numerical value in the memory cell is read according to first order, and is counted according to the first order of setting by second The memory cell of value write-in memory；The first order according to setting reads the second value in the memory cell；The second order according to setting reads the second value in the memory cell, and according to setting the second order by first Numerical value writes the memory cell of memory；The second order according to setting reads the first numerical value in the memory cell.
- 7. equipment as claimed in claim 6, it is characterised in that the read-write operation module is additionally operable to：Before the first numerical value during the memory cell is read according to first order, according to address ascending order or descending by One numerical value writes the memory cell of memory.
- 8. equipment as claimed in claim 6, it is characterised in that the read-write operation module is additionally operable to：After second order according to setting reads the first numerical value in the memory cell, according to address ascending order or descending Read the first numerical value in the memory cell.
- 9. the equipment as described in claim 6~8 is any, it is characterised in that if first numerical value is 0, second number It is worth for 1；If first numerical value is 1, the second value is 0.
- 10. the equipment as described in claim 6~8 is any, it is characterised in that if first order is address ascending order, institute It is address descending to state the second order；If first order is address descending, second order is address ascending order.
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| CN110570896A (en) * | 2019-07-31 | 2019-12-13 | 南京邮电大学 | Low-voltage SRAM (static random Access memory) testing method for weak faults |
| CN110648715A (en) * | 2019-10-09 | 2020-01-03 | 南京邮电大学 | Test method for write half-select fault of low-voltage SRAM (static random Access memory) |
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| CN112349341A (en) * | 2020-11-09 | 2021-02-09 | 深圳佰维存储科技股份有限公司 | LPDDR test method, device, readable storage medium and electronic equipment |
| CN113178223A (en) * | 2021-04-27 | 2021-07-27 | 珠海全志科技股份有限公司 | Data training method of memory, computer device and computer readable storage medium |
| US11862233B2 (en) | 2021-11-05 | 2024-01-02 | Changxin Memory Technologies, Inc. | System and method for detecting mismatch of sense amplifier |
| CN117594107A (en) * | 2024-01-18 | 2024-02-23 | 安徽大学 | Test method and test circuit for detecting memory faults |
| CN117594107B (en) * | 2024-01-18 | 2024-05-03 | 安徽大学 | Test method and test circuit for detecting memory faults |
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