CN111863111B - DRAM testing method and device, computer readable storage medium and electronic equipment - Google Patents
DRAM testing method and device, computer readable storage medium and electronic equipment Download PDFInfo
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- CN111863111B CN111863111B CN202010660417.6A CN202010660417A CN111863111B CN 111863111 B CN111863111 B CN 111863111B CN 202010660417 A CN202010660417 A CN 202010660417A CN 111863111 B CN111863111 B CN 111863111B
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The invention discloses a DRAM test method, a device, a computer readable storage medium and an electronic device, when testing the DRAM, jumping to select a second preset read-write unit for each first preset read-write unit of the DRAM and write data until the data are written in a storage array of the DRAM to be tested, jumping to read the data according to the sequence corresponding to the data writing and the corresponding data when reading the data, and obtaining the test result of the DRAM according to the data result of jumping to write and the data result of corresponding jumping to read; the embodiment of the invention well simulates the actual use environment of a user in a skip read-write mode, can better detect the weak cells and the fault units in the DRAM, covers the problem that the conventional algorithm cannot detect, and can improve the fault coverage rate.
Description
Technical Field
The present invention relates to the field of DRAM chip testing, and in particular, to a DRAM testing method and apparatus, a computer-readable storage medium, and an electronic device.
Background
DRAM (Dynamic Random Access Memory) is a high-speed Chip that directly communicates with SOC (System-On-a-Chip), and data is transmitted to SOC through DRAM Chip first, so the quality of DRAM is closely related to the stability of the whole System.
To ensure the reliability of a DRAM chip, it is often necessary to test it. At present, many tests on DRAM chips are performed sequentially row by row, and memory cells inside the DRAM are sequentially tested in an ascending direction. The test mode does not match the actual use process of the DRAM by a user although all addresses of the DRAM are traversed. In the actual use process, a user cannot strictly read and write each storage unit row by row and column by column in sequence in an ascending order. Therefore, the existing test method for the DRAM cannot simulate the actual use environment of a user, some detection holes exist, and the week cells and fault cells existing in the DRAM cannot be detected comprehensively.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a DRAM test method, a device, a computer readable storage medium and an electronic device are provided, which can simulate the actual use environment of a user and improve the fault coverage rate.
In order to solve the technical problems, the invention adopts a technical scheme that:
a test method of a DRAM includes the steps:
jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written in the storage array of the DRAM to be tested, and obtaining a data writing result;
sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process until the data of the storage array of the DRAM to be tested are all read, and obtaining a data reading result;
and obtaining a test result of the DRAM to be tested according to the data writing result and the data reading result.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
a test apparatus of a DRAM, comprising:
the data writing module is used for jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written in the storage array of the DRAM to be tested, and obtaining a data writing result;
the data reading module is used for sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process until the data of the storage array of the DRAM to be tested are all read, and obtaining a data reading result;
and the comparison module is used for obtaining the test result of the DRAM to be tested according to the data writing result and the data reading result.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
a computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method of testing a DRAM.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
an electronic device comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the computer program to realize the steps of the DRAM testing method.
The invention has the beneficial effects that: when the DRAM is tested, jumping to select a second preset read-write unit for each first preset read-write unit of the DRAM and writing data until the data are all written in the storage array of the DRAM to be tested, when the data are read, jumping to read the data according to the sequence corresponding to the data writing and the corresponding data, and obtaining the test result of the DRAM according to the data result of jumping writing and the corresponding data result of jumping reading; the actual use environment of a user is well simulated in a jumping read-write mode, a weak cell and a fault unit in a DRAM can be better detected, the problem that the existing conventional algorithm cannot detect is solved, and the fault coverage rate can be improved.
Drawings
FIG. 1 is a flow chart of steps of a method for testing a DRAM according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a DRAM testing apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating data writing of a first model in a testing method of a DRAM according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating data reading of a first model in a testing method of a DRAM according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating data writing of a second model in a testing method of a DRAM according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating data reading of a second model in the testing method of the DRAM according to the embodiment of the present invention;
FIG. 8 is a diagram illustrating data writing of a third model in the testing method of the DRAM according to the embodiment of the present invention;
FIG. 9 is a diagram illustrating data reading of a third model in the testing method of the DRAM according to the embodiment of the present invention.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, an embodiment of the invention provides a method for testing a DRAM, including the steps of:
jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written in the storage array of the DRAM to be tested, and obtaining a data writing result;
sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process until the data of the storage array of the DRAM to be tested are all read, and obtaining a data reading result;
and obtaining a test result of the DRAM to be tested according to the data writing result and the data reading result.
As can be seen from the above description, the beneficial effects of the present invention are: when the DRAM is tested, jumping to select a second preset read-write unit for each first preset read-write unit of the DRAM and writing data until the data are all written in the storage array of the DRAM to be tested, when the data are read, jumping to read the data according to the sequence corresponding to the data writing and the corresponding data, and obtaining the test result of the DRAM according to the data result of jumping writing and the corresponding data result of jumping reading; the actual use environment of a user is well simulated in a jumping read-write mode, a weak cell and a fault unit in a DRAM can be better detected, the problem that the existing conventional algorithm cannot detect is solved, and the fault coverage rate can be improved.
Further, the first preset read-write units are rows, and the second preset read-write units are columns;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each row in each bank (bank or memory bank) of the DRAM to be tested:
selecting the ith column of the row and writing data, then jumping to select the max-i +1 th column of the row and writing data, wherein max represents the number of columns contained in the row, and the initial value of i is 1;
and enabling i = i +1, and returning to execute the step of selecting the ith column of the row and writing data until data is written in each column of the row.
According to the description, for each row of the DRAM to be tested, reading and writing are carried out back and forth in the unit of column, data are written in a jumping mode first until the data are written in the storage array of the DRAM to be tested, then the data are read in a jumping mode correspondingly until the data in the storage array of the DRAM to be tested are read, the actual use environment of a user for the DRAM chip can be simulated well, the comprehensiveness of the DRAM chip detection is guaranteed, the fault coverage rate of the DRAM chip can be improved, the reading and writing complexity is low through the reading and writing mode, the testing time is saved, and the production cost is reduced.
Further, the first preset read-write units are rows, and the second preset read-write units are columns;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each column in each bank of the DRAMs to be tested:
selecting the ith row of the column and writing data, then jumping to select the max-i +1 th row of the column and writing data, wherein max represents the number of rows contained in the column, and the initial value of i is 1;
and enabling i = i +1, and returning to execute the step of selecting the ith row of the column and writing data until each row of the column is written with data.
According to the description, for each row of the DRAM to be tested, reading and writing are carried out back and forth in a row unit, data are written in a jumping mode first until the data are written in the storage array of the DRAM to be tested, and then the data are read in a jumping mode correspondingly until the data of the storage array of the DRAM to be tested are read.
Further, the first preset read-write unit is a row and a column, and the second preset read-write unit is a bank;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each rank of the DRAMs to be tested:
selecting the rank of the ith bank and writing data in the rank, then jumping and selecting the rank of the max-i +1 th bank and writing data in the rank, wherein max represents the number of the banks of the DRAM to be tested, and the initial value of i is 1;
and i = i +1, and returning to execute the step of selecting the rank of the ith bank and writing data until the rank of each bank writes data.
According to the description, for each row and column of the DRAM to be tested, namely, the storage units corresponding to a certain row and column, the reading and writing are carried out back and forth by taking bank as a unit, the data are written in a jumping mode firstly until the data are written in the storage arrays of the DRAM to be tested, and then the data are read in a jumping mode correspondingly until the data of the storage arrays of the DRAM to be tested are read.
Further, sequentially selecting each first preset read-write unit in the DRAM to be tested according to the serial number of the first preset read-write unit from small to large; or randomly selecting a first preset read-write unit in the DRAM to be tested until all the first preset read-write units in the DRAM to be tested are traversed; or jumping to select the first preset read-write unit in the DRAM to be tested until all the first preset read-write units in the DRAM to be tested are traversed.
As can be seen from the above description, the first preset read-write units of the DRAM to be tested can be selected in various different ways until each first preset read-write unit is traversed, so that the flexibility and the applicability are improved.
Further, in the data writing process, the data written by the adjacent second preset reading and writing units are opposite.
Further, the parity of the number of second preset read-write units corresponding to the first preset read-write units is judged, and if the number of the second preset read-write units is an odd number, the data written by the ith second preset read-write unit corresponding to each first preset read-write unit is the same as the data written by the max-i +1 th second preset read-write unit; and if the number of the first preset reading-writing units is an even number, the data written by the ith second preset reading-writing unit corresponding to each first preset reading-writing unit is opposite to the data written by the max-i + 1 second preset reading-writing unit.
According to the description, in the data writing process, the data written by the adjacent second preset reading and writing unit are opposite, so that the simulated reading and writing mode can be further ensured to be closer to the actual use environment of a user, and the fault coverage rate is further improved.
Referring to fig. 2, another embodiment of the invention provides a testing apparatus for a DRAM, including:
the data writing module is used for jumping and selecting a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested, and obtaining a data writing result;
the data reading module is used for sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process until the data of the storage array of the DRAM to be tested are all read, and obtaining a data reading result;
and the comparison module is used for obtaining the test result of the DRAM to be tested according to the data writing result and the data reading result.
Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps in the above-described method for testing a DRAM.
Referring to fig. 3, another embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for testing the DRAM when executing the computer program.
The DRAM testing method, the device, the computer readable storage medium and the electronic equipment can be applied to testing any type of DRAM and have universality.
A DRAM chip is formed by a memory array, a register, a decoder and some peripheral circuits, wherein a plurality of banks are arranged inside the memory array, for example, LPDDR3 has 8 banks, and a bank can be subdivided into a plurality of rows and columns, each row and column is formed by a large number of basic memory cells (a capacitor and a transistor), and the following description is provided by the specific implementation mode:
example one
Referring to fig. 1, a testing method of a DRAM includes the steps of:
s1, jumping to select a second preset read-write unit on each first preset read-write unit of a DRAM to be tested, and writing data until data are written in a storage array of the DRAM to be tested, so as to obtain a data writing result;
s2, according to a second preset read-write unit selected from each first preset read-write unit in the data write-in process and corresponding written data, sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data until the data of the storage array of the DRAM to be tested are all read, and obtaining a data read result;
s3, obtaining a test result of the DRAM to be tested according to the data writing result and the data reading result;
specifically, whether each written data in the data writing result is consistent with each read data in the corresponding data reading result is sequentially judged, if so, the memory cell corresponding to the written data operates normally, and if not, the memory cell corresponding to the written data is a fault cell;
the first preset read-write unit and the second preset read-write unit can be combined differently and are realized through different models:
in an optional embodiment, the first preset read-write units are rows, and the second preset read-write units are columns;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each row in each bank of the DRAMs to be tested:
selecting the ith column of the row and writing data, then jumping to select the max-i +1 th column of the row and writing data, wherein max represents the number of columns contained in the row, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the ith column of the row and writing data until each column of the row is written with data;
specifically, as shown in fig. 4, first, skip back and forth writing is performed:
firstly, writing data into a memory cell corresponding to the 1 st column of the first row in the first bank, and then jumping to a memory cell corresponding to the max column of the row to write data;
then writing data into the memory cell corresponding to the 2 nd column of the row, and jumping to the memory cell corresponding to the max-1 th column of the row to write data;
writing data into the memory cell corresponding to the 3 rd column of the row, and then jumping to the memory cell corresponding to the max-2 nd column of the row to write data;
repeating the same operation until all the memory cells of the DRAM to be tested write data, and then moving to the next bank;
after the data writing is completed, as shown in fig. 5, the jump reading is performed, and the corresponding reading is performed in sequence according to the writing order:
reading and writing corresponding data in a memory cell corresponding to the 1 st column of a first row in a first bank, and then jumping to a memory cell corresponding to the max column of the row to read and write corresponding data;
reading and writing corresponding data in a memory cell corresponding to the 2 nd column of the row, and jumping to a memory cell corresponding to the max-1 th column of the row to read and write corresponding data;
reading and writing corresponding data in a memory cell corresponding to the 3 rd column of the row, and jumping to a memory cell corresponding to the max-2 th column of the row to read and write corresponding data;
and repeating the same operation until all the memory cells of the DRAM to be tested are read, and finally obtaining a data reading result.
In another optional implementation, the first preset read-write units are columns, and the second preset read-write units are rows;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each column in each bank of the DRAMs to be tested:
selecting the ith row of the column and writing data, then jumping to select the max-i + 1 row of the column and writing data, wherein max represents the number of the rows contained in the column, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the ith row of the column and writing data until each row of the column is written with data;
specifically, as shown in fig. 6, first, skip back and forth writing is performed:
firstly, writing data into the memory cell corresponding to the 1 st row of the first column in the first bank, and then jumping to the memory cell corresponding to the max row of the column to write data;
then writing data into the memory cell corresponding to the 2 nd row in the column, and jumping to the memory cell corresponding to the max-1 th row in the column to write data;
writing data into the memory cell corresponding to the 3 rd row of the column, and jumping to the memory cell corresponding to the max-2 th row of the column to write data;
repeating the same operation until all the memory cells of the DRAM to be tested write data, and then moving to the next bank, repeating the same operation until all the memory cells of the DRAM to be tested write data, and finally obtaining a data writing result;
after the data writing is completed, as shown in fig. 7, the jump reading is performed, and the corresponding reading is performed in sequence according to the writing order:
reading and writing corresponding data in a memory cell corresponding to the 1 st row of the first column in the first bank, and then jumping to a memory cell corresponding to the max row of the column to read and write corresponding data;
reading and writing corresponding data in the memory cell corresponding to the 2 nd row of the column, and jumping to the memory cell corresponding to the max-1 th row of the column to read and write corresponding data;
reading and writing corresponding data in the memory cell corresponding to the 3 rd row of the column, and jumping to the memory cell corresponding to the max-2 th row of the column to read and write corresponding data;
and repeating the same operation until all the memory cells of the DRAM to be tested are read, and finally obtaining a data reading result.
In another optional embodiment, the first predetermined read-write unit is a row and the second predetermined read-write unit is a bank;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each rank of the DRAMs to be tested:
selecting the ranks of the ith bank and writing data, and then jumping to select the ranks of the max-i +1 th bank and writing data, wherein max represents the number of the banks of the DRAM to be tested, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the row and column of the ith bank and writing data until the row and column of each bank write data;
specifically, as shown in fig. 8, first, skip back and forth writing is performed:
after the first row and the first column are selected, firstly writing data into the memory cell corresponding to the first row and the first column in the first bank, then jumping to the max-th bank, and writing data into the memory cell corresponding to the first row and the first column of the max-th bank;
writing data into the memory cell corresponding to the first row and the first column in the second bank, jumping to the max-1 bank, and writing data into the memory cell corresponding to the first row and the first column of the max-1 bank;
writing data into the memory cell corresponding to the first row and the first column in the third bank, jumping to the max-2 bank, and writing data into the memory cell corresponding to the first row and the first column of the max-2 bank;
repeating the same operation until the storage units corresponding to each column of each row of all the banks are written with the data, and finally obtaining a data writing result;
after the data writing is completed, as shown in fig. 9, next, skip back and forth reading is performed, and corresponding reading is performed in sequence according to the writing order:
after the first row and the first column are selected, reading and writing corresponding data in a memory cell corresponding to the first row and the first column in the first bank, jumping to the max-th bank, and reading and writing corresponding data in a memory cell corresponding to the first row and the first column of the max-th bank;
reading and writing corresponding data in a memory cell corresponding to a first row and a first column in a second bank, jumping to a max-1 bank, and reading and writing corresponding data in a memory cell corresponding to a first row and a first column of the max-1 bank;
reading and writing corresponding data in a memory cell corresponding to a first row and a first column in a third bank, jumping to a max-2 bank, and reading and writing corresponding data in a memory cell corresponding to a first row and a first column of the max-2 bank;
and repeating the same operation until the data of the memory cells corresponding to each column of each row of all the banks are read, and finally obtaining the data reading result.
In the process of jumping to read and write back and forth, if the value of max is an even number, for the condition that the first preset read-write unit is a row or a column, two second preset read-write units located in the middle of the first preset read-write unit are used for performing last reading and writing on the first preset read-write unit, and if the value of max is an odd number, one second preset read-write unit located in the middle of the first preset read-write unit is used for performing last reading and writing on the first preset read-write unit; for the case that the first preset read-write unit is a row and a column, that is, a certain row and a certain column, if the value of max is an even number, the last read-write operation is performed on the middle two banks of the max banks, and if the value of max is an odd number, the last read-write operation is performed on the middle one bank of the max banks.
In addition to the above-mentioned head-and-tail reading and writing manner to implement skip reading and writing, there may be other manners to implement skip reading and writing, for example, when selecting the second preset reading and writing unit, skip reading and writing can be implemented by non-adjacent second preset reading and writing units selected twice.
In another alternative embodiment, the three models of jump reading and writing can be sequentially performed on the DRAM chip to be tested, so that all possibly existing faulty memory cells are covered as much as possible, and the fault coverage rate is further improved.
Example two
The difference between this embodiment and the first embodiment is that how to select the first preset read-write unit is specifically defined:
except that each first preset read-write unit in the DRAM to be tested is sequentially selected from small to large according to the serial number of the first preset read-write unit in the embodiment, for example, for the condition that the first preset read-write unit is a row, the row numbers of the rows can be selected from line 1, line 2 and line 3 of the first bank for \8230, the row numbers of the row are sequentially selected to line 1, then the row numbers of the rows are selected to line 2 and line 3 of the second bank for \8230, the row numbers of the rows are sequentially selected to line 1, and the like; for the condition that the first preset read-write unit is a column, the sequence from the 1 st column, the 2 nd column and the 3 rd column of the first bank can be selected \8230 \ 8230 \ from the last 1 column to the second bank, and the sequence from the 1 st column, the 2 nd column and the 3 rd column of the second bank can be selected \8230fromthe last 1 column to the third column and so on according to the serial number of the column; for the condition that the first preset read-write unit is a row and a column, the method can comprise the steps of starting from a first row according to the number of the row, sequentially selecting a first row and a first column, a first row and a second row, wherein 8230is formed by (8230) 'sequentially selecting a last row and a similar column from the first row and a second row and then a second row and a similar column from the second row and the first column, wherein (8230) is formed by (8230)' sequentially selecting a first row and a similar column from the first row and a similar column according to the number of the column, or sequentially selecting a first column and a second row and a similar column from the first row and the second column according to the number of the column, \\ 8230from the first row and the second row and the similar column, and then sequentially selecting a second column and a similar column from the first row and the second column, and the second row and the second column 8230;
the following modes can also be adopted:
randomly selecting first preset read-write units in the DRAM to be tested until all the first preset read-write units in the DRAM to be tested are traversed;
or jumping and selecting the first preset read-write unit in the DRAM to be tested until all the first preset read-write units in the DRAM to be tested are traversed, wherein the jumping and selecting can be realized by that the first preset read-write units selected twice are not adjacent; alternatively, the first predetermined read/write unit can be selected by the jumping back and forth selection method for the second predetermined read/write unit as in the first embodiment.
EXAMPLE III
The difference between this embodiment and the first or second embodiment is that, in the data writing process, the data written by the adjacent second preset read-write unit is opposite, for example, if the data written by the first second preset read-write unit is 0, the data written by the second preset read-write unit adjacent to the first second preset read-write unit is 1, or the data written by the first second preset read-write unit is 1, the data written by the second preset read-write unit adjacent to the first second preset read-write unit is 0;
in the three models listed in the first embodiment, the parity of the number of the second preset read-write units corresponding to the first preset read-write unit is determined, and if the number of the second preset read-write units is an odd number, the data written by the ith second preset read-write unit corresponding to each first preset read-write unit is the same as the data written by the max-i +1 th second preset read-write unit; if the number of the first preset read-write units is even, the data written by the ith second preset read-write unit corresponding to each first preset read-write unit is opposite to the data written by the max-i + 1 second preset read-write units;
specifically, for the first model, as shown in fig. 4, when data writing is performed, when max is an even number, 0 is written in the first column and the last column, 1 is written in the second column and the second last column, 0 is written in the third column and the third last column, and so on, in the figure, W1 represents the first writing in the corresponding row, W2 represents the second writing, and W3 represents the third writing;
correspondingly, as shown in fig. 5, when data reading is performed, 0 is written in the first column and the last column, 1 is read in the second column and the second last column, 0 is read in the third column and the third last column, and so on, wherein R1 represents the first reading in the corresponding row, R2 represents the second reading, and R3 represents the third reading.
In FIGS. 4 and 5, D represents 0 and/D represents 1.
For the second model, as shown in fig. 6, when data writing is performed, when max is an even number, 0 is written in the first and last rows, 1 is written in the second and second last rows, 0 is written in the third and third last rows, and so on, in the figure, W1 represents the first writing in the corresponding column, W2 represents the second writing, and W3 represents the third writing;
correspondingly, as shown in fig. 7, when data reading is performed, 0 is written in the first row and the last row, 1 is read in the second row and the second last row, 0 is read in the third row and the third last row, and so on, where R1 represents the first reading in the corresponding column, R2 represents the second reading, and R3 represents the third reading.
In FIGS. 6 and 7, D represents 0 and/D represents 1.
For the third model, as shown in fig. 8, when data writing is performed, when max is 8, for a memory cell corresponding to a first row and a first column, 0 is written to a first bank and a last bank, that is, an eighth bank, 1 is written to a second bank and a penultimate bank, that is, a seventh bank, 0 is written to a third bank and a penultimate bank, that is, a sixth bank, and 1 is written to a fourth bank and a fifth bank, where W1 represents first writing at a corresponding row, W2 represents second writing, W3 represents third writing, and W4 represents fourth writing;
correspondingly, as shown in fig. 9, when data reading is performed, for the memory cells corresponding to the first row and the first column, the first bank and the last bank, i.e., the eighth bank read 0, the second bank and the second last bank, i.e., the seventh bank read 1, the third bank and the third last bank, i.e., the sixth bank read 0, the fourth bank and the fifth bank read 1 are read 1, in which R1 represents the first read at the corresponding column, R2 represents the second read, R3 represents the third read, and R4 represents the fourth read;
in FIGS. 8 and 9, D represents 0 and/D represents 1.
Example four
Referring to fig. 2, a testing apparatus for a DRAM includes:
the data writing module is used for jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written in the storage array of the DRAM to be tested, and obtaining a data writing result;
the data reading module is used for sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process and reading the corresponding data until the data of the storage array of the DRAM to be tested are all read, so that a data reading result is obtained;
and the comparison module is used for obtaining the test result of the DRAM to be tested according to the data writing result and the data reading result.
EXAMPLE five
A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements each step in a testing method of a DRAM in any one of the first to third embodiments.
Example six
Referring to fig. 3, the electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for testing a DRAM in any one of the first to third embodiments.
In summary, according to the test method and apparatus for the DRAM, the computer readable storage medium and the electronic device provided by the present invention, when testing the DRAM, a second preset read-write unit is jumped back and forth to each first preset read-write unit of the DRAM and data is written until the data is written into the storage array of the DRAM to be tested, when data is read, data is jumped and read according to the sequence corresponding to the data writing and the corresponding data, a test result of the DRAM is obtained according to the data result of the jump writing and the data result of the corresponding jump reading, and in the data writing process, the data written into the adjacent second preset read-write units are opposite; the method has the advantages that the actual use environment of a user can be well simulated in a jumping read-write mode, the weak cell and the fault unit in the DRAM can be better detected, the problem that the conventional algorithm cannot detect is solved, the fault coverage rate can be improved, the read-write complexity is reduced in a back-and-forth jumping read-write mode, the test time is saved, the generation cost is reduced, various different models are designed to carry out back-and-forth jumping read-write, the applicability is good, and the method can be used for all DRAM products.
In the above embodiments provided in the present application, it should be understood that the disclosed method, apparatus, computer-readable storage medium, and electronic device may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple components or modules may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or components or modules, and may be in an electrical, mechanical or other form.
The components described as separate parts may or may not be physically separate, and parts displayed as components may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the components can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention, which is substantially or partly contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (7)
1. A method for testing a DRAM, comprising the steps of:
jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written in the storage array of the DRAM to be tested, and obtaining a data writing result;
sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process until the data of the storage array of the DRAM to be tested are all read, and obtaining a data reading result;
obtaining a test result of the DRAM to be tested according to the data writing result and the data reading result;
the first preset read-write units are rows, and the second preset read-write units are columns;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each row in each bank of the DRAMs to be tested:
selecting the ith column of the row and writing data, then jumping to select the max-i +1 th column of the row and writing data, wherein max represents the number of columns contained in the row, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the ith column of the row and writing data until each column of the row is written with data;
or the like, or a combination thereof,
the first preset read-write units are columns, and the second preset read-write units are rows;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each column in each bank of the DRAM to be tested:
selecting the ith row of the column and writing data, then jumping to select the max-i +1 row of the column and writing data, wherein max represents the number of the rows contained in the column, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the ith row of the column and writing data until each row of the column is written with data;
or the like, or, alternatively,
the first preset read-write unit is a row and a column, and the second preset read-write unit is a bank;
the step of jumping and selecting a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each rank of the DRAMs to be tested:
selecting the rank of the ith bank and writing data in the rank, then jumping and selecting the rank of the max-i +1 th bank and writing data in the rank, wherein max represents the number of the banks of the DRAM to be tested, and the initial value of i is 1;
and i = i +1, and returning to execute the step of selecting the rank of the ith bank and writing data until the rank of each bank writes data.
2. The method according to claim 1, wherein each first preset read-write unit in the DRAM to be tested is sequentially selected from small to large according to the number of the first preset read-write unit; alternatively, the first and second electrodes may be,
randomly selecting a first preset read-write unit in the DRAM to be tested until all the first preset read-write units in the DRAM to be tested are traversed; alternatively, the first and second electrodes may be,
and jumping and selecting the first preset read-write unit in the DRAM to be tested until all the first preset read-write units in the DRAM to be tested are traversed.
3. The method as claimed in any one of claims 1 to 2, wherein during the data writing process, the data written by the adjacent second predetermined read/write unit is opposite.
4. The method according to claim 3, wherein the parity of the number of the second predetermined read/write units corresponding to the first predetermined read/write unit is determined, and if the parity is an odd number, the data written by the ith second predetermined read/write unit corresponding to each first predetermined read/write unit is the same as the data written by the max-i +1 second predetermined read/write units; and if the number of the first preset reading-writing units is an even number, the data written by the ith second preset reading-writing unit corresponding to each first preset reading-writing unit is opposite to the data written by the max-i +1 second preset reading-writing unit.
5. A test apparatus for a DRAM, comprising:
the data writing module is used for jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written in the storage array of the DRAM to be tested, and obtaining a data writing result;
the first preset read-write units are rows, and the second preset read-write units are columns;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each row in each bank of the DRAM to be tested:
selecting the ith column of the row and writing data, then jumping to select the max-i +1 th column of the row and writing data, wherein max represents the number of columns contained in the row, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the ith column of the row and writing data until each column of the row is written with data;
or the like, or, alternatively,
the first preset read-write units are columns, and the second preset read-write units are rows;
the step of jumping and selecting a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each column in each bank of the DRAMs to be tested:
selecting the ith row of the column and writing data, then jumping to select the max-i +1 row of the column and writing data, wherein max represents the number of the rows contained in the column, and the initial value of i is 1;
making i = i +1, and returning to execute the step of selecting the ith row of the column and writing data until each row of the column is written with data;
or the like, or, alternatively,
the first preset read-write unit is a row and a column, and the second preset read-write unit is a bank;
the step of jumping to select a second preset read-write unit on each first preset read-write unit of the DRAM to be tested and writing data until the data are written into the storage array of the DRAM to be tested comprises the following steps:
in each rank of the DRAMs to be tested:
selecting the rank of the ith bank and writing data in the rank, then jumping and selecting the rank of the max-i +1 th bank and writing data in the rank, wherein max represents the number of the banks of the DRAM to be tested, and the initial value of i is 1;
enabling i = i +1, and returning to execute the step of selecting the row and column of the ith bank and writing data until the row and column of each bank write data;
the data reading module is used for sequentially selecting a corresponding second preset read-write unit from each corresponding first preset read-write unit of the DRAM to be tested and reading corresponding data according to the second preset read-write unit selected from each first preset read-write unit and the corresponding written data in the data writing process until the data of the storage array of the DRAM to be tested are all read, and obtaining a data reading result;
and the comparison module is used for obtaining the test result of the DRAM to be tested according to the data writing result and the data reading result.
6. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of a method for testing a DRAM according to any one of claims 1 to 4.
7. An electronic device comprising a memory, a processor and a computer program stored on the memory and running on the processor, wherein the processor implements the steps of a method of testing a DRAM as claimed in any one of claims 1 to 4 when executing the computer program.
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