CN112331256A

CN112331256A - DRAM test method and device, readable storage medium and electronic equipment

Info

Publication number: CN112331256A
Application number: CN202011267707.0A
Authority: CN
Inventors: 孙成思; 孙日欣; 刘冲; 雷泰
Original assignee: Biwin Storage Technology Co Ltd
Current assignee: Biwin Storage Technology Co Ltd
Priority date: 2020-11-13
Filing date: 2020-11-13
Publication date: 2021-02-05

Abstract

The invention discloses a DRAM test method, a device, a readable storage medium and an electronic device, wherein a DRAM to be tested is tested in two rounds, all storage units written with preset test data are subjected to surrounding access, a comparison result is obtained in the surrounding access process, and a final test result is obtained through the comparison result of the two rounds of testing.

Description

DRAM test method and device, readable storage medium and electronic equipment

Technical Field

The invention relates to the field of DRAM chip testing, in particular to a DRAM testing method, a DRAM testing device, a readable storage medium and electronic equipment.

Background

A Dynamic Random Access Memory (DRAM) is a semiconductor Memory, which is an indispensable component of contemporary computer systems, and the sub-platform may include a Double Data Rate (DDR) module applied to a personal computer or a server and a Low Power consumption Memory (LPDDR) chip applied to an embedded ARM architecture.

The basic memory cell of the DRAM is a cell, and a computer and an embedded system perform data storage and read-write by writing a high level or a low level in the cell, but due to the influence of a manufacturing process, the memory cell may cause data storage failure during read-write, so that the access rate is low.

In order to solve the above problems, the current DRAM adopts a burst read/write mode, and as long as the initial column address and the burst length are specified, the memory will automatically perform read/write operations on the corresponding number of following memory cells in sequence. That is, the read/write operation is performed in a memory array in units of Burst Lengths (BL), and the read/write operation is performed for a multi-bit (e.g., 8 or 16-bit) column address at a time, and data consisting of 0 and 1 is accessed for each burst length. For example, the address of the location is 0 row, the burst length is 8 bits, 1bit of data is written in each bit in the space from 0 row and column to 0 row and column 7 column, the total is 8 bits, the second burst length is from 0 row and column to 15 column, and so on. When all the Memory locations in a row are written, a Memory Controller (MC) locates the address of the next row and continues the same operation. The method enables data access to be more efficient, but the method has the defects that multiple cell faults such as Bridging Fault (BF) and Coupling Fault (CF) between cells are difficult to excite through the memory test performed by the method, the coverage rate of the test faults is low, and the reliability of the test result is low.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: a DRAM test method, a device, a readable storage medium and an electronic device are provided, which can improve the fault coverage rate when testing the DRAM.

In order to solve the technical problems, the invention adopts a technical scheme that:

a DRAM test method includes the steps:

performing two rounds of tests on the DRAM to be tested to respectively obtain a first comparison result and a second comparison result;

the test comprises the following steps:

writing preset test data into the DRAM to be tested until all memory cells of the DRAM to be tested are written with data;

traversing the DRAM to be tested by taking a preset burst length as a unit until the whole storage array of the DRAM to be tested is traversed;

for the traversed target storage unit corresponding to the preset burst length, writing the inverse number of the preset test data into the target storage unit, performing surrounding reading data on the target storage unit, and comparing the read data with the correspondingly written data;

the preset test data of the first round of test is the inverse number of the preset test data of the second round of test;

and obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

In order to solve the technical problem, the invention adopts another technical scheme as follows:

a DRAM test apparatus, comprising:

the data read-write module is used for carrying out two-round test on the DRAM to be tested to respectively obtain a first comparison result and a second comparison result;

the test comprises the following steps:

and the test module is used for obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result.

a computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned DRAM test method.

an electronic device comprises a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the DRAM test method when executing the computer program.

The invention has the beneficial effects that: the invention carries out two-round test on the DRAM to be tested, carries out surrounding access on all storage units written with preset test data, obtains a comparison result in the surrounding access process, and obtains a final test result through the comparison result of the two-round test.

Drawings

FIG. 1 is a flow chart of steps in a DRAM test method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a DRAM test apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a DRAM array to be tested with data written in a first predetermined unit of row in the DRAM test method according to the embodiment of the present invention;

FIG. 5 is a diagram illustrating a traversal procedure in a DRAM test method according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a memory cell to be accessed around a target memory cell in a DRAM test method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of clockwise wrap around access in a DRAM test method according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a DRAM array to be tested with data written in a first predetermined unit of columns according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of counterclockwise wrap-around access in the DRAM test method according to the embodiment of the present invention.

Detailed Description

In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

As shown in fig. 1, an embodiment of the present invention provides a method for testing a DRAM, including the steps of:

the test comprises the following steps:

From the above description, the beneficial effects of the present invention are: the invention carries out two-round test on the DRAM to be tested, carries out surrounding access on all storage units written with preset test data, obtains a comparison result in the surrounding access process, and obtains a final test result through the comparison result of the two-round test.

Further, performing wrap-around read data on the target memory cell includes:

determining a storage unit adjacent to the target storage unit to obtain an adjacent storage unit set;

reading data of adjacent storage units in the adjacent storage unit set one by one according to a preset sequence, and comparing the read data with the correspondingly written data until each adjacent storage unit in the adjacent storage unit set is read;

and reading the data of the target storage unit, and comparing the read data with the inverse number of the preset test data.

Further, reading data of adjacent memory cells in the set of adjacent memory cells one by one according to a preset sequence includes:

and taking the target storage unit as a center, reading data of the adjacent storage units corresponding to the 8 azimuths of the target storage unit one by one according to a preset sequence, and if the adjacent storage units do not exist in any azimuth, omitting the data reading of the adjacent storage units corresponding to the azimuth.

According to the above description, the target storage unit is taken as the center, the adjacent storage units corresponding to the 8 orientations of the target storage unit are read one by one according to the preset sequence, and the read data and the correspondingly written data are compared until each adjacent storage unit set in the adjacent storage unit sets is read, so that the previous test blind area can be covered, the fault between the cells can be excited, and the fault coverage rate during the test can be improved.

Further, after comparing the read data with the corresponding written data, the method further comprises the following steps:

writing the preset test data into the compared storage unit;

the compared memory cell includes the adjacent memory cell and the target memory cell.

According to the description, the dynamic memory has the refreshing characteristic, the preset test data written into the memory unit is prevented from being lost by writing the preset test data into the compared memory unit, the actual use environment of a user on the DRAM chip can be well simulated, and the reliability and the accuracy of the test are ensured.

Further, writing preset test data into the DRAM to be tested until all memory cells of the DRAM to be tested write data includes:

and writing the preset test data from the low-order address of each first preset read-write unit of the DRAM to be tested by taking the preset burst length as a unit until all the memory units of the DRAM to be tested write the data.

As can be seen from the above description, by writing the preset test data into the DRAM to be tested in units of burst lengths, the data writing speed can be increased, and the time complexity is low, which is suitable for mass production tests.

Further, the preset sequence includes a clockwise direction or a counterclockwise direction.

According to the above description, the preset sequence comprises a clockwise direction or a counterclockwise direction, so that the tester can select the test sequence of the surrounding access by himself, and the flexibility is high.

Further, the obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result includes:

if the first comparison result and the second comparison result are both consistent, the test result is successful; otherwise, the test result is failure.

From the above description, it can be known that the first comparison result and the second comparison result are obtained by two tests respectively, so that the chip defects which are difficult to find can be detected, the fault coverage rate during the test is improved, and the reliability of the test is ensured.

As shown in fig. 2, another embodiment of the present invention provides a DRAM test apparatus, including:

the test comprises the following steps:

Another embodiment of the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the above-described DRAM test method.

As shown in fig. 3, another embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the DRAM test method.

The above-mentioned DRAM test method, apparatus, computer readable storage medium and electronic device of the present invention can be applied to any type of DRAM test, such as DDR and LPDDR generations, and are described below by way of specific embodiments:

example one

Referring to fig. 1, a DRAM test method includes the steps of:

s1, performing two-round test on the DRAM to be tested to respectively obtain a first comparison result and a second comparison result;

the test comprises the following steps:

s11, writing preset test data into the DRAM to be tested until all memory cells of the DRAM to be tested write data;

specifically, writing the preset test data from the low-order address of each first preset read-write unit of the DRAM to be tested by taking a preset burst length as a unit until all the memory units of the DRAM to be tested write data;

the first preset read-write unit can be flexibly set according to actual needs, for example, can be set as a column or a row;

the Burst Length (BL) is determined by JEDEC standards, and can also be freely set, that is, a plurality of bits (for example, 8 bits or 16 bits) are operated at a time to perform corresponding read and write operations, for example, when row-based write data is performed, if the located address is 0 row and the Burst Length is 8 bits, the first 8-bit value of the data to be written is simultaneously written at the position of 0 row and 0 column, then 9-16 bits of the data to be written are written in the second Burst Length, and the writing is continued until all the storage positions of 0 row are written, and then the address of the next row is relocated, and the operation of the previous row is continued until the data is written in the full disk, and the read data is also similar operation;

in this embodiment, the first preset cells are rows, as shown in fig. 4;

for example, writing preset test data from the first column of the first row, after writing the first row, writing the preset test data from the first column of the second row, and so on until each row of the DRAM to be tested writes data;

s12, traversing the DRAM to be tested by taking a preset burst length as a unit until the whole storage array of the DRAM to be tested is traversed;

writing the inverse number of the preset test data into the target storage unit for the traversed target storage unit corresponding to the preset burst length, and determining a storage unit adjacent to the target storage unit to obtain an adjacent storage unit set;

specifically, performing wrap-around read data on the target storage unit includes:

s121, determining a storage unit adjacent to the target storage unit to obtain an adjacent storage unit set;

s122, reading data of adjacent storage units in the adjacent storage unit set one by one according to a preset sequence, and comparing the read data with correspondingly written data until each adjacent storage unit in the adjacent storage unit set is read;

s123, reading the data of the target storage unit, and comparing the read data with the inverse number of the preset test data;

s124, reading the data of the target storage unit, and comparing the read data with the inverse number of the preset test data;

wherein reading data of adjacent memory cells in the set of adjacent memory cells one by one according to a preset sequence comprises:

taking the target storage unit as a center, reading the adjacent storage units corresponding to 8 orientations of the target storage unit one by one according to a preset sequence, if the adjacent storage unit does not exist in any orientation, omitting the data reading of the adjacent storage unit corresponding to the orientation, and comparing the read data with the correspondingly written data until each adjacent storage unit in the adjacent storage unit set is read;

the preset sequence includes a clockwise direction or a counterclockwise direction, and in this embodiment, the preset sequence is a clockwise direction, as shown in fig. 6 to 7;

reading one by one includes reading at intervals of n memory cells, where n is greater than or equal to 0, and in this embodiment, reading is performed at intervals of 0 memory cells, as shown in fig. 6 to 7;

for example, the storage unit in the W direction is read first, the read data is compared with the data written correspondingly, then the storage unit in the NW direction is read, the read data is compared with the data written correspondingly, then the storage unit in the N direction is read, the read data is compared with the data written correspondingly, and so on, until each adjacent storage unit in the adjacent storage unit set is read;

after comparing the read data with the correspondingly written data, the method also comprises the following steps:

writing the preset test data into the compared storage unit; the compared storage unit comprises the adjacent storage unit and the target storage unit;

after the first round of test is finished, performing a second round of test, wherein the preset test data of the first round of test is the inverse number of the preset test data of the second round of test;

s2, obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result;

if the first comparison result and the second comparison result are both consistent, the test result is successful; otherwise, the test result is failure;

in this embodiment, referring to fig. 4-7 specifically, first, a first round of test is performed on the DRAM to be tested:

defining the written test data as D01010101 … … 0101, and the inverse of D10101010 … … 1010, assuming that the preset burst length BL is 8bit, then D01010101, and/D10101010;

firstly, the address to be positioned is row 0, column 0, the test data D is written from the storage unit corresponding to row 0 and column 0 according to BL, after row 0 is written, the test data D is written from row 1 and column 0, and so on, until the data is written in the whole storage array, as shown in fig. 4;

secondly, all the memory cells are traversed from the 0 th row and the 0 th column of the 0 th row until the whole memory array is traversed, and write/D is carried out on the traversed target memory cells (Victim cells, VC) in the BL, as shown in FIG. 5;

then, with VC as the center, determining adjacent memory cell sets corresponding to VC 8 orientations, as shown in fig. 6, W (west), NW (northwest), N (north), NE (northeast), E (east), SE (southeast), S (south), and SW (southwest), respectively;

if no adjacent storage unit exists in any azimuth of the VC, data reading of the adjacent storage unit corresponding to the azimuth is omitted, for example, if the 0 th column in the 0 th row is VC, the sets of the adjacent storage units corresponding to the VC are S (south), SE (southeast) and E (east), and data reading is performed on the storage units corresponding to the three directions of S (south), SE (southeast) and E (east) one by one according to a preset sequence;

then, the memory cell in the W direction is read, the read data is compared with D, whether there is an error is checked, and D is written as shown in fig. 7 (a);

reading the memory cell in the NW direction, comparing the read data with D, verifying if there is an error, and writing D as shown in fig. 7 (b);

reading the memory cell in the N direction, comparing the read data with D, checking whether there is an error, and writing D, as shown in FIG. 7 (c);

reading the memory cell in the NE direction, comparing the read data with D, verifying whether there is an error, and writing D as shown in fig. 7 (D);

reading the memory cell in the direction E, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 7 (E);

reading the memory cell in the SE direction, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 7 (f);

reading the memory cell in the S direction, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 7 (g);

reading the memory cell in the SW direction, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 7 (h);

reading VC, comparing the read data with/D, checking whether there is error, and writing D, as shown in FIG. 7 (i);

obtaining a first comparison result;

in the second round of test, defining the written test data D as 10101010 and the inverse/D as 01010101, and performing the above steps to obtain a second comparison result;

Example two

Referring to fig. 8-9, a difference between the second embodiment and the first embodiment is that the first predetermined cells are rows, the predetermined sequence is counterclockwise, and the read operation is performed at intervals of 1 memory cell;

specifically, as shown in fig. 8, the located address is row 0 in column 0, test data D is written into the memory cell corresponding to row 0 in column 0 according to BL, that is, test data D is written into row 0 in column 0 to row 0 in column 7, after writing, test data D is written into row 1 in column 0, after writing all rows in column 0 to column 7, then all rows in column 8 to column 15 are written into the memory cell according to the row sequence, and so on, until the data is written into the entire memory array, as shown in fig. 8;

secondly, traversing all the storage units from the 0 th row in the 0 th column until the whole storage array is traversed, and writing/D into a target storage unit (Victim Cell, VC) in the traversed BL;

then, taking VC as a center, determining adjacent storage unit sets corresponding to VC 8 azimuths, namely W (west), NW (northwest), N (north), NE (northeast), E (east), SE (southeast), S (south) and SW (southwest);

then, the memory cell in the S direction is read, the read data is compared with D, whether there is an error is checked, and D is written as shown in fig. 9 (a);

reading the memory cell in the direction E, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 9 (b);

reading the memory cell in the N direction, comparing the read data with D, checking whether there is an error, and writing D, as shown in FIG. 9 (c);

reading the memory cell in the direction W, comparing the read data with D, verifying whether there is an error, and writing D as shown in FIG. 9 (D);

reading the memory cell in the SW direction, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 9 (e);

reading the memory cell in the SE direction, comparing the read data with D, verifying whether there is an error, and writing D, as shown in FIG. 9 (f);

reading the memory cell in the NE direction, comparing the read data with D, verifying whether there is an error, and writing D as shown in fig. 9 (g);

reading the memory cell in the NW direction, comparing the read data with D, verifying if there is an error, and writing D as shown in fig. 9 (h);

reading VC, comparing the read data with/D, checking whether there is error, and writing D, as shown in FIG. 9 (i);

obtaining a first comparison result;

EXAMPLE III

Referring to fig. 2, a DRAM test apparatus includes:

the test comprises the following steps:

Example four

A computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, is capable of implementing the steps of the DRAM test method of one or both embodiments.

EXAMPLE five

Referring to fig. 3, an electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor executes the computer program to implement the steps of the DRAM test method according to the first embodiment or the second embodiment.

In summary, the DRAM testing method, the DRAM testing device, the readable storage medium, and the electronic device according to the present invention perform two-round testing on a DRAM to be tested, perform writing in a unit of a preset burst length during writing preset test data in the DRAM to be tested, can improve data writing speed, have low time complexity, and facilitate mass production testing, perform data reading on adjacent memory cells one by one according to a preset sequence in a process of performing surrounding data reading on a target memory cell, the preset sequence including clockwise and counterclockwise, improve testing flexibility, compare the read data with data written in correspondingly, write the preset test data in a compared memory cell, and avoid that the preset test data written in the memory cells before are lost and close to a user usage environment based on the refresh characteristic of a dynamic memory, by realizing surrounding access to the DRAM to be tested, the test blind area in the prior art is covered, and the chip defects which are difficult to be found in the prior art are detected, so that the faults of multiple storage units such as bridging faults, coupling faults and the like are excited, the fault coverage rate is improved, the reliability of the test result is enhanced, and the product virtues are improved.

In the above embodiments provided in the present application, it should be understood that the disclosed method, apparatus, computer-readable storage medium, and electronic device may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of components or modules may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or components or modules, and may be in an electrical, mechanical or other form.

The components described as separate parts may or may not be physically separate, and parts displayed as components may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the components can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.

Claims

1. A DRAM test method, comprising the steps of:

the test comprises the following steps:

2. The method of claim 1, wherein performing wrap around read data on the target memory cell comprises:

3. The method for testing the DRAM according to claim 2, wherein reading the data of the adjacent memory cells in the adjacent memory cell set one by one according to the preset sequence comprises:

and taking the target storage unit as a center, reading the adjacent storage units corresponding to the 8 azimuths of the target storage unit one by one according to a preset sequence, and if the adjacent storage units do not exist in any azimuth, omitting the data reading of the adjacent storage units corresponding to the azimuth.

4. The method for testing the DRAM according to claim 2, further comprising the step of, after comparing the read data with the corresponding written data:

writing the preset test data into the compared storage unit;

5. The method for testing the DRAM according to claim 1, wherein writing preset test data to the DRAM to be tested until all memory cells of the DRAM to be tested are written with data comprises:

6. A DRAM test method according to any of claims 2 to 4 wherein said predetermined sequence comprises a clockwise or counter-clockwise direction.

7. The method for testing a DRAM according to any one of claims 1 to 5, wherein the obtaining the test result of the DRAM to be tested according to the first comparison result and the second comparison result comprises:

8. A DRAM test apparatus, comprising:

the test comprises the following steps:

9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of a method for testing a DRAM according to any one of claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of a method for testing a DRAM as claimed in any one of claims 1 to 7 when executing the computer program.