CN114464242A - DDR test method, device, controller and storage medium - Google Patents

DDR test method, device, controller and storage medium Download PDF

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CN114464242A
CN114464242A CN202210038194.9A CN202210038194A CN114464242A CN 114464242 A CN114464242 A CN 114464242A CN 202210038194 A CN202210038194 A CN 202210038194A CN 114464242 A CN114464242 A CN 114464242A
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test
test data
data blocks
ddr
unit
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CN114464242B (en
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李创锋
姜莉萍
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Shenzhen Tigo Semiconductor Co ltd
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Shenzhen Tigo Semiconductor Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

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Abstract

The invention relates to a DDR test method, a DDR test device, a controller and a storage medium, and relates to the technical field of semiconductor integrated circuit testing. According to the DDR test method, data are checked twice on DDR memory chips, wherein the first check is used for reading and checking N test data blocks, the DDR memory chips which are checked to be qualified preliminarily are screened out, after the first logical data movement and the second logical data movement, the second check is used for reading and checking the N test data blocks of the testable memory unit, the DDR memory chips which are checked to be qualified in performance are screened out through the two checks, and the problem that errors are prone to occur in results obtained through the test only through the one-time data reading check in the prior art is solved. The data verification result obtained by the DDR test method provided by the invention has reliability, and the accuracy of the test result of the DDR memory chip is further improved.

Description

DDR test method, device, controller and storage medium
Technical Field
The invention relates to the technical field of semiconductor integrated circuit testing, in particular to a DDR testing method, a DDR testing device, a controller and a storage medium.
Background
In the field of DDR memory chip testing, the more types of failures that may exist in a memory chip, the more the test time and the test cost are increased sharply, and since each memory cell may have different states, different types of failures may occur, such as a fixed failure, where the value of one memory cell is fixed at 0 or 1 and is not changed. Transition fault F-a storage cell in a memory array cannot make a transition of 0- >1 or 1- > 0. Coupling failures-short circuits and couplings between memory cells that cause a change to one memory cell necessarily causes a change in the state of another memory cell. Addressing failure-the corresponding address cannot be found correctly. The conventional test method is generally used for performing read data verification on a DDR memory chip only once, and a result obtained by the test is easy to generate errors.
Disclosure of Invention
The invention provides a DDR test method, a DDR test device, a controller and a storage medium, and aims to solve the problem that in the prior art, the accuracy of a test result of a DDR memory chip is low.
In a first aspect, the present invention provides a DDR test method, where the DDR test method includes:
accessing a DDR memory chip to obtain a testable memory unit of the DDR memory chip; the testable memory unit comprises a plurality of storage units;
dividing a plurality of the storage units into N data blocks;
writing test data into the N data blocks according to a preset rule to obtain N test data blocks;
performing read verification on the N test data blocks;
if the read verification result of the N test data blocks is successful, dividing the testable memory unit into four test units; the testable memory unit comprises N test data blocks;
respectively carrying out first logical data movement on the N test data blocks;
performing second logical data movement on the four test units;
performing read verification on the N test data blocks of the testable memory unit;
and if the result of the read verification of the N test data blocks of the testable memory unit is successful, judging the DDR memory chip to be a qualified memory chip.
A further technical solution is that the test data block includes 32 bytes, and writing test data into the N data blocks according to a preset rule includes:
acquiring 32 bytes of sequencing information of the N test data blocks;
and respectively writing test data into 32 bytes of the N test data blocks according to the hexadecimal principle according to the sequencing information.
According to the further technical scheme, the writing of the test data into the 32 bytes of the N test data blocks according to the hexadecimal principle according to the sorting information comprises:
writing first test data into bytes which are sequenced from the first byte to the eighth byte and from the seventeenth byte to the twenty-fourth byte of the N test data blocks according to the sequencing information;
writing second test data into the ninth byte to the sixteenth byte and the twenty fifth byte to the twenty twelfth byte of the N test data blocks according to the sorting information; wherein the second test data is a hexadecimal negation of the first test data.
The further technical solution is that the performing read verification on the N test data blocks includes:
reading the test data one by N test data blocks to obtain first read data;
judging whether the first read data is consistent with the test data;
and if the first read data is consistent with the test data, judging that the verification is successful.
A further technical solution is that the performing the first logical data movement on the N test data blocks respectively includes:
dividing the N test data blocks into a first test data block and a second test data block respectively, wherein the number of bytes of the first test data block is equal to that of the second test data block;
and interchanging the positions of the first test data block and the second test data block.
A further technical solution is that the testable memory unit includes a first test unit, a second test unit, a third test unit, and a fourth test unit, and the performing second logical data movement on the four test units includes:
acquiring initial position information of the first test unit, the second test unit, the third test unit and the fourth test unit;
and performing second logical data movement on the first test unit, the second test unit, the third test unit and the fourth test unit according to the initial position information.
The further technical scheme is that the reading verification is carried out on the N test data blocks of the testable memory unit, and the method comprises the following steps:
reading the test data in the N test data blocks one by one to obtain second read data;
judging whether the second read data is consistent with the test data;
and if the second read data is consistent with the test data, judging that the DDR memory chip is a qualified memory chip, wherein N is an integer greater than 4.
In a second aspect, the invention provides a DDR test apparatus comprising means for performing the method of the first aspect.
In a third aspect, the present invention provides a controller, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
a processor for implementing the steps of the method according to the first aspect when executing a program stored in the memory.
In a fourth aspect, the invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method according to the first aspect.
Has the advantages that: through carrying out twice data check on DDR memory chips, wherein, N test data blocks are read and checked through the first check, the DDR memory chips which are qualified through the first check are screened out, after the first logic data movement and the second logic data movement, the N test data blocks of the testable memory unit are read and checked through the second check, the DDR memory chips with qualified performance are screened out through the twice check, and the problem that errors easily occur in the result obtained through the test of only once data read and check in the prior art is solved. The data verification result obtained by the DDR test method provided by the invention has reliability, and the accuracy of the test result of the DDR memory chip is further improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flowchart of a DDR test method according to embodiment 1 of the present invention;
fig. 2 is a schematic diagram of a first logical data movement according to embodiment 1 of the present invention;
fig. 3 is a schematic diagram illustrating an initial position of a testable memory cell according to embodiment 1 of the present invention;
FIG. 4 is a partial schematic diagram of a second logical data movement provided in embodiment 1 of the present invention;
FIG. 5 is a partial schematic diagram of a second logical data movement provided in embodiment 1 of the present invention;
fig. 6 is a schematic diagram illustrating a location of a testable memory cell after a second logical data move according to embodiment 1 of the present invention;
fig. 7 is a schematic structural diagram of a DDR test device according to embodiment 2 of the present invention;
fig. 8 is a structural diagram of a controller provided in the present invention.
Detailed Description
In order to more fully understand the technical content of the present invention, the technical solution of the present invention will be further described and illustrated with reference to the following specific embodiments, but not limited thereto.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1, an embodiment 1 of the present invention provides a DDR test method, where the DDR test method of the embodiment 1 includes the following steps: S101-S109.
S101, accessing a DDR memory chip to obtain a testable memory unit of the DDR memory chip; the testable memory cell includes a plurality of memory cells.
In the embodiment of the invention, the testable memory unit of the DDR memory chip is obtained by accessing the DDR memory chip, wherein the testable memory unit consists of all the memory units of the DDR memory chip, so that all the memory units of the DDR memory chip can be named as testable memory units.
S102, dividing a plurality of storage units into N data blocks.
Specifically, the testable memory unit of the DDR memory chip may be divided, that is, all the memory units of the DDR memory chip are divided into N data blocks, where the N data blocks have the same length and are 32 bytes. The test of the DDR memory chip can be performed by writing test data to 32 bytes.
S103, writing test data into the N data blocks according to a preset rule to obtain N test data blocks.
Specifically, as described above, the N data blocks are all 32 bytes in length. Test data can be written by writing 32 bytes. After each byte in the N data blocks is written with test data, N test data blocks result, each byte in the test data blocks being written with test data.
In one embodiment, the test data block includes 32 bytes, and the step S103 includes the steps of: S1031-S1032.
And S1031, obtaining the 32-byte sequencing information of the N test data blocks.
Specifically, the order information of 32 bytes of the N test data blocks is obtained to identify the order in which the test data is written, for example, a byte ordered to be the first has certain test data written therein, a byte ordered to be the first has other test data written therein, and so on. In the embodiment of the invention, test data is written into each byte in turn according to the sorting information of 32 bytes.
And S1032, respectively writing test data into 32 bytes of the N test data blocks according to the ordering information and a hexadecimal principle.
Specifically, each of the test data blocks needs to write test data to 32 bytes respectively according to the hexadecimal principle. In an embodiment of the present invention, the following is the test data of the first test data block: the data written by the bytes ordered first to eighth (byte0-7) is: 0x00000001, the negation data of the ninth to sixteenth bytes (byte8-15) according to the hexadecimal principle is: 0 xfffffffe. Then, the data written into the seventeenth to twenty-fourth bytes (byte16-23) in sequence is: 0x00000001, then the byte24-31 ordered twenty-fifth to thirty-second has the negation data according to the hexadecimal principle: 0 xfffffffe. By dividing a test data block into 4 equal parts according to the sorting information, writing 0x00000001 in the first sorting part and 0 xffffffffe in the third sorting part and writing 0 xffffffffe in the second sorting part and the fourth sorting part, the test data is written in at intervals through the division, so that the test result can be more accurate.
In one embodiment, the above step S1032 includes the following steps: S10321-S10322.
S10321, writing the first test data into the byte ordered from the first to the eighth and the byte ordered from the seventeenth to the twenty-fourth of the N test data blocks according to the ordering information.
Specifically, as described above, the data written by the bytes ordered first to eighth (byte0-7) and the bytes ordered seventeenth to twenty-fourth (byte16-23) are: 0x 00000001; the negation data of the byte8-15 ordered as ninth to sixteenth and the byte24-31 ordered as twenty-fifth to thirty-sixth according to the hexadecimal principle are: 0 xfffffffe. By adopting the interval write-back data, whether the performance of the DDR memory chip reaches the standard or not can be more accurately tested when the test data is read, so that the test effect is better.
S10322, writing second test data into the ninth to sixteenth bytes and the twenty fifth to thirty-second bytes of the N test data blocks according to the sorting information; wherein the second test data is a hexadecimal negation of the first test data.
Specifically, the second test data is the hexadecimal negation data of the first test data, where the test data written in the first test data block is only interpreted, and then the test data written in the second test data block is: the data written in the first to eighth byte (byte0-7) and in the seventeenth to twenty-fourth byte (byte16-23) are: 0x 00000002; the negation data of the byte8-15 ordered as ninth to sixteenth and the byte24-31 ordered as twenty-fifth to thirty-sixth according to the hexadecimal principle are: 0 xffffffffd. Obviously, the test data written in the second test data block is different from the test data written in the first test data block, but has a certain rule, and the written data is changed from 0x00000001 to 0x 00000002; from 0 xffffffe to 0 xffffffffd. And repeating the operation in the same order according to the rule until the N data blocks are written into the corresponding test data to obtain the N test data blocks.
S104, performing read verification on the N test data blocks.
Specifically, through the N test data blocks obtained in S103, all bytes of the N test data blocks have been written with corresponding test data, and then the N test data blocks may be verified by reading whether the test data in each byte is consistent with the test data during writing, and when the test data in a certain test data block is inconsistent with the test data during writing, the DDR memory chip that is determined to be defective is determined, and the verification is stopped at this time.
In one embodiment, the above step S104 includes the steps of: S1041-S1043.
S1041, reading the test data from the N test data blocks one by one to obtain first read data.
Specifically, the test data is read one by one for the N test data blocks in sequence, that is, the test data in the byte is read for each byte of the N test data blocks in sequence, so as to obtain first read data.
S1042, determining whether the first read data is consistent with the test data.
Specifically, the current check result can be obtained by judging whether the first read data is consistent with the test data, and if the first read data is inconsistent with the test data, the following steps are not required, and the DDR memory chip can be directly judged to be a failed memory chip. If the data read out of the first byte of the first test data block is 0x00000011, which is obviously different from the test data 0x00000001 written into the byte, the first read data and the test data are determined to be inconsistent, and the DDR memory chip is determined to be a failed memory chip. It should be noted that the data read out of each byte of the N test data blocks needs to be completely consistent with the written test data before it can be determined that the first read data is consistent with the test data, so that the following steps can be continued to continue testing the DDR memory chip.
And S1043, if the first read data is consistent with the test data, determining that the verification is successful.
Specifically, when the read data of each byte of the N test data blocks completely matches the written test data, that is, the first read data matches the test data, the verification result is successful, and the following test steps can be performed.
S105, if the result of the read verification of the N test data blocks is verification success, dividing the testable memory unit into four test units; the testable memory unit includes N test data blocks.
Specifically, when the first read data is identical to the test data, the testable memory cell is divided into four test cells, and the four test cells include N test data blocks.
S106, respectively carrying out first logical data movement on the N test data blocks.
Specifically, as shown in fig. 2, fig. 2 is a schematic diagram of the first logical data movement, each test data block may be divided into an upper half portion 10 and a lower half portion 20, and the position of the upper half portion 10 and the position of the lower half portion 20 are interchanged, thereby completing the first logical data movement.
In one embodiment, the above step S106 includes the steps of: S1061-S1062.
S1061, respectively dividing the N test data blocks into a first test data block and a second test data block, where the number of bytes of the first test data block is equal to the number of bytes of the second test data block.
Specifically, as shown in fig. 2, the N test data blocks are divided into a first test data block and a second test data block, the first test data block is an upper half 10, and the second test data block is a lower half 20, wherein the number of bytes of the first test data block is equal to the number of bytes of the second test data block.
S1062, interchanging positions of the first test data block and the second test data block.
Specifically, the position of the upper half portion 10 and the position of the lower half portion 20 are interchanged, and the first logical data movement is completed.
And S107, carrying out second logical data movement on the four test units.
Specifically, after the first logical data movement is completed, on this basis, the byte order inside the N test data blocks has been changed, and therefore, the second logical data movement is performed on the four test units, so as to completely break the ordering of the bytes inside the N test data blocks, and thus the performance of the DDR memory chip can be better tested when checking data, because the data read from the N test data blocks and the written test data are consistent after the first logical data movement and the second logical data movement of the DDR memory chip with good performance. However, after the DDR memory chip with poor performance is subjected to the first logical data movement and the second logical data movement, the situation that the data read from the N test data blocks is inconsistent with the written test data may occur.
In one embodiment, the memory cells capable of being tested include a first test unit 1, a second test unit 2, a third test unit 3 and a fourth test unit 4, and the step S107 includes the steps of: S1071-S1072.
S1071, acquiring initial position information of the first test unit 1, the second test unit 2, the third test unit 3, and the fourth test unit 4.
Specifically, the whole testable memory cell can be divided into four parts, namely, the first test unit 1, the second test unit 2, the third test unit 3 and the fourth test unit 4, and the initial position is shown in fig. 3.
S1072, performing a second logical data movement on the first test unit, the second test unit, the third test unit, and the fourth test unit according to the initial position information.
Specifically, as shown in fig. 4 and 5, the second logical data movement process is performed first as shown in fig. 4, and then as shown in fig. 5, the position information of the four test units as shown in fig. 6 is obtained. The original ordering of the test data blocks is changed by the second logical data movement, and the position information of the four test units shown in fig. 6, that is, the memory unit can be tested again.
S108, reading and checking the N test data blocks of the testable memory unit.
Specifically, after the first logical data movement and the second logical data movement are performed on the four test units of the testable memory unit, the original sorting information of the N test data blocks is also changed, and further the sorting of each byte of the N test data blocks is also changed, at this time, the N test data blocks of the testable memory unit are read and checked, and the DDR memory chip with better performance can be tested through the checking, because the detection in step S104 is only performed preliminarily, only the DDR memory chips that may be qualified are selected, but through the checking in step S108, the first logical data movement and the checking after the second logical data movement are performed, the DDR memory chips that may be qualified can be detected, and the performance of the DDR memory chips obtained through the detection is better. After the read-write operation is executed on the first test data block, the operations are sequentially and respectively executed on the next test data until all the test data blocks are subjected to the operation of twice verification, so that not only can coupling faults, adjacent vector sensitization faults, leakage faults and the like between different storage units be detected, but also coupling faults and the like between different positions in the same unit can be detected, and the fault coverage rate is further improved. Through the interval read-write operation of adjacent units of a storage unit, the coupling fault detection of continuous memory storage units is covered, and the detection of the mutual influence of the storage unit and nearby units, such as short circuit and the like, is increased.
In one embodiment, step S108 includes the steps of: S1081-S1083.
S1081, the test data in the N test data blocks are read one by one to obtain second read data.
Specifically, the second read data is obtained by reading the test data one by one from the N test data blocks of the testable memory unit. And comparing whether the data of each byte of the N test data blocks of the testable memory unit is consistent with the written test data or not by reading.
S1082, judging whether the second read data is consistent with the test data.
Specifically, as described above, the determination result is obtained by comparing the data of each byte of the N test data blocks of the testable memory unit with the written test data, that is, determining whether the second read data is consistent with the test data in step S1082, and then determining whether the DDR memory chip provides a qualified memory chip.
S1083, if the second read data is consistent with the test data, determining that the DDR memory chip is a qualified memory chip.
Specifically, when the data of each byte of the N test data blocks of the testable memory unit is completely consistent with the written test data, the entire test process is completed, and the DDR memory chip may be determined to be a qualified memory chip.
And S109, if the result of the read verification of the N test data blocks of the testable memory unit is successful, determining that the DDR memory chip is a qualified memory chip, wherein N is an integer greater than 4.
Specifically, if the result of the read verification of the N test data blocks of the testable memory unit is successful, that is, the data of each byte of the N test data blocks of the testable memory unit is completely consistent with the written test data, it may be determined that the DDR memory chip is a qualified memory chip.
Example 2
Referring to fig. 7, an embodiment 2 of the present invention provides a DDR test device 400, and the DDR test device 400 of the embodiment 2 includes: access section 401, first dividing section 402, writing section 403, first verifying section 404, second dividing section 405, first moving section 406, second moving section 407, second verifying section 408, and determining section 409.
An access unit 401, configured to access a DDR memory chip to obtain a testable memory unit of the DDR memory chip; the testable memory cell includes a plurality of memory cells.
A first dividing unit 402, configured to divide a number of the storage units into N data blocks.
A writing unit 403, configured to write test data into the N data blocks according to a preset rule, so as to obtain N test data blocks.
A first checking unit 404, configured to perform read checking on the N test data blocks.
A second dividing unit 405, configured to divide the testable memory unit into four test units if the result of the read verification on the N test data blocks is verification success; the testable memory unit includes N test data blocks.
The first moving unit 406 is configured to perform a first logical data movement on the N test data blocks, respectively.
And a second moving unit 407, configured to perform a second logical data movement on four test units.
The second verification unit 408 is configured to perform read verification on the N test data blocks of the testable memory unit.
A determining unit 409, configured to determine that the DDR memory chip is a qualified memory chip if the result of the read verification on the N test data blocks of the testable memory unit is a successful verification, where N is an integer greater than 4.
In an embodiment, the writing of the test data to the N data blocks according to the preset rule includes:
acquiring 32 bytes of sequencing information of the N test data blocks;
and respectively writing test data into 32 bytes of the N test data blocks according to the hexadecimal principle according to the sequencing information.
In an embodiment, the writing of test data to 32 bytes of the N test data blocks according to hexadecimal principle according to the sorting information includes:
writing first test data into bytes which are sequenced from the first byte to the eighth byte and from the seventeenth byte to the twenty-fourth byte of the N test data blocks according to the sequencing information;
writing second test data into the ninth byte to the sixteenth byte and the twenty fifth byte to the twenty twelfth byte of the N test data blocks according to the sorting information; wherein the second test data is a hexadecimal negation of the first test data.
In an embodiment, the performing read verification on the N test data blocks includes:
reading the test data one by N test data blocks to obtain first read data;
judging whether the first read data is consistent with the test data;
and if the first read data is consistent with the test data, judging that the verification is successful.
In an embodiment, the performing the first logical data movement on the N test data blocks respectively includes:
dividing the N test data blocks into a first test data block and a second test data block respectively, wherein the number of bytes of the first test data block is equal to that of the second test data block;
and interchanging the positions of the first test data block and the second test data block.
In one embodiment, the testable memory unit includes a first test unit, a second test unit, a third test unit, and a fourth test unit, and the performing the second logical data movement on the four test units includes:
acquiring initial position information of the first test unit, the second test unit, the third test unit and the fourth test unit;
and performing second logical data movement on the first test unit, the second test unit, the third test unit and the fourth test unit according to the initial position information.
In one embodiment, the performing read verification on the N test data blocks of the testable memory cells includes:
reading the test data one by one from the N test data blocks of the testable memory unit to obtain second read data;
judging whether the second read data is consistent with the test data;
and if the second read data is consistent with the test data, judging that the DDR memory chip is a qualified memory chip.
Example 3
Referring to fig. 8, the controller according to an embodiment of the present invention includes a processor 111, a communication interface 112, a memory 113, and a communication bus 114, where the processor 111, the communication interface 112, and the memory 113 complete communication with each other through the communication bus 114.
A memory 113 for storing a computer program;
the processor 111 is configured to execute the program stored in the memory 113, and implement the DDR test method provided in embodiment 1.
Embodiment 3 of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by the processor 111, implements the steps of the DDR test method provided in embodiment 1.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A DDR test method, comprising:
accessing a DDR memory chip to obtain a testable memory unit of the DDR memory chip; the testable memory unit comprises a plurality of storage units;
dividing a plurality of the storage units into N data blocks;
writing test data into the N data blocks according to a preset rule to obtain N test data blocks;
performing read verification on the N test data blocks;
if the read verification result of the N test data blocks is successful, dividing the testable memory unit into four test units; the testable memory unit comprises N test data blocks;
respectively carrying out first logical data movement on the N test data blocks;
performing second logical data movement on the four test units;
performing read verification on the N test data blocks of the testable memory unit;
and if the result of the read verification of the N test data blocks of the testable memory unit is successful, judging the DDR memory chip to be a qualified memory chip, wherein N is an integer greater than 4.
2. The DDR test method of claim 1, wherein the test data block comprises 32 bytes, and the writing of the test data to the N data blocks according to the preset rule comprises:
acquiring 32 bytes of sequencing information of the N test data blocks;
and respectively writing test data into 32 bytes of the N test data blocks according to the hexadecimal principle according to the sequencing information.
3. The DDR test method of claim 2, wherein writing test data to 32 bytes of the N test data blocks according to hexadecimal principle according to the sorting information comprises:
writing first test data into bytes which are sequenced from the first byte to the eighth byte and from the seventeenth byte to the twenty-fourth byte of the N test data blocks according to the sequencing information;
writing second test data into the ninth byte to the sixteenth byte and the twenty fifth byte to the twenty twelfth byte of the N test data blocks according to the sorting information; wherein the second test data is a hexadecimal negation of the first test data.
4. The DDR test method of claim 3, wherein the read checking of the N test data blocks comprises:
reading the test data one by N test data blocks to obtain first read data;
judging whether the first read data is consistent with the test data;
and if the first read data is consistent with the test data, judging that the verification is successful.
5. The DDR test method of claim 1, wherein said performing a first logical data move on N test data blocks, respectively, comprises:
dividing the N test data blocks into a first test data block and a second test data block respectively, wherein the number of bytes of the first test data block is equal to that of the second test data block;
and interchanging the positions of the first test data block and the second test data block.
6. The DDR test method of claim 1, wherein the testable memory unit comprises a first test unit, a second test unit, a third test unit, and a fourth test unit, and the performing the second logical data movement on the four test units comprises:
acquiring initial position information of the first test unit, the second test unit, the third test unit and the fourth test unit;
and performing second logical data movement on the first test unit, the second test unit, the third test unit and the fourth test unit according to the initial position information.
7. The DDR test method of claim 1, wherein performing read verification on the N test data blocks of the testable memory cell comprises:
reading the test data in the N test data blocks one by one to obtain second read data;
judging whether the second read data is consistent with the test data;
and if the second read data is consistent with the test data, judging that the DDR memory chip is a qualified memory chip.
8. A DDR test apparatus, comprising means for performing the method of any of claims 1 to 7.
9. The controller is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing the communication between the processor and the memory through the communication bus;
a memory for storing a computer program;
a processor for implementing the steps of the method as claimed in any one of claims 1 to 7 when executing the program stored in the memory.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.
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Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05266694A (en) * 1992-03-23 1993-10-15 Fuji Xerox Co Ltd Memory test system
US5357521A (en) * 1990-02-14 1994-10-18 International Business Machines Corporation Address sensitive memory testing
US5663965A (en) * 1995-10-06 1997-09-02 International Business Machines Corp. Apparatus and method for testing a memory array
JP2002312252A (en) * 2001-04-17 2002-10-25 Nec Corp Memory diagnostic device and diagnostic method
WO2004104840A2 (en) * 2003-05-20 2004-12-02 Cray Inc. Memory with bit swapping on the fly and testing
CN1577629A (en) * 2003-07-29 2005-02-09 华为技术有限公司 FLASH internal unit testing method
KR20080004671A (en) * 2006-07-06 2008-01-10 주식회사 대우일렉트로닉스 Method for controlling dynamically ddr
JP2008009614A (en) * 2006-06-28 2008-01-17 Tdk Corp Memory controller, memory system, and memory control method
JP2009259329A (en) * 2008-04-16 2009-11-05 Toshiba Corp Semiconductor integrated circuit device
US20150279485A1 (en) * 2014-03-28 2015-10-01 Lenovo (Singapore) Pte, Ltd. Advanced memory test diagnostics
CN105719702A (en) * 2016-01-26 2016-06-29 中国科学院微电子研究所 Improved memory error detection method and device
JP2017123207A (en) * 2016-01-04 2017-07-13 株式会社東芝 Memory inspection device
CN107430533A (en) * 2015-09-30 2017-12-01 华为技术有限公司 A kind of data verification method and device
US20180046541A1 (en) * 2016-08-15 2018-02-15 Samsung Electronics Co., Ltd. Dram assist error correction mechanism for ddr sdram interface
CN112185453A (en) * 2020-10-09 2021-01-05 深圳佰维存储科技股份有限公司 Read interference test method and device, computer readable storage medium and electronic equipment
CN112331256A (en) * 2020-11-13 2021-02-05 深圳佰维存储科技股份有限公司 DRAM test method and device, readable storage medium and electronic equipment
CN112349341A (en) * 2020-11-09 2021-02-09 深圳佰维存储科技股份有限公司 LPDDR test method, device, readable storage medium and electronic equipment
CN112420115A (en) * 2020-11-05 2021-02-26 深圳市宏旺微电子有限公司 Fault detection method for dynamic random access memory

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357521A (en) * 1990-02-14 1994-10-18 International Business Machines Corporation Address sensitive memory testing
JPH05266694A (en) * 1992-03-23 1993-10-15 Fuji Xerox Co Ltd Memory test system
US5663965A (en) * 1995-10-06 1997-09-02 International Business Machines Corp. Apparatus and method for testing a memory array
JP2002312252A (en) * 2001-04-17 2002-10-25 Nec Corp Memory diagnostic device and diagnostic method
WO2004104840A2 (en) * 2003-05-20 2004-12-02 Cray Inc. Memory with bit swapping on the fly and testing
CN1577629A (en) * 2003-07-29 2005-02-09 华为技术有限公司 FLASH internal unit testing method
JP2008009614A (en) * 2006-06-28 2008-01-17 Tdk Corp Memory controller, memory system, and memory control method
KR20080004671A (en) * 2006-07-06 2008-01-10 주식회사 대우일렉트로닉스 Method for controlling dynamically ddr
JP2009259329A (en) * 2008-04-16 2009-11-05 Toshiba Corp Semiconductor integrated circuit device
US20150279485A1 (en) * 2014-03-28 2015-10-01 Lenovo (Singapore) Pte, Ltd. Advanced memory test diagnostics
CN107430533A (en) * 2015-09-30 2017-12-01 华为技术有限公司 A kind of data verification method and device
JP2017123207A (en) * 2016-01-04 2017-07-13 株式会社東芝 Memory inspection device
CN105719702A (en) * 2016-01-26 2016-06-29 中国科学院微电子研究所 Improved memory error detection method and device
US20180046541A1 (en) * 2016-08-15 2018-02-15 Samsung Electronics Co., Ltd. Dram assist error correction mechanism for ddr sdram interface
CN112185453A (en) * 2020-10-09 2021-01-05 深圳佰维存储科技股份有限公司 Read interference test method and device, computer readable storage medium and electronic equipment
CN112420115A (en) * 2020-11-05 2021-02-26 深圳市宏旺微电子有限公司 Fault detection method for dynamic random access memory
CN112349341A (en) * 2020-11-09 2021-02-09 深圳佰维存储科技股份有限公司 LPDDR test method, device, readable storage medium and electronic equipment
CN112331256A (en) * 2020-11-13 2021-02-05 深圳佰维存储科技股份有限公司 DRAM test method and device, readable storage medium and electronic equipment

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