CN113889176A - Method, device and equipment for testing storage unit of DDR (double data Rate) chip and storage medium - Google Patents
Method, device and equipment for testing storage unit of DDR (double data Rate) chip and storage medium Download PDFInfo
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Abstract
The invention relates to a method, a device and equipment for testing a storage unit of a DDR (double data rate) chip and a storage medium, and relates to the field of semiconductor testing. The method comprises the following steps: writing data into each storage unit of the DDR chip; selecting a storage unit as a storage unit to be tested, and recording the storage units around the storage unit to be tested as first data; carrying out logic operation on the storage unit to be tested to obtain an operation result; recording storage units around the storage unit to be tested as second data; comparing the logical operation result with a preset expected value to obtain a first comparison result; comparing the first data with the second data to obtain a second comparison result; and determining the test result of the memory unit to be tested according to the first comparison result and the second comparison result. The invention can detect the sensitivity of the DDR chip memory unit to different data by carrying out logic operation and verification on the memory unit, and can carry out omnibearing detection on the DDR chip memory unit quickly and accurately by comparing the verification result with the first data and the second data.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a method, a device, equipment and a storage medium for testing a storage unit of a DDR (double data rate) chip.
Background
Today, with the rapid development of technology, semiconductor technology is continuously developed, and with the increasingly shrinking of elements such as transistors and diodes, the density of integrated circuit chips is increasing. The increasing number of wires between the integrated circuit chip and the circuit leads to more and more frequent failures of the integrated circuit chip. To date, fault detection of integrated circuits has become a major and difficult point in the research of integrated circuit technology.
Memory sensing is a very critical and independent part of an integrated circuit, mainly for several reasons:
1. the memory is one of the important parts of electronic products, especially embedded system electronic products, and the testing of the embedded integrated circuit chip is mainly to test the memory.
2. The density and complexity index of the memory chip are increased, so that the detection time of the memory is multiplied, and the detection cost is increased.
3. The faults of the memory are various, and in order to improve the test coverage rate and the effectiveness, the complexity and the test time of a test algorithm are continuously increased.
4. The memory is a combination circuit with a regular structure of timing characteristic units, thus making it more difficult to test than a general regular structure circuit.
5. The memory is of a wide variety.
The memory algorithm is designed based on a memory failure model. Common faults are: fix-up failure (SAF), Transition Failure (TF), Coupling Failure (CF), Pattern Sensitive Failure (PSF), Addressing Failure (AF), and Data Retention Failure (DRF). Based on the above fault model, many memory test algorithms have been designed, such as: a five-step chess algorithm, a boundary scanning method, a running method, a March algorithm and the like. The most common is the March algorithm, from a simpler MATS algorithm to a complex March series algorithm, the fault coverage rate is gradually improved, the detection time is increased, and the test cost is increased more and more. Therefore, fast and accurate memory sensing methods are the focus of research.
Disclosure of Invention
The invention provides a method and a device for testing a storage unit of a DDR (double data rate) chip and a storage medium, which are used for solving the problems of long detection time and high detection cost of the traditional method for detecting the DDR chip.
In a first aspect, the present invention provides a method for testing a memory unit of a DDR chip, where the method includes:
writing data into each storage unit of the DDR chip;
selecting a storage unit of the DDR chip as a storage unit to be tested, and recording first data in the storage unit in a preset area around the storage unit to be tested;
performing logic operation on the data in the storage unit to be tested to obtain a logic operation result;
recording second data in the storage unit in a preset area around the storage unit to be tested after the logical operation;
comparing the logical operation result with a preset expected value to obtain a first comparison result;
comparing the first data with the second data to obtain a second comparison result;
and determining the test result of the storage unit to be tested according to the first comparison result and the second comparison result.
In a second aspect, the present invention provides a DDR chip classification method, including:
testing memory units of the DDR chip one by one according to the method of the first aspect;
and classifying the DDR chips according to the test results of all the storage units of the DDR chips and a preset classification standard.
In a third aspect, the present invention provides a DDR chip memory cell detection apparatus, including a unit for executing the method for testing a memory cell of a DDR chip according to the first aspect.
In a fourth aspect, the present invention provides a DDR chip sorting device, including a unit for executing the DDR chip sorting method according to the second aspect.
In a fifth aspect, the present invention provides a detection device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus;
a memory for storing a computer program;
the processor is configured to implement the method for testing the memory unit of the DDR chip according to the first aspect or the method for classifying the DDR chip according to the second aspect when executing the program stored in the memory.
In a sixth aspect, the present invention provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the method for testing the memory cells of the DDR chip according to the first aspect, or the method for sorting the DDR chip according to the second aspect.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
the method provided by the embodiment of the invention can more comprehensively check the storage performance of the storage unit of the DDR chip by using different data from the test point of view, can detect the sensitivity of the storage unit of the DDR chip to different data by performing logic operation on the storage unit, and can improve the speed and the accuracy of the detection on the storage unit of the DDR chip. The DDR chip which meets the storage function can be found out by a user, and the failed DDR chip can be found out in time.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic flowchart illustrating a method for testing a memory cell of a DDR chip according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a to-be-tested unit in a peripheral preset area according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of a DDR chip classification method according to an embodiment of the present invention;
fig. 4 is a block diagram of a memory cell testing apparatus of a DDR chip according to an embodiment of the present invention;
fig. 5 is a block diagram of a DDR chip sorting device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a testing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a method for testing a memory cell of a DDR chip according to an embodiment of the present invention. The flow chart provides a method for testing a memory unit of a DDR chip, and the method can be applied to the field of semiconductor testing. The method specifically comprises the following steps:
and S101, writing data into each memory cell of the DDR chip.
In specific implementation, the DDR chip is a double-data-rate synchronous dynamic random access memory, and belongs to one of memories. The purpose of writing data into the DDR chip is to perform coverage detection on the DDR chip by using all written data so as to detect the sensitivity of a memory unit of the DDR chip to different data.
The write data is written with 0000 or 1111(4 bits) as data. If the memory cell is 32bit, 32 0 s are formed. And traversing all the memory units of the DDR chip by using the data, and filling the data into all the memory units of the DDR chip. By traversing all the storage units, whether the values read from all the storage units are the data filled before is checked. Whether the chip has Addressing Failure (AF) is judged by detecting the data in the storage unit, if the data in the storage unit is not the expected data, the addressing failure is indicated, and the chip cannot normally work and operate. If the data in the storage unit is the expected first data, the data traversal is successful, and the first data is successfully addressed and written.
S102, selecting a storage unit of the DDR chip as a storage unit to be tested, and recording first data in the storage unit in a preset area around the storage unit to be tested.
In a specific implementation, the memory cell in the DDR chip is the minimum memory unit in the DDR chip. Recording data in a storage unit in a preset area around a storage unit to be tested as first data, wherein the first data is data in the storage unit in the preset area. By operating the selected memory unit to be tested, whether the memory unit is read or written, if the data of the memory unit in the peripheral preset area is influenced, the data of the memory unit in the peripheral preset area is influenced when the memory unit to be tested is subjected to data operation, and meanwhile, the data storage capability of the DDR chip is poor, so that the effect cannot occur in a good DDR chip.
Referring to fig. 2, the preset regions include the following regions: two memory cells 102 located on the upper side of the memory cell 101 to be tested; two memory cells 103 located on the left side of the memory cell 101 to be tested; two memory cells 104 located on the right side of the memory cell 101 under test and two memory cells 105 located on the lower side of the memory cell 101 under test.
S103, performing logical operation on the data in the storage unit to be tested to obtain a logical operation result.
In a specific implementation, the purpose of performing a logic operation on data in a memory cell to be tested is to verify whether the internal data in the memory cell to be tested can be normally converted, so as to obtain a desired expected value. The logical operation includes a not operation, an or operation, an and operation, and an not operation. After the logical operation, new data can be obtained, and the new data is the logical operation result. For example, when the write data in a memory cell is 0000, and the non-operation is performed on the memory cell, the result is 1111, the data 1111 is the result of the logical operation. Through logic operation, whether the memory cell to be tested can normally convert the internal data can be verified, so that the expected value required by people is achieved. If the data of the memory cell to be tested cannot be converted normally and is always in a certain data, for example, the first data is 0000, the expected value is 1111 through the non-operation, and the result reading the value of the memory cell is 0000 or 0111, it indicates that the memory cell to be tested has a stuck-at fault, is stuck to 0, and cannot be converted into other data. If the read value is consistent with the expected value, the logic operation is successful. In this process, the memory cell to be tested has already been changed to 1111 through logic operation, and the memory cells in the surrounding preset area are all 0000, since the weight of 1111 is lower and the weight of the surrounding 0000 is higher. If the DDR chip memory unit is weak, the data in the memory unit to be tested will change, and the expected value will not be obtained. The logic operation can also verify the validity of each bit of data in each memory cell to be tested, taking a 32-bit DDR chip as an example, each memory cell stores 32 bits of data, for example, all data written is 0, and a new data can be obtained through the logic operation, for example, data (0000) and data (0001) are or-ed, so that data 0001 can be obtained, and the expected value of the memory cell at this time should be 0001, that is, 31 0 and 1 are stored. For the memory cell, the weight of 0 is the largest, the weight of 31/32 is 96.875%, and the weight of 1 is only 1/32 is 3.125%, so that in the memory cell, in the process of logic operation, if the chip is weak, operation failure may occur, and 1 is coupled by 0, resulting in that the obtained true second data is 0000. Therefore, the coupling failure may occur in the same memory cell in addition to the coupling failure between the memory cells. Carry out logical operation to 32 memory cell, can be accurate operate each bit, check whether each bit can both normally convert (0- >1 and 1- >0), just can more effective quick and independent detection each memory cell have unusually.
And S104, recording second data in the storage unit in the preset area around the storage unit to be tested after the logic operation.
In a specific implementation, the memory cell in the DDR chip is the minimum memory unit in the DDR chip. And performing logical operation on the data in the storage unit to be tested according to a preset storage unit to be tested, and recording the data in the storage unit in a preset area around the storage unit to be tested as second data after a logical operation result is obtained, wherein the second data is the data in the storage unit in the preset area. After the logical operation is performed on the memory cell to be tested, in order to prevent the memory cell in the peripheral preset area from generating a coupling fault due to the read operation performed on the memory cell to be tested, it is necessary to read data from the memory cell in the peripheral preset area and determine whether the value in the memory cell in the peripheral preset area changes. If the values in the storage units in the peripheral preset area are not changed, the coupling fault is not generated; if the value in the storage unit in the peripheral preset area changes, the coupling fault of the storage unit to be tested is shown, and the DDR chip is abnormal.
Referring to fig. 2, the preset regions include the following regions: two memory cells 102 located on the upper side of the memory cell 101 to be tested; two memory cells 103 located on the left side of the memory cell 101 to be tested; two memory cells 104 located on the right side of the memory cell 101 under test and two memory cells 105 located on the lower side of the memory cell 101 under test.
S105, comparing the logical operation result with a preset expected value to obtain a first comparison result.
In one embodiment, the logical operations include NOT, OR, AND, and NOT. And the logical operation result is obtained after the data in the storage unit to be tested is subjected to logical operation, and the obtained result is the logical operation result. The preset expected value is a result obtained after the data in the storage unit to be tested is logically operated, the result obtained after the data in the storage unit to be tested is logically operated is compared with the preset expected value, and the obtained comparison result is a first comparison result.
In an embodiment, the comparing the logical operation result with a preset expected value to obtain a first comparison result includes the following steps:
s201, judging whether the obtained logic operation result is the same as a preset expected value or not.
In specific implementation, through logical operation, whether the memory unit to be tested can normally convert the data stored in the memory unit to be tested can be checked. And comparing the result of the logic operation of the data in the storage unit to be tested with a preset expected value, and judging whether the two data are the same.
S202, if the obtained logical operation result is the same as the preset expected value, judging that the first comparison result is a pass.
In specific implementation, the result of the logical operation on the data in the memory cell to be tested is compared with a preset expected value. If the two values are the same, the first comparison result is passed.
S203, if the obtained logical operation result is different from the preset expected value, determining that the first comparison result is a fail.
In specific implementation, the result of the logical operation on the data in the memory cell to be tested is compared with a preset expected value. If the two values are different, the first comparison result is a fail.
S106, comparing the first data with the second data to obtain a second comparison result.
In specific implementation, the first data is obtained by recording data in a storage unit in a preset area around a storage unit to be tested as first data according to a preset storage unit to be tested; and the second data is obtained by performing logical operation on the data in the storage unit to be tested according to a preset storage unit to be tested, and recording the data in the storage unit in a preset area around the storage unit to be tested as the second data after a logical operation result is obtained. The second comparison result is a result obtained by comparing the first data with the second data, and is the second comparison result.
In an embodiment, the step of comparing the first data with the second data to obtain a second comparison result includes the following steps:
s301, judging whether the first data is the same as the second data.
In specific implementation, the obtained first data and the second data are compared, and whether the values in the two data are the same or not is judged.
S302, if the first data is the same as the second data, the second comparison result is judged to be pass.
In a specific implementation, the values in the first data and the second data are compared, and if the two values are the same, the second comparison result is a pass.
S303, if the first data is different from the second data, judging that the second comparison result is a fail.
In a specific implementation, the values in the first data and the second data are compared, and if the two values are different, the second comparison result is a fail.
S107, determining the test result of the storage unit to be tested according to the first comparison result and the second comparison result.
In specific implementation, if the first comparison result and the second comparison result are both pass, determining that the test result of the unit to be tested is qualified; and if any one of the first comparison result and the second comparison result is not qualified, determining that the test result of the unit to be tested is unqualified. In addition to the logical operations such as not operation, or, and, other logical operations may be performed in the logical operations, and the corresponding logical operations may be sequentially selected by increasing the weight. For example, when the write data 0000 is not operated to obtain the data 1111, the ratio of the data 0 is 0% and the ratio of the data 1 is 100%, and the process of the ratio of the data 1 from 0% to 100% is a process in which the weight of the data 1 is increased, and the potential difference of the memory cell in the peripheral preset area is gradually increased in the process in which the weight of the data 1 is increased. When the DDR chip is poor in physical quality, the potential difference is increased in the process to cause potential leakage, which indicates that the memory unit to be tested cannot normally store high potential and overflows to the periphery, so that the potential of the memory unit in the peripheral preset area is changed, and the data of the memory unit in the peripheral preset area is changed accordingly. The data of all the memory cells in the peripheral preset area are 0000, the weight of 1 is increased continuously, the corresponding potential is pulled up gradually, the probability that the data of the memory cells in the peripheral preset area are influenced is higher, and the physical requirement and the detection of the DDR chip are stricter and more accurate in the testing mode. The accurate and efficient test purpose is achieved.
In an embodiment, the determining the test result of the memory cell to be tested according to the first comparison result and the second comparison result includes the following steps:
s401, if the first comparison result and the second comparison result are both pass, judging that the test result of the storage unit to be tested is qualified.
In specific implementation, the first comparison result and the second comparison result are compared, and whether the values of the first comparison result and the second comparison result are the same or not is compared. If the two are the same, the result of the test of the memory cell to be tested is qualified.
S402, if the first comparison result or the second comparison result is not good, the test result of the storage unit to be tested is judged to be unqualified.
In specific implementation, the first comparison result and the second comparison result are compared, and whether the values of the first comparison result and the second comparison result are the same or not is compared. If any result is not the same, the result of the test of the memory cell to be tested is not qualified.
Example 2
Referring to fig. 3, fig. 3 is a schematic flow chart of a DDR chip classification method according to an embodiment of the present invention. The method specifically comprises the following steps:
s501, testing the memory cells of the DDR chip one by one according to the method described in embodiment 1.
In specific implementation, data in the memory unit is written, and data in the memory unit in a preset area around the memory unit to be tested of the DDR chip is recorded. And performing logic operation on the storage unit to be tested, reading the value of the storage unit to be tested after the logic operation, and checking whether the value is the expected value after the logic operation. If the value is the expected value after the logical operation, the logical operation is successful; if the value is not the expected value after the logical operation, the logical operation fails. Indicating that the chip has a Transition Fault (TF). After the logical operation is completed, verifying the data in the storage units in the preset area around the storage unit to be tested, judging whether the data in the storage units in the preset area are consistent or not, and if the data in the storage units in the preset area are consistent, indicating that no coupling fault occurs; if the data in the memory cells in the preset area are inconsistent, a Coupling Fault (CF) is indicated. After all the logic operations are executed, which is equivalent to performing multiple operations on the unit to be detected, the probability that the memory units in the preset area are coupled is greatly increased, and if the DDR chip is weak, the DDR chip is detected. And if the memory cell to be tested and the memory cells in the preset area have no problem, performing the operation on the next memory cell to be tested until all the memory cells are left after traversal.
S502, classifying the DDR chips according to the test results of all the storage units of the DDR chips and a preset classification standard.
In specific implementation, whether the test unit passes or not is determined by performing a series of tests on the DDR chip and determining the test result of the memory unit according to the first comparison result and the second comparison result.
If the first comparison result and the second comparison result both pass, the test unit is qualified;
if any one of the first comparison result and the second comparison result is not passed, the test unit is unqualified; by testing the slave memory units in all DDR chips, if all the memory units pass the test and the result is qualified, the DDR chips are qualified; if any memory unit of all the memory units fails the test, the result is unqualified, the DDR chip is unqualified, and the chip is an abnormal chip.
Referring to fig. 4, fig. 4 is a block diagram illustrating a structure of a DDR chip memory cell test device according to an embodiment of the present invention. As shown in fig. 4, the DDR chip memory cell test device 200 according to the embodiment of the present invention further includes a data writing unit 201, a first data recording unit 202, a logic operation unit 203, a second data recording unit 204, a first comparing unit 205, a second comparing unit 206, a test result determining unit 207, and a classifying unit 208.
And the data writing unit 201 is used for writing data into the memory units in the DDR chip and writing the data into each memory unit of the DDR chip.
The recording first data unit 202 is configured to record first data in a memory cell in a preset area around a memory cell to be tested, and obtain the first data.
The logic operation unit 203 is configured to perform logic operation on the data in the memory unit to be tested, and obtain a logic operation result.
And the recording second data unit 204 is used for recording second data in the storage unit in the preset area around the storage unit to be tested after the logical operation, and obtaining recorded data.
The first comparing unit 205 is configured to compare the logical operation result with a preset expected value, and obtain a first comparison result.
The second comparing unit 206 is configured to compare the first data with the second data to obtain a second comparison result.
And the test result determining unit 207 is configured to determine a test result of the memory unit to be tested according to the first comparison result and the second comparison result, and obtain a final test result.
And the classification unit 208 is configured to classify the DDR chip according to the test results of all the memory units of the DDR chip and a preset classification standard, and obtain a classification result.
In an embodiment, the comparing the logical operation result with a preset expected value to obtain a first comparison result includes:
judging whether the obtained logical operation result is the same as a preset expected value or not;
if the obtained logical operation result is the same as the preset expected value, judging that the first comparison result is a pass;
and if the obtained logical operation result is not the same as the preset expected value, judging that the first comparison result is a fail.
In an embodiment, comparing the first data with the second data to obtain a second comparison result includes:
judging whether the first data is the same as the second data;
if the first data is the same as the second data, judging that the second comparison result is a pass;
and if the first data is not the same as the second data, judging that the second comparison result is a fail.
In an embodiment, determining the test result of the memory cell to be tested according to the first comparison result and the second comparison result includes:
if the first comparison result and the second comparison result are both pass, judging that the test result of the storage unit to be tested is qualified;
and if the first comparison result or the second comparison result is not qualified, judging that the test result of the storage unit to be tested is unqualified.
In one embodiment, the logical operations include a not operation, an or operation, an and operation, and operation; the preset area comprises two storage units positioned on the upper side of the storage unit to be detected, two storage units positioned on the lower side of the storage unit to be detected, two storage units positioned on the left side of the storage unit to be detected and two storage units positioned on the right side of the storage unit to be detected.
Referring to fig. 5, fig. 5 is a block diagram of a DDR chip sorting device according to an embodiment of the present invention. As shown in fig. 5, an embodiment of the invention further provides a DDR chip sorting device 300, where the DDR chip sorting device 300 includes a test unit 301 and a sorting unit 302.
The test unit 301 is configured to test the memory units of the DDR chips one by one according to the method described above;
the classification unit 302 is configured to classify the DDR chip according to the test results of all the memory units of the DDR chip and a preset classification standard.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a testing apparatus according to an embodiment of the present invention. The embodiment of the invention also provides a test device, which comprises a processor 111, a communication interface 112, a memory 113 and a communication bus 114, wherein the processor 111, the communication interface 112 and the memory 113 complete mutual communication through the communication bus 114, and the memory 113 is used for storing computer programs;
and the processor is used for executing the program stored in the memory, and implementing the steps of the method for testing the memory unit of the DDR chip provided by any one of the method embodiments, or the steps of the method for classifying the DDR chip provided by any one of the method embodiments.
The embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the method for testing the storage unit of the DDR chip provided in any of the above method embodiments, or implements the steps of the method for classifying the DDR chip provided in any of the above method embodiments.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for testing a memory unit of a DDR chip is characterized by comprising the following steps:
writing data into each storage unit of the DDR chip;
selecting a storage unit of the DDR chip as a storage unit to be tested, and recording first data in the storage unit in a preset area around the storage unit to be tested;
performing logic operation on the data in the storage unit to be tested to obtain a logic operation result;
recording second data in the storage unit in a preset area around the storage unit to be tested after the logical operation;
comparing the logical operation result with a preset expected value to obtain a first comparison result;
comparing the first data with the second data to obtain a second comparison result;
and determining the test result of the storage unit to be tested according to the first comparison result and the second comparison result.
2. The method of claim 1, wherein comparing the logical operation result with a predetermined expected value to obtain a first comparison result comprises:
judging whether the obtained logical operation result is the same as a preset expected value or not;
if the obtained logical operation result is the same as the preset expected value, judging that the first comparison result is a pass;
and if the obtained logical operation result is not the same as the preset expected value, judging that the first comparison result is a fail.
3. The method of claim 2, wherein comparing the first data with the second data to obtain a second comparison result comprises:
judging whether the first data is the same as the second data;
if the first data is the same as the second data, judging that the second comparison result is a pass;
and if the first data is not the same as the second data, judging that the second comparison result is a fail.
4. The method of claim 3, wherein determining the test result of the memory cell under test according to the first comparison result and the second comparison result comprises:
if the first comparison result and the second comparison result are both pass, judging that the test result of the storage unit to be tested is qualified;
and if the first comparison result or the second comparison result is not qualified, judging that the test result of the storage unit to be tested is unqualified.
5. The method of claim 1, wherein the logical operation comprises a not operation, an or operation, an and operation, a nand operation; the preset area comprises two storage units positioned on the upper side of the storage unit to be detected, two storage units positioned on the lower side of the storage unit to be detected, two storage units positioned on the left side of the storage unit to be detected and two storage units positioned on the right side of the storage unit to be detected.
6. A DDR chip classification method is characterized by comprising the following steps:
testing memory cells of the DDR chip one by one according to the method of any of claims 1 to 5;
and classifying the DDR chips according to the test results of all the storage units of the DDR chips and a preset classification standard.
7. A DDR chip memory cell detection device characterized by comprising a unit for executing the method for testing a memory cell of a DDR chip according to any one of claims 1 to 5.
8. A DDR chip sorting apparatus comprising means for performing the DDR chip sorting method of claim 6.
9. The detection equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor and the communication interface are used for realizing mutual communication by the memory through the communication bus;
a memory for storing a computer program;
a processor, configured to implement a method for testing a memory unit of the DDR chip according to any one of claims 1 to 5 or a method for classifying DDR chips according to claim 6 when executing a program stored in a memory.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements a method for testing a memory cell of a DDR chip according to any one of claims 1 to 5, or a method for classifying DDR chips according to claim 6.
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