CN112397136B

CN112397136B - Parameter testing method and device for semiconductor memory testing software

Info

Publication number: CN112397136B
Application number: CN202110082956.0A
Authority: CN
Inventors: 彭梓莹; 邓标华
Original assignee: Wuhan Jinghong Electronic Technology Co ltd; Wuhan Jingce Electronic Group Co Ltd
Current assignee: Wuhan Jinghong Electronic Technology Co ltd; Wuhan Jingce Electronic Group Co Ltd
Priority date: 2021-01-21
Filing date: 2021-01-21
Publication date: 2021-05-14
Anticipated expiration: 2041-01-21
Also published as: CN112397136A

Abstract

The application relates to a parameter testing method and a parameter testing device for semiconductor memory testing software, which relate to the technical field of semiconductor memory testing, and the method comprises the following steps: setting various test parameter combinations according to the parameter information of the semiconductor memory; setting a plurality of groups of preset error number combinations according to the parameter information of the semiconductor memory; and respectively configuring the semiconductor memories according to the preset error number combinations, testing the configured semiconductor memories by using the test parameter combinations, and comparing the corresponding test results with the corresponding preset error number combinations to verify whether the test parameter combinations are reasonable. According to the method and the device, the test parameters are reasonably set and combined, the bad block condition of the semiconductor memory is simulated, different test parameter combinations are verified in an efficient verification mode, so that the test parameters with higher accuracy are obtained and serve as test bases, and the test reliability is fully guaranteed.

Description

Parameter testing method and device for semiconductor memory testing software

Technical Field

The application relates to the technical field of semiconductor memory testing, in particular to a parameter testing method and device of semiconductor memory testing software.

Background

In the testing process of the NAND flash memory chip, the generation of bad blocks is an important index for measuring the quality of the NAND flash memory chip. At present, a software test mode is mostly adopted to detect whether a bad block exists in the NAND flash memory, and the method belongs to the current common method. Although there are many software parameters for judging whether to generate a bad block, how to obtain accurate software parameters is a key factor influencing the result accuracy at present, because the result that the NAND flash memory generates the bad block in the testing process can be guaranteed to be credible only on the premise that the function of the software parameters for judging the bad block is normal.

In order to improve the reliability of the test result of the NAND flash memory, a test technology for judging the software parameters of the bad block of the NAND flash memory is provided so as to meet the current test requirement.

Disclosure of Invention

The application provides a parameter testing method and device of semiconductor memory testing software, which reasonably sets and combines testing parameters, simulates the bad block condition of a semiconductor memory, verifies different testing parameter combinations by using an efficient verification mode, and obtains testing parameters with higher accuracy as testing bases, thereby fully ensuring the reasonability, normalization, correctness and reliability of testing.

In a first aspect, the present application provides a method for testing parameters of semiconductor memory test software, the method comprising the steps of:

setting various test parameter combinations according to the parameter information of the semiconductor memory;

setting a plurality of groups of preset error number combinations according to the parameter information of the semiconductor memory;

respectively configuring the semiconductor memories according to the preset error quantity combinations, testing the configured semiconductor memories by using the test parameter combinations, and comparing the corresponding test results with the corresponding preset error quantity combinations to verify whether the test parameter combinations are reasonable or not; wherein the content of the first and second substances,

the multiple test parameter combinations are obtained through combinations of Chunk size parameters, at least 2 stored FBC judgment parameters, at least 2 FBC error limiting parameters, at least 2 Chunk error limiting parameters and at least 2 Page error limiting parameters, the preset error number combinations all comprise the number of Page errors, the number of Chunk errors and the number of Byte errors, one Byte error corresponds to 4 bit errors, and FBC is the number of erroneous bits in one Chunk.

Specifically, the setting of various test parameter combinations according to the parameter information of the semiconductor memory includes the following steps:

acquiring the Page Size of the semiconductor memory, and setting the number of chunks of one Page in the semiconductor memory during testing according to the Chunk Size parameter;

setting at least 2 types of Chunk error limiting parameters and at least 2 types of Page error limiting parameters according to the Chunk number of one Page in the semiconductor memory;

and setting a plurality of stored FBC judgment parameters and a plurality of FBC error limiting parameters according to the Chunk size parameter.

Specifically, the at least 2 types of Chunk error limiting parameters and the at least 2 types of Page error limiting parameters both include 0 and 1.

Further, the method comprises the following steps:

comparing the FBC value of each Chunk in the Block with the stored FBC judgment parameter, and storing the corresponding FBC file of the Block when the FBC value of any Chunk in the Block is greater than the stored FBC judgment parameter.

Specifically, the step of testing the semiconductor memory configured by the test parameter combinations includes:

judging whether the FBC value of each Chunk of the semiconductor memory is larger than an FBC error limiting parameter so as to judge whether each Chunk is failed;

judging whether the total number of the failed chunks is greater than the Chunk error limiting parameter so as to judge whether the corresponding pages are failed,

and judging whether the total number of the failed pages is greater than a Page error limiting parameter or not, thereby judging whether the semiconductor memory has bad blocks or not.

In a second aspect, the present application provides a parametric test apparatus for semiconductor memory test software, the apparatus comprising:

the test parameter setting module is used for setting various test parameter combinations according to the parameter information of the semiconductor memory;

the error simulation module is used for setting a plurality of groups of preset error number combinations according to the parameter information of the semiconductor memory;

the simulation test module is used for respectively configuring the semiconductor memories according to the preset error quantity combinations, testing the configured semiconductor memories by using the test parameter combinations, comparing the corresponding test results with the corresponding preset error quantity combinations and verifying whether the test parameter combinations are reasonable or not; wherein the content of the first and second substances,

Further, the test parameter setting module is further configured to obtain a Page Size of the semiconductor memory, and set a Chunk number of one Page in the semiconductor memory during testing according to the Chunk Size parameter;

the test parameter setting module is further used for setting at least 2 types of Chunk error limiting parameters and at least 2 types of Page error limiting parameters according to the Chunk number of one Page in the semiconductor memory;

the test parameter setting module is further configured to set a plurality of stored FBC determination parameters and a plurality of FBC error limiting parameters according to the Chunk size parameter.

Furthermore, the simulation testing module is further configured to compare FBC values of chunks in a Block with the stored FBC judgment parameters, and store a corresponding FBC file of the Block when an FBC value of any Chunk in the Block is greater than the stored FBC judgment parameters.

Further, the simulation test module is further configured to determine whether an FBC value of each Chunk of the semiconductor memory is greater than an FBC error limit parameter, so as to determine whether each Chunk fails;

the simulation test module is further configured to determine whether the total number of failed chunks is greater than the Chunk error limiting parameter, so as to determine whether each corresponding Page fails,

the simulation test module is further used for judging whether the total number of the failed pages is larger than a Page error limiting parameter or not, so that whether a bad block exists in the semiconductor memory or not is judged.

The beneficial effect that technical scheme that this application provided brought includes:

the test parameters are reasonably set and combined, the bad block condition of the semiconductor memory is simulated, different test parameter combinations are verified in an efficient verification mode, the test parameters with high accuracy are obtained and serve as test bases, and therefore the reasonability, the normalization, the correctness and the reliability of the test are fully guaranteed.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a flowchart illustrating steps of a method for testing parameters of semiconductor memory test software according to an embodiment of the present application;

FIG. 2 is a block diagram of a NAND flash memory chip according to a method for testing parameters of semiconductor memory test software provided in an embodiment of the present application;

FIG. 3 is a flowchart of a NAND flash memory chip determining bad blocks according to a parameter testing method of semiconductor memory testing software provided in an embodiment of the present application;

FIG. 4 is a diagram showing an example of a part of parameter combinations of a NAND flash memory chip in a parameter testing method of semiconductor memory testing software provided in an embodiment of the present application;

fig. 5 is an example of a modified Random Bin rule of a NAND flash memory chip designed for a part of parameter combinations given in the parameter testing method of the semiconductor memory testing software provided in the embodiment of the present application;

FIG. 6 is a schematic flow chart illustrating a 756 Cycle test flow in the parameter testing method of semiconductor memory testing software provided in the embodiment of the present application;

fig. 7 is an example of an output of a part of result analysis in the parameter test method of the semiconductor memory test software provided in the embodiment of the present application;

FIG. 8 is a block diagram of a parameter testing apparatus of semiconductor memory testing software provided in an embodiment of the present application;

fig. 9 is a block diagram showing an example of the configuration of a parameter testing apparatus of semiconductor memory testing software provided in the embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The embodiment of the application provides a parameter testing method and device for semiconductor memory testing software, which reasonably set and combine testing parameters, simulate the bad block condition of a semiconductor memory, verify different testing parameter combinations by using an efficient verification mode, and obtain testing parameters with higher accuracy as testing bases, so that the reasonability, the normalization, the correctness and the reliability of testing are fully guaranteed.

In order to achieve the technical effects, the general idea of the application is as follows:

a method for testing parameters of semiconductor memory test software, the method comprising the steps of:

s1, setting various test parameter combinations according to the parameter information of the semiconductor memory;

s2, setting a plurality of groups of preset error number combinations according to the parameter information of the semiconductor memory;

s3, respectively configuring the semiconductor memories according to the preset error number combinations, testing the configured semiconductor memories by using the test parameter combinations, and comparing the corresponding test results with the corresponding preset error number combinations to verify whether the test parameter combinations are reasonable; wherein the content of the first and second substances,

the multiple test parameter combinations are obtained through combinations of Chunk size parameters, at least 2 stored FBC judgment parameters, at least 2 FBC error limiting parameters, at least 2 Chunk error limiting parameters and at least 2 Page error limiting parameters, and the preset error number combinations all comprise the number of Page errors, the number of Chunk errors and the number of Byte errors.

In a first aspect, referring to fig. 1 to 7, an embodiment of the present application provides a parameter testing method for semiconductor memory testing software, including the following steps:

In addition, various parameters related to the embodiments of the present application are explained:

FBC: the number of wrong bits in a Chunk can be obtained through actual test;

chunk Size: the Chunk size parameter is used for calibrating the Byte number in one Chunk, the value can be provided for various conditions by a customer according to the characteristics of the NAND flash memory chip, and the setting is carried out by a process sequence;

data clear Limit: the method comprises the steps that FBC judgment parameters are saved and used for judging whether the FBC of a corresponding Block is saved or not, during actual testing, due to the fact that the memory occupied by generated FBC files is large, the FBC files of the Block are reserved only when 1 or more than 1 FBC value in the Block is larger than the parameters, and if the FBC values of the Block are smaller than Data clear Limit, the FBC files of the Block cannot be saved, so that the memory space is released;

FBC Limit: the FBC error limiting parameter is used for calibrating the maximum bit number of allowed errors in a Chunk to serve as a judgment basis for judging whether the Chunk fails, the value can be provided for various conditions by a client according to the characteristics of the NAND flash memory chip, the setting is carried out through a process sequence, and if the FBC value read in the actual test is greater than the FBC Limit, the Chunk fails, namely, the Chunk Fail is considered;

chunk Limit: the method comprises the steps that a Chunk error limiting parameter is used for calibrating the maximum Chunk number of allowed errors in a Page and used as a basis for judging whether the Page fails, a client can provide multiple conditions according to the characteristics of an NAND flash memory chip, the values are set according to a process sequence, and if the Chunk number of the Fail is larger than Chunk Limit in actual test, the Page is considered to be failed, namely the Page Fail;

page Limit: the Page error limiting parameter is used for the maximum number of pages with allowed errors in the Block and used as a basis for judging whether the Block fails, the value can be set by a client according to characteristics of a NAND flash memory chip, and the Block is considered to Fail if the number of pages of Fail is greater than Page Limit during actual test.

Therefore, when determining whether Block is failed, that is, whether Block is Bad Block (Bad Block), first determining whether FBC values of all Chunk are greater than FBC Limit to determine whether Chunk is Fail, then determining whether total Chunk number of Fail is greater than Chunk Limit to determine whether Page is Fail, and finally determining whether total Page number of Fail is greater than Page Limit to determine whether Page is Bad Block, if each is greater, the program determines that Block is Bad Block.

Furthermore, the at least 2 Chunk error limit parameters and the at least 2 Page error limit parameters include both 0 and 1.

In the embodiment of the application, the test parameters are reasonably set and combined, the bad block condition of the semiconductor memory is simulated, and different test parameter combinations are verified in an efficient verification mode so as to obtain the test parameters with higher accuracy as the test basis, thereby fully ensuring the reasonability, normalization, correctness and reliability of the test.

It should be noted that, in the embodiment of the present application, the parameter test method can be specifically applied to parameter test work of test software of a NAND flash memory chip.

Here, a brief description is made of the structure of the memory chip: a semiconductor memory Chip is a Chip tester unit DUT (device Under test), a DUT includes a plurality of Chip Enable (CEs), a CE includes a plurality of LUNs (logical unit numbers, minimum logical units that can be independently commanded to test), a LUN includes a plurality of blocks (blocks), a Block includes a plurality of pages (pages), a Page has a plurality of bytes, and a Page can be sliced into a plurality of data blocks (Chunk).

Specifically, the step S1 of setting a plurality of test parameter combinations according to the parameter information of the semiconductor memory includes the steps of:

s100, acquiring a Page Size of the semiconductor memory, and setting the number of chunks of one Page in the semiconductor memory during testing according to Chunk Size parameters;

s101, setting at least 2 Chunk error limiting parameters and at least 2 Page error limiting parameters according to the Chunk number of one Page in the semiconductor memory;

s102, setting a plurality of stored FBC judgment parameters and a plurality of FBC error limiting parameters according to the Chunk size parameter.

Further, in the embodiment of the present application, the method further includes the following steps:

and comparing the FBC value in each Block with the stored FBC judgment parameter, and storing the corresponding FBC file of the Block when the FBC value in the Block is greater than the stored FBC judgment parameter.

Specifically, the step S3 of testing the semiconductor memory after the configuration by using the combination of the test parameters includes the steps of:

judging whether the FBC value of each Chunk of the semiconductor memory is larger than the FBC error limiting parameter, thereby judging whether each Chunk is invalid;

judging whether the total number of failed chunks is greater than a Chunk error limiting parameter so as to judge whether the corresponding pages fail,

and judging whether the total number of the failed pages is greater than the Page error limiting parameter or not, thereby judging whether the semiconductor memory has bad blocks or not.

According to the technical scheme of the embodiment of the application, a certain NAND flash memory chip is taken as an example, one Page of the NAND flash memory chip has 18432 (18K) Byte, namely Page Size is 18432;

based on 4 types of Chunk Size: 1152Byte, 2304Byte, 4608Byte and 9216Byte, respectively designing different Chunk Limit and Page Limit, and corresponding to step S101, the specific instances of Chunk error limiting parameters and Page error limiting parameters are as follows:

when the Chunk Size is 1152 bytes, since the Page Size is 18432, 16 chunks are contained in one Page, and 3 Chunk Limit can be reasonably designed according to the situation: 0. 1, 5, each Chunk Limit can be combined with 3

Page Limit

0, 1, 5 respectively;

when Chunk Size is 2304 bytes, since Page Size is 18432, 8 chunks are shared by one Page, and 3 Chunk Limit can be reasonably designed for this case: 0. 1, 5, each Chunk Limit can be combined with 3

Page Limit

0, 1, 5 respectively;

when the Chunk Size is 4608 bytes, since the Page Size is 18432, 4 chunks are shared by one Page, and 3 Chunk Limit values can be reasonably designed according to the situation: 0. 1, 2, each Chunk Limit can be combined with 3

Page Limit

0, 1, 3 respectively.

When Chunk Size is 9216 bytes, one Page has 2 chunks, and 2 Chunk Limit can be reasonably designed: 0. 1, each Chunk Limit can be combined with 2

Page Limit

0, 1, respectively.

It should be noted that the Chunk error Limit parameter and the Page error Limit parameter, i.e. the values of Chunk Limit and Page Limit, are not randomly set, and a certain design method is required;

0 is set as a default, i.e. 1 Fail is not allowed, while 1 is also typically set, 1 Fail is allowed, 0 and 1 being two critical conditions, and then one or more slightly larger error limit values, i.e.

parameter values

2 or 3 or 5 as described above, can be set depending on the actual situation.

Further, in response to the above design examples of the Chunk error limiting parameter and the Page error limiting parameter, the following specific cases will be described in which, in step S102, after Chunk Limit and Page Limit are designed based on Chunk Size, the design examples of FBC Limit and Data Clean Limit are designed:

when the Chunk Size is 1152 bytes, after combining with the Chunk Limit and Page Limit, reasonably designing FBC Limit and Data clear Limit according to the chip characteristics, and designing 3 FBC Limit for the NAND flash memory chip: 10. 72, 150, 3 Data Clean Limit: 10. 72, 150, finally, combining each FBC Limit, Data Clean Limit and the combined Chunk Size, Chunk Limit and Page Limit again, so as to complete all parameter combinations when the Chunk Size is 1152;

when the Chunk Size is 2304 bytes, after combining with the Chunk Limit and Page Limit, the FBC Limit and Data clear Limit are reasonably designed according to the chip characteristics, and 5 FBC limits can be designed for the NAND flash memory chip: 10. 20, 72, 120, 150, 3 kinds of Data Clean Limit: 20. 120, 240, finally, combining each FBC Limit, Data Clean Limit and the combined Chunk Size, Chunk Limit and Page Limit again, so as to complete all parameter combinations when the Chunk Size is 2304;

when the Chunk Size is 4608 bytes, after combining with the Chunk Limit and Page Limit, reasonably designing the FBC Limit and Data clear Limit according to the characteristics of the chip, and designing 3 FBC limits for the NAND flash memory chip: 40. 248, 400, 3 Data clear Limit: 40. 248, 400, and finally, combining each FBC Limit, Data Clean Limit and the combined Chunk Size, Chunk Limit and Page Limit again, so as to complete all parameter combinations when the Chunk Size is 4608;

when the Chunk Size is 9216 bytes, after combining with the Chunk Limit and Page Limit, reasonably designing the FBC Limit and Data clear Limit according to the chip characteristics, and designing 3 FBC limits for the NAND flash memory chip: 80. 255, 500, 3 Data clear Limit: 80. 255 and 500, finally, combining each FBC Limit and Data Clean Limit with the combined Chunk Size, Chunk Limit and Page Limit again, so as to complete all parameter combinations when the Chunk Size is 9216;

the FBC and Data clear Limit are generally set reasonably according to chip characteristics (for example, bit flip when the chip itself reads) and the Size of Chunk Size

The number and values of the above test parameter settings are merely examples, and are not standard, and may be adjusted appropriately according to the characteristics of the chip.

In step S2, setting of multiple sets of predetermined error number combinations is described, that is, for a certain corresponding NAND flash memory chip, an example of changing Random Bin rules, that is, predetermined error number combinations (Chunk Size is 1152) of a part of parameter combination designs is as follows:

when 4 types of Chunk Size (1152, 2304, 4608 and 9216) are combined with the aforementioned Chunk Limit, Page Limit, FBC Limit and Data clear Limit, each combination is further matched with a plurality of Random bins (Random bins are used as hexadecimal numbers for writing into the NAND flash memory) which are modified by artificial manufacturing;

the number of erroneous bits (byte error, 4 bits per default per 1 byte) of an artificially produced Random Bin may be greater than or less than or equal to FBC Limit, respectively, the number of erroneous bits (Chunk error) of an artificially produced Random Bin may be greater than or less than or equal to Chunk Limit, respectively, and the number of erroneous pages (Page error) of an artificially produced Random Bin may be greater than or less than or equal to Page Limit, respectively;

that is, when designing a wrong Random Bin for manufacturing, it is recommended to cover the cases of being greater than, less than or equal to various limits, so that various parameters can be tested more comprehensively. In the present example, based on the above various combinations, 756 Random bins can be designed in total, that is, 756 combinations can be designed, and each combination needs to be tested by one Cycle, that is, 756 cycles (cycles 0-755) are tested in total.

The above description is provided only for one design idea, and is not standard, and the specific design may be adjusted appropriately according to actual conditions. If the Chunk Limit is 0, it is not possible to design a Chunk error smaller than 0. In addition, bit inversion possibly existing in the chip itself during reading needs to be considered, the difference value between the bit number of the Random Bin and the set FBC Limit which is manufactured is controlled to be out of the inversion possibly existing in the chip itself during reading, and the phenomenon that the actual result is inconsistent with the expected result and the corresponding parameter combination setting is mistakenly considered to be invalid is avoided. If the designed FBC Limit is small, if the number of bits of a changed Random Bin error is smaller than the FBC Limit, an expected result is that no bad block is generated, but an actually read FBC value is larger than the FBC Limit due to the fact that the chip turns over n bits when reading, if the Chunk Fail number and the Page Fail number are larger than the corresponding Limit, a program can judge that the block is bad, when analyzing a test result, the condition considers that the actual result is inconsistent with the expected result, so that the parameter combination test Fail needs to be checked, or the Random Bin and each parameter are unreasonable in design. Meanwhile, the chip with higher quality and more stable reading is selected for verification during testing, so that the test failure caused by the error of the chip is avoided.

It should be noted that, according to the above setting situation, as shown in fig. 6 of the accompanying drawings of the specification, a 756 Cycle test flow is provided, and specific description is as follows:

after entering the cycles, erasing the Block tested by each Cycle, reading, comparing with FF, writing in manufactured Random Bin, reading, comparing with original Random Bin, and recording the Block of Fail in each erasing, reading, writing and reading process. After 756 cycles are completed, the test flow is exited, and the Cycle test is finished;

wherein, FF is hexadecimal number, the data after the chip is erased are all 1 theoretically, and the comparison with FF is the comparison with all 1 so as to confirm whether the erasing is successful;

the original Random Bin is a Random Bin which has not been artificially modified, and the number of bits of the manufacturing error and the like are modified based on the original Random Bin, that is, 0 is changed to 1 or 1 is changed to 0 in the corresponding bit.

It should be noted that fig. 7 of the drawings in the specification is an output example of a part of result analysis, and the specific description is as follows:

the result can be automatically analyzed through the developed result analysis script tool;

the number of cycles of the A-th column printing operation is respectively from Cycle0 to Cycle755, the B, C, D, E, F-th column is respectively printed with the values of Page Limit, Chunk Size, FBC Limit and Data Clean Limit of each group, the G-th column is printed with the result of manufacturing Random Bin, the H-th column is printed with the expected BBM result, the I-th column is compared with the actual BBM result to print the comparison result, the J-th column is printed with the expected retention FBC result, and the K-th column is compared with the actual FBC file to print the comparison result;

if the first row P285C7(40) represents an error of 40 bits made in Page285 Chunk7, the Chunk number of Fail is 1 because 40> FBC Limit (36), i.e., Fail Chunk Num = 1, the Page number of Fail is 1 because Fail Chunk Num > Chunk Limit (0), i.e., Fail Page Num = 1, and the BBM Result is expected to be YES (bad blocks should be generated) because Fail Page Num > Page Limit (0), and the BBM Result is Page when actually tested; since 40> Data clear Limit (36), the FBC Result is expected to be retained as YES (FBC file should be retained), and the FBC file is also retained at the time of actual testing, so FBC Result is Pass.

In addition, in fig. 7 of the drawings of the specification, "extract Error" represents an erroneous Random Bin case expected to be manufactured by humans, "extract BBM" represents an expected BBM Result, "extract FBC" represents an expected FBC Result, "BBM Result" represents an actual BBM Result, and "FBC Result" represents an actual FBC Result;

for example, P285C7(40) represents an error of 40 bits made in Page285 Chunk7, P518C0(40) represents an error of 40 bits made in Page518 Chunk0, i.e., P represents Page, the following numbers of which represent Page No., C represents Chunk, the following numbers of which represent Chunk No., and (40) represents an error of 40 bits, so that the error Random Bin represented by the following contents is analogous.

The artificially manufactured Random Bin, namely the preset error number combination, is designed and generated, and compared with the original Random Bin, the method can know which bits have errors, so that an expected result can be known, and the actual test is the result tested by setting a corresponding parameter combination and then according to a software program;

the expected BBM result is a result of whether a bad block is expected to be generated or not according to a judgment standard of the bad block after Random bins are manufactured artificially, namely a preset error number combination is set, the actual BBM result is a result of whether the bad block is generated or not in an actual test obtained by a software program according to parameter combination, and the FBC result is the same;

i.e., whether a BBM is expected to be generated/actually generated, and whether an FBC file is expected to be retained/actually retained.

In fig. 5 of the drawings, a Page error is the number of pages that are errors in artificial manufacturing, that is, the number of pages that are errors in artificial manufacturing of Random Bin, a Chunk error is the number of chunks that are errors in artificial manufacturing, that is, the number of chunks that are errors in artificial manufacturing of Random Bin, and a byte error is the number of bytes that are errors in artificial manufacturing, that is, the number of bytes that are errors in artificial manufacturing of Random Bin.

The embodiment of the application belongs to the field of semiconductor memory testing, and the method comprises the steps of firstly, carrying out various combinations on values of different software parameters including Data clear Limit, FBC Limit, Chunk Limit, Page Limit and Chunk Size, and carrying out change of different numbers of bits on hexadecimal Random numbers (Random bins) written into a flash memory according to a certain rule by a script tool for manufacturing the Random bins corresponding to each combination;

then each combination is tested, firstly, the changed random number is written, and then the written data is read and compared with the random number before the change to obtain different bit numbers, namely FBC values;

then judging whether a bad block is generated as an actual test result by combining the software program with the software parameter combination;

finally, the actual result is compared with the expected result (whether a bad block should be generated) through a result analysis script tool to determine whether the actual result is matched with the expected result, and if the actual result is not matched with the expected result, the software parameter combination is not effective;

the technical scheme can confirm whether the software parameter function of the bad block is normal or not, so that the result that the NAND flash memory chip generates the bad block in the test process is credible.

In a second aspect, referring to fig. 8 to 9, an embodiment of the present application provides a parameter testing apparatus for semiconductor memory testing software, which is used to execute the parameter testing method for the semiconductor memory testing software mentioned in the first aspect, and the apparatus includes:

the simulation test module is used for respectively configuring the semiconductor memories according to the preset error number combinations, testing the configured semiconductor memories by using the test parameter combinations, comparing the corresponding test results with the corresponding preset error number combinations and verifying whether the test parameter combinations are reasonable or not; wherein the content of the first and second substances,

Furthermore, the test parameter setting module is also used for acquiring the Page Size of the semiconductor memory, and setting the number of chunks of one Page in the semiconductor memory during testing according to the Chunk Size parameter;

the test parameter setting module is also used for setting at least 2 types of Chunk error limiting parameters and at least 2 types of Page error limiting parameters according to the Chunk number of one Page in the semiconductor memory;

the test parameter setting module is also used for setting various stored FBC judgment parameters and various FBC error limiting parameters according to the Chunk size parameter.

It should be noted that, in the at least 2 types of Chunk error limiting parameters and the at least 2 types of Page error limiting parameters, both 0 and 1 are included.

And the simulation test module is further used for comparing the FBC value in each Block with the stored FBC judgment parameter, and storing the corresponding FBC file of the Block when the FBC value in the Block is greater than the stored FBC judgment parameter.

Furthermore, the simulation test module is also used for judging whether the FBC value of each Chunk of the semiconductor memory is greater than the FBC error limit parameter, so as to judge whether each Chunk is invalid;

the simulation test module is also used for judging whether the total number of failed chunks is greater than a Chunk error limiting parameter so as to judge whether each corresponding Page is failed,

the simulation test module is also used for judging whether the total number of the failed pages is greater than the Page error limiting parameter, so as to judge whether the semiconductor memory has a bad block.

In specific implementation, the test parameter setting module comprises a design Config module, the error simulation module comprises a design Random Bin module, the simulation test module comprises an acquisition Config module, a manufacture Random Bin module, a Cycle test module and a result analysis module, and the functions of the modules are described as follows:

designing a Config module: reasonably designing and combining values of Chunk Size, Chunk Limit, Page Limit, FBC Limit and Data clear Limit according to the characteristics of the NAND flash memory chip, recording the values as a 'Config' file, storing the file in a specific position, and designing a Config module to design all combinations of software parameters for judging NAND flash memory bad blocks;

a method for reasonably designing various parameters is provided by designing a Config module, and generally, at least 0 and 1 are set for Chunk Limit and Page Limit, so that whether the function of the parameter plays a role can be quickly judged, and then a plurality of larger limits are reasonably set according to the actual Chunk number and Page number, so that whether the function of the parameter plays a role can be judged. The less the number of Limit numbers of the set various parameters is, the less the number of cycles tested is, the shorter the testing time is, the more the number of Limit numbers of the set various parameters is, the more the number of cycles tested is, the longer the testing time is, but the more comprehensive the test is, and the more accurate the result is. The actual test can be designed according to specific conditions.

Designing a Random Bin module: based on each parameter combination, on the basis of an original Random Bin, the conditions of being more than or less than or equal to various limits are respectively designed, so that one parameter combination can correspond to various combinations of Page error, Chunk error and byte error, namely a plurality of changed Random Bins, 756 Random Bins can be designed in a total manner by designing a Random Bin module, and each combination needs to be tested by one Cycle;

by designing the Random Bin module, a method for reasonably designing and changing the Random Bin is provided, and the conditions of being more than, less than or equal to various limits are covered usually, so that various parameters can be tested more comprehensively. Meanwhile, bit inversion possibly existing when the chip is read needs to be considered, and the difference value between the bit number of the changed Random Bin and the set FBC Limit is recommended to be larger than the inversion possibly existing when the chip is read as much as possible, so that the phenomenon that the actual result is inconsistent with the expected result due to the fact that the chip is inverted is avoided, and the misjudgment is made that the corresponding parameter combination is set to be invalid.

Acquiring a Config module: when the first Cycle test is the Cycle0 test, the first row of the 'Config' file in the design Config module, namely the value of the first parameter combination, is read, and the corresponding value of each parameter is set in the software program to perform the first complete test, when the second Cycle test is the Cycle1 test, the second row of the 'Config' file in the design Config module, namely the value of the second parameter combination, is read, and the corresponding value of each parameter is set in the software program to perform the second complete test, and so on, before each complete test is performed, the value of the parameter combination in the corresponding row is read and set by the obtaining Config module, and then the Cycle test is performed until the tests of all the parameter combinations are completed, namely the tests of 756 cycles are completed.

Manufacturing a Random Bin module: reading the Page error, Chunk error and byte error of each combination through a script tool for manufacturing the Random Bin according to the design of the Random Bin module, randomly selecting one or a plurality of Page numbers, Chunk numbers and bit bits to change data to generate the Random Bin corresponding to each combination of the Page error, Chunk error and byte error, and manufacturing 756 Random Bins through the Random Bin module to respectively correspond to the data written in each Cycle test;

by fabricating a Random Bin module, a method of fabricating a Random Bin is provided and randomness is increased. Through a developed script tool for manufacturing Random bins, according to the designed Page error, one or some Page number manufactured error pages can be randomly selected, such as 2 for Page error, 2 for Page0, 6 or other 2 pages; according to the designed Chunk error, one or some Chunk numbers can be randomly selected again from the randomly selected Page numbers to manufacture the error Chunk, for example, the Chunk error is 1, Chunk2 can be randomly selected again from the randomly selected Page0 to manufacture the error Chunk or some other Chunk, and Chunk5 can be randomly selected again from the Page6 to manufacture the error Chunk or some other Chunk; depending on the design of the byte error, one or some of the previously randomly selected Page numbers and Chunk numbers may be re-randomly selected to make an error byte.

Cycle test module: the method comprises the steps that data are written into corresponding Random bins which are manufactured for each combination through a Cycle testing module, data are read out and compared with original Random bins which are not manually changed, FBC values of all pages of a Block tested by each combination are obtained, whether a bad Block is generated or not is judged through a software program, and whether the FBC values are stored as files or not is judged, so that an actual testing result is obtained;

a method for testing bad block software parameters is provided through a Cycle testing module. The manufactured Random Bin is used for writing data, and then the data is read out and compared with the original Random Bin to obtain an FBC value, and then a software program is used for obtaining whether an actual test result generates a bad block or not and whether an FBC file is reserved or not.

A result analysis module: through a result analysis script tool, reading all designed combinations to obtain an expected result of each combination, reading an actual test result of each combination, comparing the actual result of each combination with the expected result, printing Pass if the actual result of each combination is matched with the expected result, printing Fail if the actual result of each combination is not matched with the expected result of each combination, and automatically analyzing whether the test result of each combination is Pass or not through a result analysis module so as to find out a failed parameter combination;

through the result analysis module, a method for printing related information is provided. By result analysis tool script: 1) the combination of various parameters and the Cycle number are corresponded and printed, and the condition of each Cycle test is conveniently checked. 2) The method can print the specifically changed Page number, Chunk number and bit number when Random bins are randomly manufactured, artificially compare the manufactured Random bins with the original Random bins, confirm the changed Page number, Chunk number and bit number, compare the changed Page number, Chunk number and bit number with the printed numbers to confirm whether the changed Page number, Chunk number and bit number are matched, conveniently check whether the manufactured Random bins are accurate, and fully guarantee the correctness of the tool script. 3) The expected results (whether bad blocks should be generated or not and whether the FBC file should be kept) are printed, and people are not required to confirm the expected results of 756 combinations, so that the analysis time is greatly saved. 4) And printing the final analysis result, wherein the Pass test is 'Pass', the failure test is 'Fail', and the method is visual and clear and is convenient for screening out the parameter combination of Fail.

It is noted that, in the present application, relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present application and are presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing parameters of semiconductor memory test software, the method comprising the steps of:

2. The method for testing parameters of semiconductor memory test software according to claim 1, wherein said setting a plurality of test parameter combinations according to the parameter information of the semiconductor memory comprises the steps of:

3. The parameter testing method of semiconductor memory testing software according to claim 1, characterized in that:

the at least 2 Chunk error limiting parameters and the at least 2 Page error limiting parameters include both 0 and 1.

4. The parametric test method for semiconductor memory test software according to claim 1, wherein the method further comprises the steps of:

5. The method according to claim 2, wherein said testing the configured semiconductor memory device with each of said test parameter combinations comprises the steps of:

6. A parametric test apparatus for semiconductor memory test software, the apparatus comprising:

7. The parameter test apparatus of semiconductor memory test software according to claim 6, characterized in that:

the test parameter setting module is further used for acquiring the Page Size of the semiconductor memory, and setting the number of chunks of one Page in the semiconductor memory during testing according to the Chunk Size parameter;

8. The parameter test apparatus of semiconductor memory test software according to claim 6, characterized in that:

9. The parameter test apparatus of semiconductor memory test software according to claim 6, characterized in that:

the simulation testing module is further used for comparing the FBC value of each Chunk in the Block with the stored FBC judgment parameter, and when the FBC value of any Chunk in the Block is greater than the stored FBC judgment parameter, storing the corresponding FBC file of the Block.

10. The parameter test apparatus of semiconductor memory test software according to claim 6, characterized in that:

the simulation test module is further used for judging whether the FBC value of each Chunk of the semiconductor memory is larger than the FBC error limiting parameter, so as to judge whether each Chunk fails;