WO2023035413A1

WO2023035413A1 - Read and write test method and apparatus, computer storage medium, and electronic device

Info

Publication number: WO2023035413A1
Application number: PCT/CN2021/131873
Authority: WO
Inventors: 黄国维
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-09-08
Filing date: 2021-11-19
Publication date: 2023-03-16
Also published as: CN115774635A

Abstract

Embodiments of the present application provide a read and write test method and apparatus, a computer storage medium, and an electronic device. The method comprises: receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction; when the data instruction indicates a read operation, performing a read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; obtaining a target write value of the target storage object in the memory module in the latest write operation; and comparing the target read value with the target write value, and determining a test result of the target storage object in the memory module according to the comparison result.

Description

A reading and writing test method and device, computer storage medium and electronic equipment

Cross References to Related Applications

This application is based on the Chinese patent application with the application number 202111050167.5, the filing date is September 08, 2021, and the invention title is "A read-write test method and device, computer storage medium and electronic equipment", and requires the Chinese patent application The priority of this Chinese patent application, the entire content of this Chinese patent application is hereby incorporated into this application as a reference.

technical field

The present disclosure relates to the technical field of memory testing, in particular to a method and device for reading and writing testing, a computer storage medium and electronic equipment.

Background technique

In servers, personal computers and various consumer electronics products, dynamic random access memory (Dynamic Random Access Memory, DRAM) is generally used as a memory component to provide temporary data storage. According to the data storage principle of the DRAM, the DRAM needs to be refreshed continuously during use, so as to keep the data stable.

At present, DRAM is generally tested for reading and writing through test applications (such as Stress APP tools) to ensure the stability and reliability of the memory. Since the Stress APP tool needs to use the logical storage address for read and write tests, if one or more data errors occur, the Stress APP tool needs to analyze to determine the physical storage address where the error occurred. In other words, for different system platforms, the Stress APP tool needs to redesign the address mapping relationship and corresponding test parameters, and the development cycle is very long; in addition, the Stress APP tool may have compatibility problems, which leads to the flexibility of the Stress APP tool. Poor performance and versatility.

Contents of the invention

The disclosure provides a read-write test method and device, computer storage medium and electronic equipment, which can directly use physical storage addresses to perform read-write test on memory modules, and improve the flexibility and compatibility of read-write test.

The disclosed technical solution is achieved in this way:

In the first aspect, an embodiment of the present disclosure provides a read-write test method, which is applied to a read-write test device, and the method includes:

Receive the data instruction sent by the memory controller, and determine the physical storage address corresponding to the data instruction;

When the data instruction indicates a read operation, the target storage object in the memory module is read, and the target read value sent by the memory module is received; wherein, the target storage object in the memory module is determined according to the physical storage address;

Obtain the target write value of the target storage object in the memory module in the latest write operation;

The target read value is compared with the target write value, and the test result of the target storage object in the memory module is determined according to the comparison result.

In some embodiments, the method further includes: when the data instruction indicates a write operation, determining the target write value according to the data instruction; performing a write operation on the target storage object in the memory module, so as to write the target write value into the memory module The target storage object in .

In some embodiments, the device for reading and writing testing includes a first storage unit and a second storage unit; the method further includes: after determining the target write value, correspondingly storing the physical storage address and the target write value in the first storage unit Middle; after determining the target read value, correspondingly storing the physical storage address and the target read value in the second storage unit.

In some embodiments, the comparing the target read value with the target write value, and determining the test result of the target storage object in the memory module according to the comparison result includes:

From the first storage unit, obtain the target write value corresponding to the physical storage address; from the second storage unit, obtain the target read value corresponding to the physical storage address; when the target write value and the target read value are the same , determining that the target storage object in the memory module is in a normal state; or, in a case where the target write value and the target read value are different, determining that the target storage object in the memory module is in an abnormal state.

In some embodiments, the method further includes: when the target write value and the target read value are the same, or when the target write value and the target read value are different and the system recovery instruction has not been received, sending the memory controller return the target read value; or, when the target write value is different from the target read value and a system recovery instruction is received, perform data recovery processing on the target storage object in the memory module.

In some embodiments, the performing data recovery processing on the target storage object in the memory module includes:

Rewrite the target storage object in the memory module to write the target write value into the target storage object in the memory module; perform a reread operation on the target storage object in the memory module, and receive the corrected read data sent by the memory module Get value; if the corrected read value is the same as the target written value, return the corrected read value to the memory controller.

In some embodiments, the method further includes: according to the first storage unit and the second storage unit, counting the number of reads and writes of each storage object in the memory module; after controlling the memory controller to be in an idle state, according to each The number of reads and writes of the storage object determines the storage object to be processed; the read and write test process is performed on the storage object to be processed based on the preset test mode, so that the number of reads and writes of each storage object in the memory module meets the preset requirements.

In some embodiments, after performing read and write test processing on the storage object to be processed based on the preset test mode, the method further includes:

Acquiring the effective write value corresponding to the storage object to be processed from the first storage unit; wherein, the effective write value refers to the target write value in the latest write operation of the storage object to be processed before the memory controller is in an idle state; Perform write processing on the storage object to be processed, so as to write a valid write value into the storage object to be processed; control the memory controller to exit the idle state.

In a second aspect, an embodiment of the present disclosure provides a read-write test device, including:

The parsing control unit is configured to receive a data instruction sent by the memory controller, determine the physical storage address corresponding to the data instruction; and when the data instruction indicates a read operation, perform a read operation on the target storage object in the memory module, and receive the data instruction sent by the memory module. The target read value of ; wherein, the target storage object in the memory module is determined according to the physical storage address;

The comparison unit is configured to obtain the target write value of the target storage object in the memory module in the latest write operation; and compare the target read value with the target write value, and determine the target storage object in the memory module according to the comparison result test results.

In some embodiments, the parsing control unit is further configured to determine the target write value according to the data command when the data command indicates a write operation; perform a write operation on the target storage object in the memory module to write the target write value into The target storage object in the memory module.

In some embodiments, the reading and writing test device also includes a first storage unit and a second storage unit; wherein, the first storage unit is configured to store the write value of each storage object in the memory module; the second storage unit is configured to To store the read value of each storage object in the memory module;

Correspondingly, the resolution control unit is further configured to store the physical storage address and the target write value in the first storage unit after determining the target write value; after determining the target read value, store the physical storage address and the target The read value is correspondingly stored in the second storage unit.

In some embodiments, the comparison unit is specifically configured to obtain the target write value corresponding to the physical storage address from the first storage unit; obtain the target read value corresponding to the physical storage address from the second storage unit; and When the target write value and the target read value are the same, determine that the target storage object in the memory module is in a normal state; or, when the target write value and the target read value are different, determine that the target storage object in the memory module The object is in an abnormal state.

In some embodiments, the reading and writing test device further includes an output unit; the output unit is configured to generate an alarm message when the target write value and the target read value are different, and display the alarm message on a preset display screen ; Wherein, the alarm information is used to indicate that the target storage object in the memory module is in an abnormal state.

In some embodiments, the parsing control unit is further configured to write to the memory when the target write value is the same as the target read value, or when the target write value and the target read value are different and the The controller returns the target read value; or, when the target write value is different from the target read value and a system recovery instruction is received, data recovery processing is performed on the target storage object in the memory module.

In some embodiments, the parsing control unit is further configured to perform a rewrite operation on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module; Perform a re-read operation, and receive the corrected read value sent by the memory module; when the corrected read value is the same as the target written value, return the corrected read value to the memory controller.

In some embodiments, the reading and writing test device also includes a test mode unit; the test mode unit is configured to provide a preset test mode; the comparison unit is also configured to count each memory module according to the first storage unit and the second storage unit The number of reads and writes of a storage object; the analysis control unit is also configured to determine the storage object to be processed according to the number of reads and writes of each storage object in the memory module after the control memory controller is in an idle state; treat it based on a preset test mode The storage object is processed to perform read and write test processing, so that the number of reads and writes of each storage object in the memory module meets a preset requirement.

In some embodiments, the parsing control unit is further configured to obtain the effective write value corresponding to the storage object to be processed from the first storage unit after performing the read and write test processing on the storage object to be processed based on the preset test mode; The storage object performs write processing to write the effective write value into the storage object to be processed; and control the memory controller to exit the idle state; wherein, the effective write value refers to the value of the storage object to be processed before the memory controller is in the idle state The target write value in the most recent write operation.

In some embodiments, the reading and writing test device further includes a data selector; the analysis control unit is further configured to send a first selection instruction to the data selector; or, send a second selection instruction to the data selector;

The data selector is used to control the parsing control unit and the memory controller to be in a connected state after receiving the first selection instruction; or, to control the parsing control unit and the memory module to be in a connected state after receiving the second selection instruction.

In a third aspect, an embodiment of the present disclosure provides a computer storage medium, where the computer storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in the first aspect are implemented.

In a fourth aspect, an embodiment of the present disclosure provides an electronic device, where the electronic device includes the read/write test device as described in the second aspect.

Embodiments of the present disclosure provide a read-write test method and device, a computer storage medium, and electronic equipment, which receive a data instruction sent by a memory controller and determine the physical storage address corresponding to the data instruction; when the data instruction indicates a read operation, the memory The target storage object in the module performs read operation, and receives the target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to the physical storage address; The target write value in the operation; the target read value is compared with the target write value, and the test result of the target storage object in the memory module is determined according to the comparison result. In this way, the data instruction sent by the memory controller can directly determine the physical storage address of the storage object, and then use the physical storage address for subsequent tests, without re-establishing address mapping relationships for different system control platforms; in addition, this read-write test method only It involves the operation of the memory controller and the memory module, without interaction with the external operating system, there will be no compatibility issues, and the flexibility and versatility of the read-write test can be improved.

Description of drawings

FIG. 1 is a schematic flow diagram of a read-write test method provided by an embodiment of the present disclosure;

FIG. 2 is a schematic flowchart of another reading and writing test method provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a read-write test device provided by an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of another read-write test device provided by an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of another read-write test device provided by an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of Module1 provided by an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of Module2 provided by an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. It should be understood that the specific embodiments described here are only used to explain the related application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure.

In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific ordering of objects. Understandably, "first\second\third 3" where permitted, the specific order or sequence may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.

English terms and their abbreviations involved in the embodiments of the present disclosure are described below.

Dynamic Random Access Memory, DRAM: dynamic random access memory;

Memory Down: the memory soldered to the motherboard;

Dual Inline Memory Module, DIMM: Dual Inline Memory Module;

RDIMM: Dual-line memory module with registers;

LRDIMM: Low Load Dual In-line Memory Module;

UDIMM unbuffered dual-channel memory module;

SODIMM: Small Outline Dual Inline Memory Module;

Memory: memory, memory module;

Cell: the storage unit in the memory module, also known as the storage object;

Temporarily Store: temporary storage space;

Memory Controller: memory controller;

DIMM Slot: DIMM slot;

Rank: logical block in memory;

Bank: physical block in memory;

Row Address: row address;

Column Address: column address;

Pre-Charge: pre-charge;

Refresh: refresh;

Central Processing Unit, CPU: central processing unit;

JEDEC: Semiconductor industry standard specified by the Solid State Technology Association;

Raw Card: memory card type;

Serial Presence Detect, SPD: serial presence detection information;

Field Programmable Gate Array, FPGA: Field Programmable Gate Array;

Application Specific Integrated Circuit, ASIC: special application integrated circuit;

Idle: idle state.

For the semiconductor industry, DRAM is an important electronic device that provides storage functions for end devices. Specifically, since DRAM is a dynamic random access memory device, the charge for storing data can only keep the data for a certain period of time. At normal temperature, the retention time of a storage cell capacitor (Cell Capacitor) is usually about 64 milliseconds. Therefore, in order to ensure the normal storage of data, it is necessary to periodically refresh the storage unit (Periodical Refresh) to keep the data stable.

During the normal operation of the terminal device, the CPU usually puts the running data and the temporary data in the operation in the memory, that is, the memory can be understood as a large-capacity temporary storage (Temporarily Store). If the data is not kept intact in the memory, an error will occur when the operating system reads out the data, which will cause the entire system to crash or restart.

For the terminal equipment, the corresponding instruction is sent to the DRAM through the memory controller to realize data writing and reading. Specifically, during the working process of DARM, the memory controller (Memory Controller) sends the following parameters to the memory DRAM in sequence: (1) Select the Memory Controller; (2) Select the DIMM Slot; (3) Select the Rank address; ( 4) Select Bank Address, Row Address; (5) Select Column Address for read/write operations; (6) Other operations, such as Pre-Charge/Refresh and other operations.

In general, servers, laptops, and various consumer electronics all involve DRAM devices, which are used to store large amounts of data that are temporarily involved while the CPU is running. Therefore, errors in the data stored in DRAM will bring catastrophic failures to electronic products, such as system downtime and system restart.

Therefore, memory reading and writing test (also known as stress test, Stress test) is an important test of memory, which is used to test the reliability and stability of DRAM. At present, the common Stress APP tools include MemtestX86, Primer95, Memtester, StressAPP, etc. However, in the actual test, it is found that these softwares are related to issues such as system compatibility and software upgrades; moreover, the addresses reported by different Stress APPs for the same test location in the memory may be different, and it is likely that the Stress APP occurred when resolving the address. error; moreover, if multiple errors occur in the memory, the system may crash or restart, and the Stress APP will also hang up at this time, which brings great trouble to system analysis; in addition, these Stress APPs are all for specific operations Developed under the system, then the compatibility of the operating system and the compatibility of the CPU must be considered during development, and the development cycle is quite long; finally, the stress apps shown above have no way to control the Stress pressure exerted on each address in the memory size (that is, the number of reads and writes performed by each address may be different), resulting in inaccurate final test results.

Based on this, an embodiment of the present disclosure provides a read/write test method. The basic idea is: receive the data instruction sent by the memory controller, and determine the physical storage address corresponding to the data instruction; The target storage object in the memory module is read, and receives the target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to the physical storage address; the target storage object in the memory module is acquired in the latest write operation The target write value; compare the target read value with the target write value, and determine the test result of the target storage object in the memory module according to the comparison result. In this way, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then use the physical storage address for subsequent testing, without re-establishing address mapping relationships for different system control platforms; secondly, the read-write test method It only involves the operation of the memory controller and the memory module, without interacting with the external system control platform, there will be no compatibility issues, and the flexibility and versatility of the read-write test can be improved; in addition, the read-write test method also There is an error correction mechanism, which can correct the read and write errors found in time to avoid system crashes; finally, the read and write test method also has a pressure equalization mechanism, which can ensure that the read and write pressures of different storage units are the same and improve the test accuracy.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, refer to FIG. 1 , which shows a schematic flowchart of a read/write test method provided by an embodiment of the present disclosure. As shown in Figure 1, the method may include:

S101: Receive a data instruction sent by a memory controller, and determine a physical storage address corresponding to the data instruction.

It should be noted that the read-write test method provided by the embodiments of the present disclosure is applied to a read-write test device, or a terminal device integrated with a read-write test device. During implementation, the terminal device may be various types of devices with memory modules. For example, the terminal device may be a device such as a smart phone, a tablet computer, a palmtop computer, a television, a projector, a personal computer, a personal digital assistant (Personal Digital Assistant, PDA), a wearable device, etc., without any limitation here.

The read-write test device is a hardware module connected between the memory controller (Memory Controller) and the memory module (such as DIMM). Specifically, the memory module includes multiple storage objects (or called storage units, Cells), and the memory controller can send different instructions to the memory module to implement read/write operations on different storage objects.

It should be noted that when the memory controller actually writes or reads the memory module, it needs to send the actual physical address of the target storage object to operate the memory module. On this basis, since the read-write test device is set between the memory controller and the memory module in the form of hardware, the read-write test device can receive and analyze the data instructions sent by the memory controller, and determine the The corresponding physical storage address.

For example, when the memory module is composed of multiple DIMMs, the data instructions issued by the memory controller include at least the following addresses: memory channel address (Memory Channel), dual in-line memory module slot address (DIMM Position), memory Rank address (Rank Selection), memory Bank address (Bank Selection), row address (Row Address Selection) and column address (Column Address Selection), the above addresses constitute the physical storage address of this data instruction.

In other words, in related technologies, it is generally necessary to implement the reading and writing test of the memory module through the Stress APP, and the Stress APP needs to test the memory module according to the logical storage address. When an error is found, it needs to be further resolved through address analysis. Physical storage address. The embodiment of the present disclosure develops a read-write test device from the perspective of hardware, which is installed between the memory controller and the memory module. Through the read-write test device, the data instruction issued by the memory controller can be directly analyzed to obtain the physical storage address. , and then use the physical storage address instead of the logical storage address for subsequent testing. Therefore, even in different operating systems, there is no need to re-establish the address mapping relationship, thereby improving the generality and flexibility of the stress test.

S102: When the data instruction indicates a read operation, perform a read operation on a target storage object in the memory module, and receive a target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to a physical storage address.

It should be noted that there are multiple different storage objects (Cells) in the memory module, and these storage objects are distinguished by physical storage addresses. Therefore, when the data instruction indicates a read operation, the read/write test device can control the memory module to perform the read operation according to the physical storage address, so as to obtain the target read value of the target storage object.

S103: Obtain the target write value of the target storage object in the most recent write operation in the memory module.

It should be noted that the read/write test device has a separate storage space for storing the written value of each storage object in the memory module in the latest write operation.

S104: Comparing the target read value and the target write value, and determining the test result of the target storage object in the memory module according to the comparison result.

It should be noted that, on the premise that the target storage object is in a normal state, the target read value and the target write value should be the same. Therefore, according to the actual comparison result of the target read value and the target write value, the test result of the target storage object can be determined.

In some embodiments, the method may also include:

When the data command indicates a write operation, determine the target write value according to the data command;

A write operation is performed on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module.

It should be noted that when the data command indicates a write operation, the read-write test device needs to analyze the data command to determine the target write value, and then write the target write value into the target storage object.

It should also be noted that the read-write test device can be provided with a separate storage space for storing data required in the test process. Therefore, in some embodiments, the read/write test device includes a first storage unit and a second storage unit. Correspondingly, the method may also include:

After determining the target write value, correspondingly storing the physical storage address and the target write value into the first storage unit;

After the target read value is determined, the physical storage address and the target read value are correspondingly stored in the second storage unit.

It should be noted that the first storage unit is configured to store the physical storage address and the value to be written (such as the target write value) in all write operations; the second storage unit is configured to store the physical storage address and the actual value in all read operations. Read value (eg target read value).

In this way, by comparing the write value and the read value at the same physical storage address in the first storage unit and the second storage unit, the read/write test result of the storage object can be obtained. Therefore, in some embodiments, the comparing the target read value with the target write value, and determining the test result of the target storage object in the memory module according to the comparison result may include:

Obtain a target write value corresponding to the physical storage address from the first storage unit;

Obtain a target read value corresponding to the physical storage address from the second storage unit;

If the target write value and the target read value are the same, determine that the target storage object in the memory module is in a normal state; or, if the target write value and the target read value are different, determine that the target storage object in the memory module is The storage object is in an abnormal state.

It should be understood that the same storage object actually has multiple read and write processes, that is, there may be multiple write values at one physical storage address in the first storage unit, and there may be multiple write values at one physical storage address in the second storage unit. read the value. In the embodiment of the present disclosure, the target write value refers to the write value in the last write operation for the physical storage address before the read operation corresponding to the target read value occurs.

In particular, in some embodiments, the read-write test device may only include the first storage unit, and immediately after the target storage object is read, the target read value obtained by reading and the value stored in the first storage unit may be combined. The target written value is compared to obtain the test result.

It should also be noted that, for the terminal device, in order to save the amount of calculation, the read-write test device is enabled only when the read-write test is required. That is to say, when the system is in a normal working state, the memory controller is directly connected to the memory module. At this time, the memory controller directly sends data instructions to the memory module for corresponding read/write operations; In the test state, the memory controller is connected to the memory module through the read-write test device. At this time, the memory controller needs to send data instructions to the read-write test device, and the read-write test device performs corresponding read/write operations on the control memory module. , and at the same time, the read-write test device will also perform other test operations.

The read and write test process is described in detail below.

First, the memory controller issues a data instruction. Assume that the data instruction indicates to write "1" to the storage object at address A. At this time, the read-write test device stores address A and the written value "1" in the first storage unit, and control the memory module to write "1" to the storage unit corresponding to address A.

Then, when the memory controller issues a data instruction again, and the data instruction indicates to read address 1, the read-write test device controls the memory module to read the storage object at address A, assuming that the read value "1 ”, at this time, the read-write test device stores the address A and the read value “1” into the second storage unit.

Finally, the read value is compared with the written value. At this time, the written value "1" is the same as the read value "1", which means that the storage object indicated by address A is in a normal state. On the contrary, if the read value is "0", it means that the storage object indicated by the address A is in an abnormal state.

When the target storage object is in an abnormal state, an alarm mechanism can also be set to remind the staff to pay attention. Therefore, in some embodiments, where the target write value and the target read value are different, the method may further include:

Generate warning information; wherein, the warning information is used to indicate that the target storage object in the memory module is in an abnormal state; and display the warning information on a preset display screen.

Exemplarily, the preset display screen can be divided into left and right parts, one part is used to display the written values of different storage objects in the memory module in real time, and the other part is used to display the read values of different storage objects in the memory module in real time. If it is found that the target write value of a storage object is different from the target read value, the staff can be reminded through pop-up messages, highlighting, red box warnings, etc.

In some embodiments, the method also includes:

Returns the target read value to the memory controller if the target write value is the same as the target read value, or if the target write value is different from the target read value and a system recovery command has not been received; or, When the input value is different from the target read value and a system recovery instruction is received, data recovery processing is performed on the target storage object in the memory module.

It should be noted that, after obtaining the target read value, the read-write test device needs to return the target read value to the memory controller to complete the command closed-loop of the memory controller, otherwise the memory controller will have an error. However, if there is a data error in a large number of storage objects/an important storage object, directly returning the read value may cause the system to crash. Therefore, the embodiment of the present disclosure also sets a system recovery mechanism. Here, the system recovery mechanism can be enabled or disabled according to user needs.

Specifically, if the target write value is the same as the target read value, that is, the target storage object is in a normal state, the target read value may be directly returned to the memory controller. If the target write value is different from the target read value, and the system recovery command sent by the user is not received, the target read value is also returned to the memory controller. If the target write value is different from the target read value, and a system recovery instruction sent by the user is received, data recovery processing is performed on the target storage object.

It should also be noted that the data recovery processing specifically refers to attempting to re-write and read to the target storage object. Therefore, in some embodiments, the performing data recovery processing on the target storage object in the memory module may include:

Rewriting the target storage object in the memory module to write the target write value into the target storage object in the memory module;

Perform a reread operation on the target storage object in the memory module, and receive the corrected read value sent by the memory module;

In a case where the corrected read value is the same as the target written value, the corrected read value is returned to the memory controller.

It should be noted that if the corrected read value is different from the target written value, you can try to repeat the above steps; or return the wrong corrected read value to the memory controller, or remind the staff to deal with it.

In this way, through the system recovery mechanism, excessive data errors and system downtime can be avoided, and system stability is improved.

It should also be noted that, in related technologies, the read and write times of each storage unit in the memory module may be different, which leads to different read and write pressures of different storage units, thus affecting the test results. In order to solve this problem, in some embodiments, as shown in Figure 2, the method may also include:

S201: Count the read and write times of each storage object in the memory module according to the first storage unit and the second storage unit.

S202: After controlling the memory controller to be in an idle state, determine the storage object to be processed according to the number of reads and writes of each storage object in the memory module.

S203: Perform read and write test processing on the storage object to be processed based on a preset test mode, so that the number of reads and writes of each storage object in the memory module meets a preset requirement.

It should be noted that, according to the foregoing, if a write operation is performed on a storage object, a write value will be added to the physical storage address of the storage object in the first storage unit; data, a read value will be added to the physical storage address of the storage object in the second storage unit. Therefore, according to the amount of data stored in the first storage unit and the second storage unit, the number of reads and writes of different storage objects can be counted. Then, the storage object with less read and write times is determined as the storage object to be processed, and the read and write test is performed separately on the storage object to be processed, so that the read and write times of different storage objects are about the same.

It should be noted that the number of reads and writes may indicate the number of reads, the number of writes, the sum of the number of reads and the number of writes, or the number of reads and writes may also include the number of reads and the number of writes. Correspondingly, the preset test mode may indicate a specific process of how to determine the number of reads and writes according to the number of reads and writes of the storage object to be processed. The parameters of the preset test mode can be defined by the user.

In addition, a threshold (for example, 5 times, 10 times) can be set according to actual needs. If the difference in the number of reads and writes between two storage objects in the memory module does not exceed the threshold, it is considered that the number of reads and writes of different storage objects meets the preset requirements. .

It should also be noted that since the pressure equalization mechanism is provided by the read/write test device 30 , it has nothing to do with the memory controller. Therefore, after determining those storage objects to be processed with fewer reading and writing times, it is necessary to control the memory controller 31 to enter the idle state, and to hand over the control right of the memory module 32 to the reading and writing testing device 30, and then the reading and writing testing device 30 Use the preset test mode to perform read and write test processing on the storage object to be processed.

In some embodiments, after the read/write test is performed on the storage object to be processed based on the preset test mode, the method may further include:

Acquiring the effective write value corresponding to the storage object to be processed from the first storage unit; wherein, the effective write value refers to the target write value in the latest write operation of the storage object to be processed before the memory controller is in an idle state;

Perform write processing on the storage object to be processed, so as to write the effective write value into the storage object to be processed;

Controls the memory controller to exit the idle state.

It should also be noted that for the memory controller, the written value in the pending storage object needs to remain unchanged, otherwise the system will crash. Therefore, before the control memory controller exits the idle state, it is necessary to rewrite the previously valid write value to the storage object to be processed.

In this way, by providing a pressure equalization mechanism, it is possible to avoid the situation that different storage objects have different reading and writing pressures, and improve the reliability of test results.

In related technologies, generally, a stress test is performed on the memory stick through a stress test tool (Stress APP), so as to test the stability and reliability of the memory. However, on the one hand, because the Stress APP tool needs to use the logical storage address for read and write tests, if one or more data input/output channel signals (generally called DQ signals) errors occur during the test, the Stress APP needs to analyze the data according to the address mapping. Only by analyzing the relationship can we know the address of the wrong data. If the system platform is changed, the Stress APP needs to redevelop the software and re-establish a new address mapping analysis relationship to correctly locate the error; on the other hand, the Stress APP also needs to consider the operation System compatibility and other issues, so the Stress APP tool needs to be continuously updated, resulting in unfriendly versatility; on the other hand, when there are too many errors, it may exceed the error correction capability of the system platform. At this time, the system It has already crashed, and the Stress APP crashes accordingly, that is, the Stress APP cannot cope with many errors; on the other hand, the existing Stress APP has no good way to count and guarantee the stress results of each address in the memory.

In order to solve the problems existing when the memory module runs the read-write test, the embodiment of the present disclosure develops a module that can test the pressure of different storage objects in Memory and the pressure of each storage object is equal from the hardware point of view, avoiding problems caused by Stress The development cycle and verification cycle of the APP are too long, which leads to the problem that the test cannot be carried out.

Specifically, since the system operates on the Memory by sending the actual physical storage address during the actual writing or reading operation of the Memory, the specific command sending sequence is generally: Memory Channel, Rank Selection&DIMM Position, Bank Selection, Row Address Selection and Column Address Selection.

Therefore, a read-write test device capable of parsing Memory commands can be established between the Memory Controller and Memory, and the write and The read data is recorded separately, that is, the first storage unit is used to store the written value in the write operation, and the second storage unit is used to store the read value in the read operation. Then, compare the written value and the read value, and display and output the comparison result through the display screen.

In this way, if erroneous data occurs, the specific physical address of the erroneous data can be directly displayed without additional address analysis. In addition, according to the first storage unit and the second storage unit, it is possible to carry out Stress statistics on different addresses, and use the built-in preset test mode to conduct separate Stress tests on addresses with relatively small Stress, so as to ensure that the Stress of each address reaches the same or approximately. In this way, by counting the stress of each address in the memory, individual stress tests can be performed on addresses with low stress, so as to ensure that the stress of each address in the memory is equal or as equal as possible. In addition, the data recovery mechanism can also be used to avoid system downtime or restart due to too much error data.

The embodiment of the present disclosure provides a read-write test method, which determines the physical storage address corresponding to the data command by receiving the data command sent by the memory controller; when the data command indicates a read operation, reads the target storage object in the memory module Operate, and receive the target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to the physical storage address; obtain the target write value of the target storage object in the memory module in the latest write operation; The target read value is compared with the target write value, and the test result of the target storage object in the memory module is determined according to the comparison result. In this way, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then use the physical storage address for subsequent testing, without re-establishing address mapping relationships for different system control platforms; secondly, the read-write test method It only involves the operation of the memory controller and the memory module, without interacting with the external system control platform, there will be no compatibility issues, and the flexibility and versatility of the read-write test can be improved; in addition, the read-write test method also There is an error correction mechanism, which can correct the read and write errors found in time to avoid system crashes; finally, the read and write test method also has a pressure equalization mechanism, which can ensure that the read and write pressures of different storage units are the same and improve the test accuracy.

In another embodiment of the present disclosure, refer to FIG. 3 , which shows a schematic structural diagram of a read/write test device 30 provided by an embodiment of the present disclosure. As shown in Figure 3, the read-write test device 30 may include:

The analysis control unit 301 is configured to receive a data instruction sent by the memory controller, determine the physical storage address corresponding to the data instruction; and when the data instruction indicates a read operation, perform a read operation on the target storage object in the memory module, and receive the memory module The sent target read value; wherein, the target storage object in the memory module is determined according to the physical storage address;

The comparison unit 302 is configured to obtain the target write value of the target storage object in the memory module in the latest write operation; and compare the target read value with the target write value, and determine the target storage object in the memory module according to the comparison result The object's test results.

It should be noted that the embodiment of the present disclosure provides a read-write test device 30 from the perspective of hardware, which is arranged between the memory controller and the memory module. The read-write test device 30 can analyze the data instructions sent by the memory controller, In this way, the physical storage address corresponding to the data instruction is determined, and then the physical storage address is used for subsequent testing, instead of the logical storage address for subsequent testing, and there is no need to establish an address mapping relationship, which improves versatility.

Please refer to FIG. 4 , which shows a schematic structural diagram of another read/write test device 30 provided by an embodiment of the present disclosure. As shown in FIG. 4 , the read/write test device 30 is connected between the memory controller 31 and the memory module 32 . The memory module 32 contains a plurality of storage objects, and the memory controller 31 can send different instructions to the memory module 32 through the read/write test device 30 to implement read/write operations on different storage objects.

The read/write test device 30 includes an analysis control unit 301 and a comparison unit 302 . Specifically, after the read-write test device 30 receives the data instruction sent by the memory controller 31, the analysis control unit 301 analyzes the data instruction to determine the physical storage address, and controls the memory module 32 to perform corresponding read and write according to the data instruction. operate. The comparison unit 302 is configured to compare the target write value and the target read value of the target storage object, so as to determine the test result.

Here, the physical storage address includes at least one of the following: channel address, dual in-line memory module slot address, memory Rank address, memory Bank address, row address and column address.

It should also be noted that, in some embodiments, the parsing control unit 301 is also configured to determine the target write value according to the data instruction when the data instruction indicates a write operation; perform a write operation on the target storage object in the memory module to Writes the target write value to the target storage object in the memory module.

That is to say, after the read/write test device 30 receives the data command sent by the memory controller 31, if the data command indicates a write operation, the analysis control unit 301 will perform a write operation on the target storage object in the memory module 32 according to the physical storage address , and store the physical storage address and the target write value; if the data instruction indicates a read operation, the parsing control unit 301 will read the target storage object in the memory module 32 according to the physical storage address to obtain the target object returned by the memory module 32 read the value, and store the physical storage address and the target read value; then, the comparison unit 302 compares the target write value and the target read value to determine the test result of the target storage object.

The read/write test device 30 may set a separate storage space to store the physical storage address/write value or the physical storage address/read value.

As shown in FIG. 4 , the read/write test device 30 may further include a first storage unit 303 and a second storage unit 304 . Correspondingly, the resolution control unit 301 is also configured to store the physical storage address and the target write value in the first storage unit 303 after determining the target write value; after determining the target read value, store the physical storage address It is correspondingly stored in the second storage unit 304 with the target read value.

It should be noted that the first storage unit 303 is configured to store the write value of each storage object in the memory module 32 ; the second storage unit 304 is configured to store the read value of each storage object in the memory module 32 .

In some embodiments, the comparison unit 302 is specifically configured to acquire the target write value corresponding to the physical storage address from the first storage unit 303; and acquire the target read value corresponding to the physical storage address from the second storage unit 304 ; and when the target write value and the target read value are the same, determine that the target storage object in the memory module 32 is in a normal state; or, when the target write value and the target read value are different, determine that the memory module The target storage object in 32 is in an abnormal state.

In some embodiments, as shown in FIG. 4 , the read/write test device 30 further includes an output unit 305;

The output unit 305 is configured to generate warning information when the target write value and the target read value are different, and display the warning information on a preset display screen.

It should be noted that the alarm information is used to indicate that the target storage object in the memory module 32 is in an abnormal state, so as to remind the staff to handle it. In addition, the preset display screen can also be divided into left and right parts to display the written value and read value corresponding to different storage objects in real time.

In order to complete the logical closed-loop of the memory controller, if the memory controller 31 issues a data command indicating a read operation, the read/write test device 30 needs to reply the read value to the memory controller 31 . However, if more data errors occur, the memory controller 31 may crash. In order to solve this problem, in some implementations, the read/write test device 30 also has a system recovery mechanism. Specifically, the parsing control unit 301 is further configured to send the memory controller 31 Return the target read value; or, in the case that the target write value is different from the target read value and a system recovery instruction is received, perform data recovery processing on the target storage object in the memory module 32 .

It should be noted that the system recovery mechanism can be enabled or disabled according to user needs. Therefore, only after a data error occurs (the target write value is different from the target read value) and the system recovery instruction is received, the data on the target storage object will be restored. resume processing; otherwise, return the obtained target read value to the memory controller 31 . Of course, in other embodiments, the system recovery mechanism can also be designed to be always enabled, that is, as long as a data error occurs, data recovery processing will be performed on the target storage object.

In addition, a data recovery button may be set in the read-write test device 30 , and if the user presses the data recovery button, it is determined that a system recovery command is received.

It should also be noted that the essence of data recovery processing is to rewrite and reread the target storage object. Therefore, in some embodiments, the parsing control unit 301 is also configured to perform a rewrite operation on the target storage object in the memory module 32, so as to write the target write value into the target storage object in the memory module 32; The target storage object in 32 performs a re-read operation, and receives the corrected read value sent by the memory module 32; when the corrected read value is identical to the target write value, the corrected read value is returned to the memory controller 31 .

In related technologies, the read and write times of different storage objects may be different during the testing process, thereby affecting the accuracy of the test results. Therefore, in some embodiments, the read/write test device 30 may further include a test mode unit 306 . specifically,

A test mode unit 306 configured to provide a preset test mode;

The comparison unit 302 is further configured to count the number of reads and writes of each storage object in the memory module 32 according to the first storage unit and the second storage unit;

The analysis control unit 301 is also configured to determine the storage object to be processed according to the number of reads and writes of each storage object in the memory module 32 after controlling the memory controller 31 to be in an idle state; read the storage object to be processed based on a preset test mode Write test processing, so that the number of reads and writes of each storage object in the memory module 32 meets the preset requirement.

It should be noted that, according to the data in the first storage unit 303 and the data in the second storage unit 304, the number of times of reading and writing of different storage objects can be counted, and then the reading and writing test processing can be performed on storage objects with fewer times of reading and writing. In this way, the number of reads and writes of different storage objects is controlled to meet the preset requirements.

It should be noted that the preset test mode specifies the specific method of read and write test processing, such as the default write value, the sequence of write operation and read operation, etc. The preset test mode can be modified according to the needs of users.

In addition, the read-write test device 30 also includes a power management unit 307 configured to supply power to the read-write test device. In this way, since the read/write test device 30 has an independent power solution, it can still play a controlling role after the memory controller 31 enters the idle state.

It should also be noted that after the number of times of reading and writing of different storage objects meets the preset requirements, when the number of times of reading and writing of each storage object meets the preset requirements, the reading and writing test device 30 also needs to return the control right to the memory controller 31, that is, the memory controller 31 exits the idle state. However, the value in the storage object to be processed must be consistent before the memory controller 31 enters the idle state and after exiting the idle state, otherwise the memory controller 31 will crash.

Therefore, in some embodiments, the parsing control unit 31 is further configured to obtain the effective write data corresponding to the storage object to be processed from the first storage unit 303 after performing read and write test processing on the storage object to be processed based on the preset test mode. value; perform write processing on the storage object to be processed, so as to write a valid write value into the storage object to be processed; and control the memory controller 31 to exit the idle state.

It should be noted that the effective write value refers to the target write value in the last write operation of the storage object to be processed before the memory controller 31 is in an idle state.

It should also be noted that, in order to facilitate staff to grasp the test situation, the output unit 305 is also configured to display the read/write times of each storage object in the memory module 32 on the preset display screen 33 .

As can be seen from the above, for the read-write test device 30, at first, form a data path with the memory controller 31, thereby receiving and analyzing the data instructions sent by the memory controller 31; then, form a data path with the memory module 32, so that the target The storage object performs a read operation/write operation; finally, a data path is formed with the memory controller 32 to return the operation result of the data instruction.

In other words, the read/write test device 30 needs to form a data path with the memory controller 31 and the memory module 32 in sequence. In order to achieve this purpose, in some embodiments, the read-write test device 30 also includes a data selector;

The parsing control unit 301 is further configured to send a first selection instruction to the data selector; or, send a second selection instruction to the data selector;

It should be noted that, in addition to setting the data selector, the above purpose can also be achieved by using software control.

In related technologies, according to the data storage principle of the DRAM, the time for the DRAM to keep data stable is limited, so the DRAM needs to be constantly refreshed to keep the data stable. In other words, if the data retention time (Retention) of the entire storage unit (Cell) in DRAM is not enough, or the Retention of some cells is not enough, important data will be lost, such as data bits (Data Bits) change from 1 to 0, Or change from 0 to 1. When the data bit changes unexpectedly, it may cause the entire system to go down or restart the system. Therefore, the read/write test of DRAM is an important performance test, but there are various problems in the existing read/write test devices.

Therefore, the embodiment of the present disclosure provides a read-write test device 30, which can be integrated into a motherboard (Motherboard) of a terminal device, or be used as an independent module. In particular, the read-write test device 30 has a completely independent operating system, and it has an independent power supply system at the same time. There are four main functions:

(1) By reading and writing the test device 30, the pressure of each address in the memory module can be judged in the process of the Stress pressure test, and then the value of each address (according to Channel/DIMM/Rank/Row address) is displayed through the display screen Pressure size. At the same time, when the wrong data is tested, the information of the wrong address is displayed on the display screen.

(2) According to the pressure of the Channel/DIMM/Rank/Row address statistics, select a specific test mode to perform a separate stress test on the addresses with low pressure, so as to ensure that the pressure of each address is equal or approximately equal.

(3) It can improve and replace the Stress APP function, eliminating the need for the Stress APP because of the platform upgrade and compatibility development cycle, and the specific information of the error data can be located by hardware.

(4) When the system finds one or more wrong data, it can restore the data to ensure the stability of the operating system.

An embodiment of the present disclosure provides a read-write test device, including an analysis control unit configured to receive a data instruction sent by a memory controller, and determine a physical storage address corresponding to the data instruction; and when the data instruction indicates a read operation , performing a read operation on the target storage object in the memory module, and receiving the target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to the physical storage address; the comparison unit, It is configured to obtain the target write value of the target storage object in the memory module in the latest write operation; and compare the target read value with the target write value, and determine the memory module according to the comparison result The target in stores the test results for the object. In this way, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and then use the physical storage address for subsequent testing, without re-establishing address mapping relationships for different system control platforms; in addition, the read-write test method It only involves the operation of the memory controller and the memory module, does not need to interact with the external system control platform, does not have compatibility problems, and can improve the flexibility and versatility of the read-write test.

In yet another embodiment, refer to FIG. 5 , which shows a schematic structural diagram of another read/write test device 30 provided by an embodiment of the present disclosure. The application scenario includes a memory controller (Memory Controller) 31, a read-write test device 30 and at least one memory module (DIMM or Memory Down) 32.

As shown in FIG. 5 , the read/write test device 30 is arranged between the memory controller 31 and the memory module 32 . Read-write test device 30 is a completely independent control system, including controller (Controller), power supply and power management unit (equivalent to power management unit 307 in Fig. 4), data recovery button, display screen, storage unit, test mode unit (or called Pattern unit), calculation/comparison unit and output unit (not shown) and so on. Wherein, the principle of the controller can be FPGA or customized CPU, and the storage unit can include writing data storage unit 1 (equivalent to the first storage unit 303 in FIG. 4 ), reading data storage unit 2 (equivalent to the first storage unit 303 in FIG. 4 ). second storage unit 304).

It should be understood that the structure of the read-write test device 30 in Fig. 5 refers to some module physical structures, rather than the functional structure in the strict sense, for example, the part of the controller in Fig. Analysis control unit 301, the controller among Fig. 5 and calculation/comparison unit are functionally equivalent to comparison unit 302 among Fig. 4, controller among Fig. 5 and some devices (not shown in Fig. 5) that can carry out data output output) are functionally equivalent to the output unit 305 in FIG. 4 .

In practical applications, there may be multiple data channels (Channel) in the memory controller 31, and for each Channel, a read-write test device 30 can be separately set up, which is used to locate the data error address in the memory module 32 and to correct it. wrong. In order to improve device usage efficiency, a controller can be set separately for each Channel (such as controller 0 and controller N in Figure 5), while sharing other parts.

In general, the embodiments of the present disclosure relate to various electronic products. On servers, computers and consumer platforms, they are all applied to Memory (such as DRAM, LR/RDIMM, UDIMM, SODIMM, etc.), and the data in the memory is complete Integrity affects the operation of the entire system, especially in server applications, the data integrity of memory is particularly important. The read-write test device 30 provided by the embodiment of the present disclosure can quickly and accurately locate the wrong data address when the memory (such as normal read-write or stress test) has erroneous data, thereby effectively improving the stability and reliability of the memory. , also helps to ensure that the function test and the stress test are carried out smoothly; and, the read-write test device 30 can also count the actual size of the Stress pressure of the storage object in each Rank/Bank in the Memory, and according to the Stress pressure size of the statistics, the pressure is small The address of each address is subjected to a separate Stress test according to a specific Pattern, so as to ensure that the Stress of each address is equal or similar; in addition, when multiple data errors occur, the wrong data can be corrected, and it is also very important for the stable operation of the operating system. big help.

The read/write test device 30 can be realized by two different hardware structures, which are respectively called Module1 and Module2. In other words, in the following embodiments, both Module1 and Module2 are essentially read-write test devices 30, which can play the same function. The main difference between the two is: (1) Module1 is more complicated than the hardware of Module2 , the cost is also higher, and it will take a certain amount of time, but the software is slightly simpler; (2) Module2 has more complicated software, but the hardware cost is lower. In particular, both the controllers in Module1 and Module2 have the function of parsing data instructions (or called Command commands) of the memory controller 31 .

Please refer to FIG. 6 , which shows a schematic structural diagram of Module1 provided by an embodiment of the present disclosure. As shown in Figure 6, Module1 includes a controller, a data recovery button, a high-speed data selector (High Speed Mux), a power supply and power management unit, a first storage unit (or called a write data storage unit 1), a second storage unit unit (or called read data storage unit 2), test mode unit. At the same time, a comparison unit, an output unit and an analysis control unit are integrated in the controller. Wherein, the parsing control unit is mainly configured to parse Command commands and control the high-speed data selector. In particular, the controller can be realized by, for example, FPGA or ASIC.

In Fig. 6, the data path between the high-speed data selector and the memory controller 31 is called A, the data path between the high-speed data selector and the controller is called B, and the data between the high-speed data selector and the memory module The pathway is called C.

As shown in FIG. 6, when writing data, the high-speed data selector first controls AB to be turned on, so that the memory controller 31 sends data instructions to the controller (generally including CMD signal/CA signal/CTL signal/DQ signal/ DQS signal); the high-speed data selector controls the BC conduction again, so that the controller sends a control signal (generally a Control Signals signal) to the memory module 32 to control the memory module 32 to write data; otherwise, when reading data , the high-speed data selector first controls CB to be turned on, so that the controller controls the memory module 32 to read data; the high-speed data selector then controls AB to be turned on, so that the controller returns the read result to the memory controller 31 .

That is to say, Module1 has an independent power supply and power management unit, and can switch the data paths of the memory controller 31 , the read-write test device 30 and the memory module 32 through a high-speed data selector. In this way, the read/write test device 30 can collect data commands and other information between the memory controller 31 and the memory module 32, and save these information at the same time. Then, by comparing the written and read information before and after, the comparison result is displayed on the display screen by means of the data comparison output unit, for example, the address of the wrong data can be displayed. In addition, the read-write test device 30 counts the read-write times (ie, the pressure) of each address, so as to conduct individual tests more specifically.

In particular, each DIMM has a Raw Card definition in JEDEC. The Raw Card type information can be obtained by reading the SPD information on the DIMM. If the test result indicates that there is error data, it can be based on the Raw Card information and The address of the data error is used to locate the position of the particle on the DIMM where the data error occurs (that is, to locate the storage object where the error occurs), and the error location information can be displayed on the display.

For Module1, its specific control logic is divided into the following parts:

(1) The controller in Module1 can analyze the Command command between the memory controller 31 and the memory module 32 , and record the read command and write command separately according to the Command command of the memory controller 31 . When storing data, it is also necessary to form a physical storage address according to Channel, DIMM Slot, Rank, Banks, Row, Column and other information for recording.

(2) Write operation, after the controller in Module1 parses the write command, the controller records all write data, and stores the write data into the first storage unit according to Channel, DIMM Slot, Rank, Banks, Row, and Column. At the same time, the controller switches the high-speed data selector from the original BA path to the BC path, and the controller writes all write values (recording data in sequence) to the specified storage object in the memory module 32 .

(3) Read operation, after the controller in Module1 parses the read command, the high-speed data selector switches to the BC channel, the controller reads the data, and reads the data according to Channel, DIMM Slot, Rank, Banks, Row, and Column Store in the second storage unit; then, compare the read data with the data in the first storage unit (comparison of the same Channel, DIMM Slot, Rank, Banks, Row, Column). If no error occurs, the controller switches the high-speed data selector from the CB channel to the BA channel. If one or more abnormalities are found in the data, the error information can be displayed on the display screen, and the corresponding Channel, DIMM Slot, Rank will be displayed at the same time. , Banks, Row, Column and other information.

In particular, if the read operation is aimed at multiple storage objects, when the read operation is continued according to the read command, if there is a new error after comparing the subsequent read data with the previously written data, it will also be displayed on the display screen. Error information, and display the corresponding Channel, DIMM Slot, Rank, Banks, Row, Column and other information at the same time.

(3.1) Error recovery mechanism (or system recovery mechanism), if the controller finds one or several data errors, the user can press the data recovery button (equivalent to sending a system recovery command), and the controller can restore the memory Write it once and read it again. If the read data is consistent with the written data, the controller will switch the high-speed data selector from the original BC channel to the BA channel or from the original BC channel to the CA channel according to actual needs. path, at this time, the memory controller 31 is directly connected to the memory module 32 .

(3.2) When a data error occurs, if the data recovery button is not pressed, the controller will automatically switch the high-speed data selector from the BC channel to the BA channel.

(4) For the staff, find the particles on the DIMM through the recorded Channel, DIMM Slot, Rank, Banks, Row, Column and other information and the Row Card information of the corresponding DIMM (obtainable through SPD information), and can display The screen displays the DIMM where the error occurred and the location of the particle.

(5) Utilize the comparison unit to carry out statistics on the data in the first storage unit and the second storage unit, determine the number of reads and writes of each address according to the result of the comparison unit, and obtain the statistical result of the Stress size of different addresses. According to the statistical results, a specific stress test is performed on addresses with low stress. The method is as follows: first, the memory controller 31 is made to enter the Idle mode. At this time, the memory controller 31 does not operate the DRAM. Since the Module1 has a separate power supply and power management unit, the Module1 can work normally and can operate the memory module 32; Then, according to the previous Stress test results of different addresses in the memory, Module1 performs a separate stress test on addresses with less stress according to the preset test mode. The preset test mode can be provided by the test mode unit, so that the Stress of each address can be guaranteed. The pressures are equal or approximately equal; finally, when the stress testing module exits the operation on the DRAM, the stress testing module writes the data previously written into the first storage unit into the DRAM.

In this way, through Module1, all the functions of the read-write test device 30 can be realized.

Please refer to FIG. 7 , which shows a schematic structural diagram of Module2 provided by an embodiment of the present disclosure. As shown in Figure 7, Module2 includes a controller, a data recovery button, a power supply and power management unit, a display screen, a first storage unit, a second storage unit, and a test mode unit; at the same time, a comparison unit and an output unit are integrated in the controller and analytical control unit. Wherein, the parsing control unit is mainly configured to parse Command commands and play a control role.

For Module2, its specific control logic is divided into the following parts:

(1) When the main board is running, Module2 acts as the analysis function of the data information between the memory controller 31 and the memory module 32 and the resolution of the Memory control command; according to the Command command information of the memory controller 31, write and The read data is recorded separately, and recorded according to Channel, DIMM Slot, Rank, Banks, Row, Column and other information;

(2) Write operation, when the controller in Module2 parses the write command, the controller records all written data, and stores the written data into the first storage unit according to Channel, DIMM Slot, Rank, Banks, Row, and Column ;

(3) Read operation, when the controller in Module2 parses the read command, the controller reads the data, stores the read data into the second storage unit according to Channel, DIMM Slot, Rank, Banks, Row, and Column, and Compare with the data in the first storage unit (for the same Channel, DIMM Slot, Rank, Banks, Row, Column comparison), if one or more of the data is found to be different, an error message can be displayed on the display screen, and the corresponding Channel, DIMM Slot, Rank, Banks, Row, Column and other information.

Then, in the subsequent read operation, if new error information is found after data comparison, the error information will also be displayed on the display screen, and the corresponding Channel, DIMM Slot, Rank, Banks, Row, Column and other information will be displayed at the same time.

(4) error recovery mechanism, when the controller finds one or several data, the data recovery button on the Module2 can be pressed immediately, and the controller can rewrite the memory once (the memory controller 31 does not write the memory module 32 at this moment). operation), and then read the memory data;

(5) Find the particles on the DIMM through the recorded Channel, DIMM Slot, Rank, Banks, Row, Column and other information and the Row Card information of the corresponding DIMM, and display the DIMM and particle position where the error occurred through the display.

(6) According to the result of the comparison unit, the number of times of reading and writing of each address is counted, and the statistical result of the stress size of different addresses is obtained. According to the statistical results, a specific Pattern stress test is performed on addresses with low stress. The method is as follows: first, make the memory controller 31 enter the Idle mode, at this time, the memory controller 31 does not operate the DRAM, and because the power supply and power management unit of Module2 are independent, Module2 can work normally and can operate the memory module 32 Operation, according to the previous Stress test results on different addresses in the memory, Module2 performs a separate stress test on addresses with low Stress pressure according to the preset test mode. The default test mode can be to select one or more of the Pattern units in the stress test module, so as to ensure that the Stress pressure of each address is equal or approximately equal. When Module2 exits the DRAM operation, Module2 will write the previous to the first storage unit The data in is written into DRAM.

In Figure 7, DQ/DQS are signals related to data, and CMD/CA/CTL are signals related to commands, addresses and control.

In this way, all the functions of the read/write test device 30 can also be realized through the Module2.

To sum up, the embodiment of the present disclosure aims to protect a mechanism module function and similar functions that can test the pressure of Memory Stress and ensure that the pressure is equal to each other. Specifically, the embodiment of the present disclosure provides a read-write test device 30, which has the following functions: On the one hand, the read-write test device 30 can detect whether there is any error data when the memory module is subjected to a Stress test, and the display screen can Visually see the physical address information where the error data occurs; on the other hand, the read-write test device 30 can count the Stress pressure size of each address, and select a specific test mode for the address with a small Stress pressure to carry out a stress test, thereby ensuring that each address The Stress size is the same or similar; on the other hand, when the memory is stress tested, the read-write test device 30 records the address according to the hardware physical method, without considering the compatibility of the Stress APP system, and will not occur when a data error occurs. There are problems such as being unable to locate the wrong address or inaccurate positioning; on the other hand, when the memory module 32 sends an error in data, the reading and writing test device 30 can be used to correct the erroneous data to prevent the system from going down or restarting.

The embodiment of the present disclosure provides a read-write test method. Through this embodiment, the specific implementation method of the foregoing embodiment is described in detail. It can be seen from this that the data command sent by the memory controller can directly determine the corresponding The physical storage address, and then use the physical storage address to carry out subsequent tests, without re-establishing the address mapping relationship for different system control platforms; secondly, this read and write test method only involves the operation of the memory controller and memory modules, and does not need to communicate with external The system control platform interacts without compatibility problems, which can improve the flexibility and versatility of the read-write test; in addition, the read-write test method also has an error correction mechanism, which can correct the read-write errors found in time. Avoid system crashes; finally, the read-write test method also has a pressure equalization mechanism, which can ensure that the read-write pressure of different storage units is the same and improve test accuracy.

In yet another embodiment of the present disclosure, based on the schematic composition diagram of the above-mentioned read/write test device 30 , refer to FIG. 8 , which shows a schematic composition diagram of an electronic device 40 provided by an embodiment of the present disclosure. As shown in FIG. 8 , the electronic device 40 at least includes the read/write test device 30 of any one of the foregoing embodiments.

For the electronic device 40, since it includes the read-write test device 30, the data command sent by the memory controller can directly determine the physical storage address corresponding to the data command, and then use the physical storage address to perform subsequent tests without the need for different system control The platform re-establishes the address mapping relationship; secondly, the read-write test method only involves the operation of the memory controller and the memory module, and does not need to interact with the external system control platform, there will be no compatibility problems, and the read-write test can be improved. Flexibility and versatility; in addition, the read-write test method also has an error correction mechanism, which can correct the read-write errors found in time to avoid system crashes; finally, the read-write test method also has a pressure equalization mechanism, which can ensure The reading and writing pressure of different storage units is the same, which improves the test accuracy.

It can be understood that, in the foregoing embodiments, a "unit" may be a part of a circuit, a part of a processor, a part of a program or software, etc., of course it may also be a module, and it may also be non-modular. Moreover, each component in this embodiment may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software function modules.

If the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or The part contributed by the prior art or the whole or part of the technical solution can be embodied in the form of software products, the computer software products are stored in a storage medium, and include several instructions to make a computer device (which can be a personal A computer, a server, or a network device, etc.) or a Processor (processor) executes all or part of the steps of the method of this embodiment. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (Read Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other various media that can store program codes.

Therefore, this embodiment provides a computer storage medium, the computer storage medium stores a computer program, and when the computer program is executed by multiple processors, the steps of any one of the methods in the preceding embodiments are implemented.

The above are only preferred embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure.

It should be noted that in this disclosure, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements , but also includes other elements not expressly listed, or also includes elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

The serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure can be combined arbitrarily to obtain new method embodiments if there is no conflict.

The features disclosed in several product embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope of the present disclosure, and should cover all within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Industrial Applicability

Claims

A read-write test method applied to a read-write test device, the method comprising:

receiving a data instruction sent by the memory controller, and determining a physical storage address corresponding to the data instruction;

When the data instruction indicates a read operation, perform a read operation on the target storage object in the memory module, and receive the target read value sent by the memory module; wherein, the target storage object in the memory module is based on the The physical storage address is determined;

Obtain the target write value of the target storage object in the memory module in the latest write operation;

The target read value is compared with the target write value, and the test result of the target storage object in the memory module is determined according to the comparison result.
The reading and writing test method according to claim 1, wherein said method further comprises:

When the data instruction indicates a write operation, determine the target write value according to the data instruction;

Perform a write operation on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module.
The read-write test method according to claim 2, wherein the read-write test device comprises a first storage unit and a second storage unit; the method further comprises:

After determining the target write value, correspondingly storing the physical storage address and the target write value into the first storage unit;

After the target read value is determined, correspondingly store the physical storage address and the target read value into the second storage unit.
The read-write test method according to claim 3, wherein said target read value is compared with said target write value, and the test result of the target storage object in the memory module is determined according to the comparison result, include:

Obtain a target write value corresponding to the physical storage address from the first storage unit;

Obtain a target read value corresponding to the physical storage address from the second storage unit;

When the target write value and the target read value are the same, determine that the target storage object in the memory module is in a normal state; or,

If the target write value and the target read value are different, it is determined that the target storage object in the memory module is in an abnormal state.
The reading and writing test method according to claim 4, wherein said method further comprises:

If the target write value is the same as the target read value, or if the target write value is different from the target read value and a system recovery instruction has not been received, return to the memory controller the target reading; or,

When the target write value is different from the target read value and the system recovery instruction is received, perform data recovery processing on the target storage object in the memory module.
The read-write test method according to claim 5, wherein said performing data recovery processing on the target storage object in the memory module includes:

performing a rewrite operation on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module;

Perform a reread operation on the target storage object in the memory module, and receive the corrected read value sent by the memory module;

If the corrected read value is the same as the target written value, the corrected read value is returned to the memory controller.
The reading and writing test method according to claim 3, wherein said method further comprises:

According to the first storage unit and the second storage unit, count the number of reads and writes of each storage object in the memory module;

After controlling the memory controller to be in an idle state, determine the storage object to be processed according to the number of reads and writes of each storage object in the memory module;

A read-write test is performed on the storage object to be processed based on a preset test mode, so that the read-write times of each storage object in the memory module meet a preset requirement.
The read-write test method according to claim 7, wherein, after performing the read-write test process on the storage object to be processed based on the preset test mode, the method further comprises:

Obtain the effective write value corresponding to the storage object to be processed from the first storage unit; wherein, the effective write value refers to the latest storage object to be processed before the memory controller is in an idle state The target write value in a write operation;

performing write processing on the storage object to be processed, so as to write the effective write value into the storage object to be processed;

controlling the memory controller to exit the idle state.
A reading and writing test device, comprising:

An analysis control unit configured to receive a data instruction sent by the memory controller, determine a physical storage address corresponding to the data instruction; and when the data instruction indicates a read operation, perform a read operation on the target storage object in the memory module, and receiving the target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to the physical storage address;

The comparison unit is configured to obtain a target write value of the target storage object in the memory module in the latest write operation; and compare the target read value with the target write value, and determine the target value according to the comparison result test results for the target storage object in the memory module described above.
The reading and writing test device according to claim 9, wherein,

The parsing control unit is further configured to determine the target write value according to the data instruction when the data instruction indicates a write operation; and perform a write operation on the target storage object in the memory module to convert the The target write value is written to the target storage object in the memory module.
The read-write test device according to claim 10, wherein, the read-write test device also includes a first storage unit and a second storage unit; wherein,

The first storage unit is configured to store the write value of each storage object in the memory module;

The second storage unit is configured to store the read value of each storage object in the memory module;

Correspondingly, the parsing control unit is further configured to store the physical storage address and the target write value in the first storage unit correspondingly after determining the target write value; After the target read value, correspondingly store the physical storage address and the target read value into the second storage unit.
The reading and writing test device according to claim 11, wherein,

The comparison unit is specifically configured to obtain the target write value corresponding to the physical storage address from the first storage unit; obtain the target read value corresponding to the physical storage address from the second storage unit. value; and when the target write value and the target read value are the same, determine that the target storage object in the memory module is in a normal state; or, when the target write value and the target read If the values are different, it is determined that the target storage object in the memory module is in an abnormal state.
The read-write test device according to claim 12, wherein the read-write test device further comprises an output unit;

The output unit is configured to generate warning information when the target write value and the target read value are different, and display the warning information on a preset display screen;

Wherein, the alarm information is used to indicate that the target storage object in the memory module is in an abnormal state.
The reading and writing test device according to claim 12, wherein,

The analysis control unit is further configured to: when the target write value is the same as the target read value, or when the target write value is different from the target read value and no system recovery instruction is received , returning the target read value to the memory controller; or, when the target write value is different from the target read value and the system recovery command is received, the memory module Perform data recovery processing on the target storage object in .
The reading and writing test device according to claim 14, wherein,

The parsing control unit is further configured to rewrite the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module; Perform re-read operation on the target storage object, and receive the corrected read value sent by the memory module; if the corrected read value is the same as the target written value, return the corrected value to the memory controller Read the value after the above correction.
The read-write test device according to claim 15, wherein the read-write test device further comprises a test mode unit;

The test mode unit is configured to provide a preset test mode;

The comparison unit is further configured to count the number of reads and writes of each storage object in the memory module according to the first storage unit and the second storage unit;

The analysis control unit is further configured to determine the storage object to be processed according to the number of reads and writes of each storage object in the memory module after controlling the memory controller to be in an idle state; The storage object to be processed is subjected to read and write test processing, so that the number of reads and writes of each storage object in the memory module meets a preset requirement.
The device for reading and writing testing according to claim 16, wherein the parsing control unit is further configured to read and write the storage object to be processed based on the preset test mode, from the first storage unit Acquiring the effective write value corresponding to the storage object to be processed; performing write processing on the storage object to be processed, so as to write the effective write value into the storage object to be processed; and controlling the memory control the device exits the idle state;

Wherein, the effective write value refers to the target write value in the latest write operation of the storage object to be processed before the memory controller is in an idle state.
The read-write test device according to claim 9, wherein the read-write test device further comprises a data selector;

The parsing control unit is further configured to send a first selection instruction to the data selector; or, send a second selection instruction to the data selector;

The data selector is configured to, after receiving the first selection instruction, control the analysis control unit and the memory controller to be in a connected state; or, after receiving the second selection instruction, control the The analysis control unit is in communication with the memory module.
A computer storage medium, the computer storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are realized.
An electronic device, comprising the read-write test device according to any one of claims 9-18.