CN112992252A - Read-write reliability detection method and device, electronic equipment and readable storage medium - Google Patents
Read-write reliability detection method and device, electronic equipment and readable storage medium Download PDFInfo
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Abstract
The application provides a read-write reliability detection method, a device, an electronic device and a readable storage medium, comprising: determining a first pseudo-random calculator function according to the data bus width of the synchronous dynamic random access memory SDRAM; determining a first address initial value of an address bus and a first initial value of a data bus; performing iterative computation for N times from a first initial value of the data bus by using the first pseudorandom calculator function to obtain N computation results; and determining the read-write reliability of the SDRAM by using N +1 pseudo-random values and a first address initial value, wherein the N pseudo-random values and the first address initial value are composed of the N calculation results and the first initial value of the data bus. In the above embodiment, the read-write reliability of the SDRAM is verified by using the calculation result calculated by the pseudo-random counter function, instead of a natural number, so that the problem of numerical concentration is not easy to occur, and the detection of the SDRAM is more accurate.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method and an apparatus for detecting read-write reliability, an electronic device, and a readable storage medium.
Background
When a communication device uses a Field Programmable Gate Array (FPGA) to forward a message, a Synchronous Dynamic Random-Access Memory (SDRAM) is usually required to buffer the message data. Before the SDRAM memories are used, the data bus and the address bus of the SDRAM need to be fully self-checked by the FPGA. The detection method is usually to write the natural number into SDRAM, then read the natural number from SDRAM back, compare it with original natural number, and test the address bus and data bus.
However, the natural numbers are used for inspection, and because the numerical values of the natural numbers are concentrated, the higher bits of the data bus cannot be inspected, so that the detection is not comprehensive and accurate enough.
Disclosure of Invention
An embodiment of the present application provides a method and an apparatus for detecting read/write reliability, an electronic device, and a readable storage medium, so as to solve the problem that the prior art cannot perform comprehensive and accurate detection.
In a first aspect, an embodiment of the present application provides a read/write reliability detection method, which determines a first pseudo random calculator function according to a data bus width of a synchronous dynamic random access memory SDRAM; determining a first address initial value of an address bus and a first initial value of a data bus; performing iterative computation for N times from a first initial value of the data bus by using the first pseudorandom calculator function to obtain N computation results; and determining the read-write reliability of the SDRAM by using N +1 pseudo-random values and a first address initial value, wherein the N pseudo-random values and the first address initial value are composed of the N calculation results and the first initial value of the data bus.
In the above embodiment, since the calculation result calculated by the pseudo random counter function is used to verify the read/write reliability of the SDRAM, instead of the natural number, the problem of concentration of the numerical values is not easily generated, and the detection of the SDRAM is more accurate.
In one possible design, the determining the read-write reliability of the SDRAM by using N +1 pseudo random values composed of the N calculation results and the first initial value of the data bus and the first address initial value includes: sequentially writing N +1 pseudo random values including the N calculation results and a first initial value of the data bus into N +1 storage units with continuous addresses from a storage unit corresponding to the first initial value of the address; reading N +1 pseudo-random values cached by SDRAM from the storage units with the continuous N +1 addresses, and obtaining N +1 pseudo-random values by iteration starting from a first initial value of the data bus by using the first pseudo-random calculator; and determining the read-write reliability of the SDRAM according to whether the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are equal to the N +1 pseudo-random values cached by the SDRAM correspondingly.
In the above-described embodiment, the N +1 pseudo random values may be written into the memory cells having consecutive addresses of the SDRAM in order from the memory cell corresponding to the first address initial value. After N +1 pseudo random values are written into the storage units with continuous N +1 addresses, then N +1 pseudo random values cached by the SDRAM are read from the storage units with continuous N +1 addresses, meanwhile, the first pseudo random calculator is utilized to obtain N +1 pseudo random values from a first initial value in an iteration mode, comparison between the two pseudo random values is carried out, and if the values different from the N +1 pseudo random values obtained by the calculation of the corresponding first pseudo random calculator exist in the N +1 pseudo random values cached by the SDRAM, the poor read-write reliability of the SDRAM is indicated.
In one possible design, the determining the read/write reliability of the SDRAM according to whether the N +1 pseudo-random values obtained by the first pseudo-random calculator and the N +1 pseudo-random values cached by the SDRAM are equal to each other includes: if the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are correspondingly equal to the N +1 pseudo-random values cached by the SDRAM, calculating the initial value of the first address by using the function of the first pseudo-random calculator to obtain an address calculation result; taking the address calculation result as a new first address initial value, taking the (N + 1) th pseudo random value in the (N + 1) th pseudo random values as a new first initial value of the data bus, and executing the following steps: and performing iterative computation for N times from the first initial value of the data bus by using the first pseudorandom computing device function to obtain N computing results, and sequentially writing N +1 pseudorandom values comprising the N computing results and the first initial value of the data bus into N +1 storage units with continuous addresses from the storage unit corresponding to the first initial value of the address until the pseudorandom values which are not equal to the N +1 pseudorandom values cached by the SDRAM exist in the N +1 pseudorandom values obtained by the computation of the first pseudorandom computing device, or the method runs for more than a preset time.
In the foregoing embodiment, if N +1 pseudo-random values cached by the SDRAM are equal to N +1 pseudo-random values calculated by the corresponding first pseudo-random calculator, a new first address initial value may be obtained, and an N +1 th pseudo-random value of the N +1 pseudo-random values calculated by the first pseudo-random calculator is used as a first initial value of a new data bus, and the above operations are repeated until the running time exceeds a preset time period, or a certain pseudo-random value cached by the SDRAM is not equal to the pseudo-random value calculated by the corresponding first pseudo-random calculator.
In one possible design, the determining a first pseudo random calculator function according to a data bus width of the SDRAM includes: determining a first target N value of a pseudo random counter function according to the data bus width of the SDRAM; determining a first target feedback coefficient corresponding to the first target N value according to the corresponding relation between the N value and the feedback coefficient; determining a first pseudorandom calculator function according to the first target feedback coefficient.
In the above embodiments, the first pseudorandom calculator function may be determined in the above manner, and may of course be determined in other manners, and the specific process of determining the first pseudorandom calculator function should not be construed as limiting the present application.
In one possible design, the method further includes: determining a second pseudorandom calculator function according to the number of address buses; determining a second address initial value of the address bus and a second initial value of a data bus; writing a second initial value of the data bus in a storage unit corresponding to the second address initial value; starting iterative computation from a second initial value of the data bus by using the second pseudorandom calculator function to obtain a pseudorandom computation result of each iterative computation; writing the same pseudo-random calculation result in a storage unit corresponding to the pseudo-random calculation result until the pseudo-random calculation result covers all addresses of the SDRAM; reading a pseudo-random value cached by an SDRAM (synchronous dynamic random access memory) from a storage unit corresponding to the initial value of the second address, performing iterative computation from the second initial value by using a second pseudo-random calculator function, obtaining the address of the next storage unit and the corresponding pseudo-random value cached by the SDRAM, and performing iterative computation from the second initial value by using the second pseudo-random calculator;
and comparing the pseudo-random value cached by the SDRAM with the pseudo-random value obtained by the calculation of the corresponding second pseudo-random calculator until the pseudo-random value which is not equal to the pseudo-random value cached by the SDRAM exists in the pseudo-random values obtained by the calculation of the second pseudo-random calculator or the addresses of the SDRAM are completely read.
In the above embodiment, each time a pseudo-random calculation result is obtained, the same pseudo-random calculation result is written in the memory cell corresponding to the data whose address value is the pseudo-random calculation result until all the addresses of the SDRAM are fully written.
In one possible design, the determining the second pseudo-random calculator function based on the number of address buses includes: determining a second target N value of the pseudo-random counter function according to the number of the address buses; determining a second target feedback coefficient corresponding to the second target N value according to the corresponding relation between the N value and the feedback coefficient; and determining a second pseudo-random calculator function according to the second target feedback coefficient.
In the above embodiments, the second pseudo-random calculator function may be determined in the above manner, and of course, the second pseudo-random calculator function may also be determined in other manners, and the specific process of determining the second pseudo-random calculator function should not be construed as limiting the present application.
In a second aspect, an embodiment of the present application provides a device for detecting read/write reliability, where the device includes: the first function determining module is used for determining a first pseudo random calculator function according to the data bus width of the synchronous dynamic random access memory SDRAM; the first initial determination module is used for determining a first address initial value of an address bus and a first initial value of a data bus; the function calculation module is used for starting iterative calculation for N times from a first initial value of the data bus by using the first pseudorandom calculator function to obtain N calculation results; and the reliability determining module is used for determining the read-write reliability of the SDRAM by using the N +1 pseudo-random values and the first address initial value, wherein the N pseudo-random values are composed of the N calculation results and the first initial value of the data bus.
In one possible design, the reliability determination module is to: sequentially writing N +1 pseudo random values including the N calculation results and a first initial value of the data bus into N +1 storage units with continuous addresses from a storage unit corresponding to the first initial value of the address; reading N +1 pseudo-random values cached by SDRAM from the storage units with the continuous N +1 addresses, and obtaining N +1 pseudo-random values by iteration starting from a first initial value of the data bus by using the first pseudo-random calculator; and determining the read-write reliability of the SDRAM according to whether the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are equal to the N +1 pseudo-random values cached by the SDRAM correspondingly.
In one possible design, the reliability determination module is to: if the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are correspondingly equal to the N +1 pseudo-random values cached by the SDRAM, calculating the initial value of the first address by using the function of the first pseudo-random calculator to obtain an address calculation result; taking the address calculation result as a new first address initial value, taking the (N + 1) th pseudo random value in the (N + 1) th pseudo random values as a new first initial value of the data bus, and executing the following steps: and performing iterative computation for N times from the first initial value of the data bus by using the first pseudorandom computing device function to obtain N computing results, and sequentially writing N +1 pseudorandom values comprising the N computing results and the first initial value of the data bus into N +1 storage units with continuous addresses from the storage unit corresponding to the first initial value of the address until the pseudorandom values which are not equal to the N +1 pseudorandom values cached by the SDRAM exist in the N +1 pseudorandom values obtained by the computation of the first pseudorandom computing device, or the method runs for more than a preset time.
In one possible design, the first function determining module is configured to determine a first target N value of the pseudo random counter function according to a data bus width of the SDRAM; determining a first target feedback coefficient corresponding to the first target N value according to the corresponding relation between the N value and the feedback coefficient; determining a first pseudorandom calculator function according to the first target feedback coefficient.
In one possible design, the apparatus further includes: a second function determining module for determining a second pseudo-random calculator function according to the number of the address buses; the second initial determination module is used for determining a second address initial value of the address bus and a second initial value of the data bus; the initial writing module is used for writing a second initial value of the data bus in a storage unit corresponding to the second address initial value; the pseudo-random calculation module is used for starting iterative calculation from a second initial value of the data bus by utilizing the second pseudo-random calculator function to obtain a pseudo-random calculation result of each iterative calculation; and the address covering module is used for writing the same pseudo-random calculation result in the storage unit corresponding to the pseudo-random calculation result until the pseudo-random calculation result covers all the addresses of the SDRAM. Then, starting from the second address initial value of the address bus, reading out the previously stored data from the SDRAM, comparing it with the result calculated by the second pseudo-random calculator function until a pseudo-random value is present, which is not equal to the pseudo-random value buffered by the SDRAM, or all the addresses of the SDRAM are read out, thus detecting the validity of each SDRAM storage unit.
In one possible design, the second function determining module is configured to determine a second target N value of the pseudo-random counter function according to the number of the address buses; determining a second target feedback coefficient corresponding to the second target N value according to the corresponding relation between the N value and the feedback coefficient; and determining a second pseudo-random calculator function according to the second target feedback coefficient.
In a third aspect, an embodiment of the present application provides an electronic device, including the processor of the first aspect or any optional implementation manner of the first aspect.
In a fourth aspect, the present application provides a readable storage medium having stored thereon an executable program which, when executed by a processor, performs the method of the first aspect or any of the optional implementations of the first aspect.
In a fifth aspect, the present application provides an executable program product which, when run on a computer, causes the computer to perform the method of the first aspect or any possible implementation manner of the first aspect.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic flow chart of a read-write reliability detection method provided in an embodiment of the present application;
FIG. 2 is a flowchart illustrating a specific step of step S140 in FIG. 1;
fig. 3 is a schematic flowchart of a specific implementation of a read-write reliability detection method according to an embodiment of the present application;
fig. 4 is a schematic structural block diagram of a read-write reliability detection apparatus provided in an embodiment of the present application;
FIG. 5 is a table showing the correspondence of N values to feedback coefficients;
fig. 6 shows a schematic structural block diagram of an FPGA applied in the read-write reliability detection method provided in the embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
Referring to fig. 1, fig. 1 shows a read-write reliability detection method provided by an embodiment of the present application, where the method may be executed by an FPGA. The method specifically comprises the following steps S110 to S140:
step S110, according to the data bus width of the SDRAM, a first pseudo-random calculator function is determined.
The pseudo-random counter function may be a Linear Feedback Shift Register (LFSR) counter.
Optionally, in a specific embodiment, the step S110 includes the following steps: determining a first target N value of a pseudo random counter function according to the data bus width of the SDRAM; determining a first target feedback coefficient corresponding to the first target N value according to the corresponding relation between the N value and the feedback coefficient; determining a first pseudorandom calculator function according to the first target feedback coefficient.
The target N value of the pseudo-random counter function can be determined according to the width of the data bus, and the N value is the maximum counting width of the pseudo-random counter function LFSR counter. Alternatively, the target N value may be a random value that is less than the data bus width of the SDRAM. For example, if the data bus width of the SDRAM is 64 bits, the target N value may be a random value, for example, 23.
The N value and the feedback coefficient have a corresponding relationship to form a table, please refer to fig. 5, where fig. 5 shows a plurality of N values (N values from 3 to 168), and a plurality of feedback coefficients of the negation corresponding to each N value in the N values. And obtaining a first target feedback coefficient corresponding to the first target N value through table lookup. For example, by looking at the table shown in fig. 5, it can be known that the value of N: 23 correspond to feedback coefficients 23, 18.
After the first target feedback coefficient is obtained, the coefficient of the pseudo-random counter function may be determined, thereby obtaining a first pseudo-random calculator function F1 (x).
In step S120, a first address initial value of the address bus and a first initial value of the data bus are determined.
The first initial value of the address is the specific value of the address of the first memory cell in the SDRAM which performs the data storage operation this time, and the first initial value of the data bus refers to the specific value of the data to be stored in the memory cell. The first address initial value and the first initial value of the data bus may be randomly selected values. For example, it is not assumed that the first address initial value and the first initial value of the data bus are both 0. I.e. indicating that a specific value 0 can be stored in a memory location with an address of 0 in the SDRAM.
Step S130, using the first pseudorandom calculator function to perform iterative calculation N times from the first initial value of the data bus, so as to obtain N calculation results.
Substituting the first initial value 0 into the first pseudo-random calculator function F1(x), may obtain the corresponding calculation result F1 ═ F1 (0); the calculation result F1 is then substituted into the first pseudorandom calculator function F1(x), which in turn results in calculation results F2 — F1 (F1.. the iterative calculation is performed in the manner described above until N calculation results F1, F2, f3... fn are obtained. The number of iterative computations may be any positive integer, for example, 15 iterations are possible, and the specific number of iterative computations should not be construed as a limitation to the present application.
Step S140, determining the read-write reliability of the SDRAM by using N +1 pseudo-random values and the first address initial value, which are composed of the N calculation results and the first initial value of the data bus.
And (3) combining the N calculation results f1, f2 and f3... fn obtained by the calculation with the first initial value of the data bus to form N +1 pseudo-random values, and then determining the read-write reliability of the SDRAM from the first initial value of the address.
In the above embodiment, a first pseudo-random counter function is determined, a first initial address value and a first initial value of the data bus are determined, then iterative computation is performed from the first initial value by using the pseudo-random counter function, and the read/write reliability of the SDRAM is verified by using a computation result obtained by the iterative computation, the first initial value and the first initial address value. In the above embodiment, the read-write reliability of the SDRAM is verified by using the calculation result calculated by the pseudo-random counter function, instead of a natural number, so that the problem of numerical concentration is not easy to occur, and the detection of the SDRAM is more accurate.
Referring to fig. 2, fig. 2 shows a flowchart of the specific step of step S140, which specifically includes the following steps S141 to S143:
step S141, sequentially writing N +1 pseudo random values including the N calculation results and the first initial value of the data bus into N +1 memory cells having consecutive addresses from the memory cell corresponding to the first initial value of the address.
And taking the storage unit corresponding to the first address initial value as a first storage unit, obtaining N +1 storage units with continuous addresses from the first storage unit, and sequentially storing one of N +1 pseudo-random values into each of the N +1 storage units.
For example, for N +1 memory cells having address values from 0 to N, N +1 pseudo-random values from 0 to fn are sequentially stored: a first initial value 0 is stored in a memory cell with an address value of 0, a pseudo-random value f1 is stored in a memory cell with an address value of 1, and a pseudo-random value f2. is stored in a memory cell with an address value of 2.
Step S142, reading N +1 pseudo random values buffered by the SDRAM from the memory units with consecutive N +1 addresses, and obtaining N +1 pseudo random values by using the first pseudo random calculator to iterate from the first initial value of the data bus.
Reading N +1 pseudo-random values buffered by the SDRAM from the storage units with N +1 continuous addresses, and obtaining N +1 pseudo-random values by iteration from the first initial value of the data bus again by using the first pseudo-random calculator.
By performing the above two steps simultaneously, the acquisition time of both can be shortened, so that step S143 can be performed more quickly.
Step S143, determining the read-write reliability of the SDRAM according to whether the N +1 pseudo-random values calculated and obtained by the first pseudo-random calculator are equal to the N +1 pseudo-random values cached by the SDRAM correspondingly.
Because data transmission between the storage units of the FPGA and the SDRAM needs to pass through the data bus, if the data bus is abnormal, the N +1 pseudo-random values cached by the SDRAM and the N +1 pseudo-random values obtained by the calculation of the corresponding first pseudo-random calculator are possibly inconsistent, and therefore whether the corresponding pseudo-random values cached by the SDRAM are consistent with the pseudo-random values obtained by the calculation of the first pseudo-random calculator or not is compared, and whether the read-write reliability brought by the data line and the address line of the SDRAM is reliable or not can be determined.
For the N +1 pseudo random values, N +1 memory locations with consecutive addresses of the SDRAM may be sequentially written from the memory location corresponding to the first address initial value. After N +1 pseudo random values are written in the storage units with continuous N +1 addresses, then N +1 pseudo random values cached by the SDRAM are read from the storage units with continuous N +1 addresses, meanwhile, the first pseudo random calculator is utilized to obtain N +1 pseudo random values from a first initial value in an iteration mode, comparison between the two pseudo random values is carried out, and if the values different from the N +1 pseudo random values obtained by the calculation of the corresponding first pseudo random calculator exist in the N +1 pseudo random values cached by the SDRAM, the SDRAM is indicated to have the problem of reading and writing reliability.
Optionally, step S143 may further include the following steps:
if the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are correspondingly equal to the N +1 pseudo-random values cached by the SDRAM, calculating the initial value of the first address by using the function of the first pseudo-random calculator to obtain an address calculation result; taking the address calculation result as a new first address initial value, taking the (N + 1) th pseudo random value in the (N + 1) th pseudo random values as a new first initial value of the data bus, and executing: step S130, using the first pseudo-random calculator function to perform iterative calculation for N times from a first initial value of the data bus to obtain N calculation results; step S141, sequentially writing N +1 pseudo random values including the N calculation results and the first initial value of the data bus into N +1 memory cells having consecutive addresses from the memory cell corresponding to the first initial value of the address; until the first pseudo-random calculator calculates the N +1 pseudo-random value that obtains has the pseudo-random value unequal to said N +1 pseudo-random value that SDRAM buffers, or the above-mentioned method runs and exceeds the predetermined duration.
If the N +1 pseudo-random values cached by the SDRAM are equal to the N +1 pseudo-random values calculated by the corresponding first pseudo-random calculator, a new first address initial value may be obtained, and the operation is repeated until the operation time exceeds the preset time period, or a certain pseudo-random value cached by the SDRAM is not equal to the pseudo-random value calculated by the corresponding first pseudo-random calculator, taking the N +1 pseudo-random value of the N +1 pseudo-random values calculated by the first pseudo-random calculator as the first initial value of the new data bus. When the running time exceeds the preset time, the corresponding pseudo random value cached by the SDRAM is still consistent with the pseudo random value calculated and obtained by the first pseudo random calculator, which means that the read-write reliability of the SDRAM is better; the fact that a certain pseudo-random value cached by the SDRAM is not equal to the pseudo-random value calculated by the corresponding first pseudo-random calculator means that the SDRAM has the problem of reading and writing reliability.
Optionally, referring to fig. 3, in a specific implementation manner, the read-write reliability detection method provided in the embodiment of the present application may further include the following steps S210 to S250:
step S210, determining a second pseudo-random calculator function according to the number of address buses.
Optionally, step S210 may specifically include the following steps: determining a second target N value of the pseudo-random counter function according to the number of the address buses; determining a second target feedback coefficient corresponding to the second target N value according to the corresponding relation between the N value and the feedback coefficient; and determining a second pseudo-random calculator function according to the second target feedback coefficient.
The number of address buses may be set as the second target N value, for example, if the number of address buses is not set to 28, the value of N is set to 28.
From the table of the correspondence relationship between the N value and the feedback coefficient shown in fig. 5, the target feedback coefficients 28,25 corresponding to the N value 28 are obtained. Determining a second pseudo-random calculator function F2(x) based on the second target feedback coefficient.
Step S220 determines a second address initial value of the address bus and a second initial value of the data bus.
The second address initial value is the specific value of the address of the first memory cell in the SDRAM performing the data storage operation this time, and the second initial value of the data bus refers to the specific value of the data to be stored in the memory cell. The second address initial value and the second initial value of the data bus may be randomly selected values. For example, it is not necessary to set both the second address initial value and the second initial value of the data bus as a. I.e. indicating that a specific value a can be stored in a memory location with address a in the SDRAM.
In step S230, writing a second initial value of the data bus in a memory cell corresponding to the second address initial value.
Step S240, using the second pseudorandom calculator function to start iterative computation from the second initial value of the data bus, and obtaining a pseudorandom computation result of each iterative computation.
After a specific value a is stored in a storage unit with the address of a in the SDRAM, a second pseudo-random calculator function is used for carrying out iterative calculation: substituting the second initial value a into the second pseudo-random calculator function F2(x), so as to obtain a corresponding calculation result F' 1 ═ F2 (a); the result F ' 1 is then substituted into the first pseudo-random calculator function F2(x), which in turn results in a result F ' 2 — F2(F ' 1).
Step S250, writing the same pseudo-random computation result in the storage unit corresponding to the pseudo-random computation result until the pseudo-random computation result covers all addresses of the SDRAM.
Step S260, reading the pseudo random value buffered by the SDRAM from the storage unit corresponding to the second address initial value, and performing iterative computation from the second initial value by using the second pseudo random calculator function to obtain the address of the next storage unit and the corresponding pseudo random value buffered by the SDRAM, and simultaneously performing iterative computation from the second initial value by using the second pseudo random calculator to obtain the pseudo random value.
Step S270, comparing the pseudo-random value cached by the SDRAM with the pseudo-random value obtained by the calculation of the corresponding second pseudo-random calculator until the pseudo-random value obtained by the calculation of the second pseudo-random calculator has a pseudo-random value unequal to the pseudo-random value cached by the SDRAM or the address of the SDRAM is completely read.
In the above embodiment, the second pseudo-random calculator function may be determined according to the number of the address buses, the second address initial value and the second initial value of the data bus may be determined, then the second initial value may be written in the storage unit of the SDRAM corresponding to the second address initial value, and then the second pseudo-random calculator function may be used to start iteration from the second initial value, and each time a pseudo-random calculation result is obtained, the same pseudo-random calculation result may be written in the storage unit corresponding to the data having the address value as the pseudo-random calculation result until all addresses of the SDRAM are fully written. For example, after a specific value a is stored in a memory location with address a in the SDRAM, F' 1 is obtained as F2 (a); the specific value F '1 is stored in the memory location with address F' 1 in the SDRAM and then F '2 is obtained as F2 (F' 1), the specific value F '2 … is stored in the memory location with address F' 2 in the SDRAM until the calculation result is full of all addresses of the SDRAM.
Then, the pseudo-random value buffered by the SDRAM is read from the memory location corresponding to the initial value of the second address, and the address of the next memory location is calculated by the second pseudo-random calculator each time one pseudo-random value is read, thereby facilitating the reading of the pseudo-random value buffered by the SDRAM stored in the next memory location. At the same time, the second pseudo-random calculator is used for carrying out iterative calculation from a second initial value, a pseudo-random value cached by the SDRAM is obtained every time, and meanwhile, the second pseudo-random calculator calculates a corresponding pseudo-random value and compares the pseudo-random value with the corresponding pseudo-random value. After the two are confirmed to be the same, the steps are continued until the pseudo-random value cached by the SDRAM is different from the corresponding pseudo-random value calculated by the second pseudo-random calculator at the same time, or all the addresses of the SDRAM are read.
Alternatively, if the calculated pseudo-random value is outside the address width range, the upper portion of the bits that are outside the address width range may be removed.
The above-mentioned embodiment is full of all addresses of the SDRAM, thus making the reliability detection of the SDRAM more comprehensive.
Referring to fig. 4, fig. 4 shows a device for detecting read/write reliability according to an embodiment of the present application, where the device 300 includes:
the first function determining module 310 is configured to determine a first pseudo random calculator function according to a data bus width of a synchronous dynamic random access memory SDRAM.
The first initial determining module 320 is configured to determine a first initial value of an address bus and a first initial value of a data bus.
A function calculating module 330, configured to perform iterative calculations N times from a first initial value of the data bus by using the first pseudorandom calculator function, to obtain N calculation results.
And a reliability determining module 340, configured to determine the read-write reliability of the SDRAM by using N +1 pseudo-random values and a first address initial value, where the N pseudo-random values are formed by the N calculation results and the first initial value of the data bus.
The reliability determination module 340 is configured to: sequentially writing N +1 pseudo random values including the N calculation results and a first initial value of the data bus into N +1 storage units with continuous addresses from a storage unit corresponding to the first initial value of the address; reading N +1 pseudo-random values cached by SDRAM from the storage units with the continuous N +1 addresses, and obtaining N +1 pseudo-random values by iteration starting from a first initial value of the data bus by using the first pseudo-random calculator; and determining the read-write reliability of the SDRAM according to whether the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are equal to the N +1 pseudo-random values cached by the SDRAM correspondingly.
The reliability determination module 340 is configured to: if the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are correspondingly equal to the N +1 pseudo-random values cached by the SDRAM, calculating the initial value of the first address by using the function of the first pseudo-random calculator to obtain an address calculation result; taking the address calculation result as a new first address initial value, taking the (N + 1) th pseudo random value in the (N + 1) th pseudo random values as a new first initial value of the data bus, and executing the following steps: and performing iterative computation for N times from the first initial value of the data bus by using the first pseudorandom computing device function to obtain N computing results, and sequentially writing N +1 pseudorandom values comprising the N computing results and the first initial value of the data bus into N +1 storage units with continuous addresses from the storage unit corresponding to the first initial value of the address until the pseudorandom values which are not equal to the N +1 pseudorandom values cached by the SDRAM exist in the N +1 pseudorandom values obtained by the computation of the first pseudorandom computing device, or the method runs for more than a preset time.
A first function determining module 310, configured to determine a first target N value of a pseudo random counter function according to a data bus width of the SDRAM; determining a first target feedback coefficient corresponding to the first target N value according to the corresponding relation between the N value and the feedback coefficient; determining a first pseudorandom calculator function according to the first target feedback coefficient.
The device further comprises: a second function determining module for determining a second pseudo-random calculator function according to the number of the address buses; the second initial determination module is used for determining a second address initial value of the address bus and a second initial value of the data bus; the initial writing module is used for writing a second initial value of the data bus in a storage unit corresponding to the second address initial value; the pseudo-random calculation module is used for starting iterative calculation from a second initial value of the data bus by utilizing the second pseudo-random calculator function to obtain a pseudo-random calculation result of each iterative calculation; the address covering module is used for writing the same pseudo-random calculation result in a storage unit corresponding to the pseudo-random calculation result until the pseudo-random calculation result covers all the addresses of the SDRAM; reading a pseudo-random value cached by an SDRAM (synchronous dynamic random access memory) from a storage unit corresponding to the initial value of the second address, performing iterative computation from the second initial value by using a second pseudo-random calculator function, obtaining the address of the next storage unit and the corresponding pseudo-random value cached by the SDRAM, and performing iterative computation from the second initial value by using the second pseudo-random calculator; and comparing the pseudo-random value cached by the SDRAM with the pseudo-random value obtained by the calculation of the corresponding second pseudo-random calculator until the pseudo-random value which is not equal to the pseudo-random value cached by the SDRAM exists in the pseudo-random values obtained by the calculation of the second pseudo-random calculator or the addresses of the SDRAM are completely read.
The second function determining module is used for determining a second target N value of the pseudo-random counter function according to the number of the address buses; determining a second target feedback coefficient corresponding to the second target N value according to the corresponding relation between the N value and the feedback coefficient; and determining a second pseudo-random calculator function according to the second target feedback coefficient.
The read-write reliability detection apparatus shown in fig. 4 corresponds to the read-write reliability detection method shown in fig. 1, and details thereof are not repeated here.
Referring to fig. 6, fig. 6 shows a schematic structural block diagram of an FPGA applied in the read-write reliability detection method provided in the embodiment of the present application, where the FPGA includes an SDRAM controller IP 410, a multi-port SDRAM operation management unit 420, an SDRAM self-test unit 430, and multiple service data read-write request units.
The main functions of the individual units are described below:
SDRAM controller IP 410: the SDRAM controller IP 410 can be a MIG controller of Xilinx company, and can complete initialization, data reading and writing, automatic refreshing and other operations on SDRAMs such as DDR2/3/4 and the like.
Multi-port SDRAM operation management unit 420: n operating ports for reading and writing SDRAM are provided, wherein (N-1) ports from port 0 to port N-2 are respectively connected with a service data reading and writing unit 0 to a service data reading and writing unit (N-1), and a multi-port SDRAM operation management unit 420 is also connected with an SDRAM controller IP 410.
Each service data read-write unit in the plurality of service data read-write units is connected with a port corresponding to the multi-port SDRAM operation management unit 420, and is used for sending or reading service data to or from the SDRAM during normal operation.
SDRAM self-check unit 430: which is used to test the SDRAM by data interaction with one port (i.e., port N-1) of the multi-port SDRAM operation management unit 420 during device initialization.
The read-write reliability detection method provided by the embodiment of the application can be executed by the SDRAM self-check unit 430, and the read-write reliability of the SDRAM can be tested by the SDRAM self-check unit 430, so that the address of the storage unit of the SDRAM and the read-write data to be stored in the storage unit are continuously read and written with high strength through the pseudo-random function. Due to the property of the pseudo random number, the address or the read-write data can be greatly changed, so that the low bit and the high bit of the data line can be more comprehensively detected.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for detecting read-write reliability is characterized by comprising the following steps:
determining a first pseudo-random calculator function according to the data bus width of the synchronous dynamic random access memory SDRAM;
determining a first address initial value of an address bus and a first initial value of a data bus;
performing iterative computation for N times from a first initial value of the data bus by using the first pseudorandom calculator function to obtain N computation results;
and determining the read-write reliability of the SDRAM by using N +1 pseudo-random values and a first address initial value, wherein the N pseudo-random values and the first address initial value are composed of the N calculation results and the first initial value of the data bus.
2. The method according to claim 1, wherein the determining the read/write reliability of the SDRAM using N +1 pseudo random values consisting of the N calculation results and a first initial value of the data bus and a first initial value of an address comprises:
sequentially writing N +1 pseudo random values including the N calculation results and a first initial value of the data bus into N +1 storage units with continuous addresses from a storage unit corresponding to the first initial value of the address;
reading N +1 pseudo-random values cached by an SDRAM (synchronous dynamic random access memory) from the storage units with the continuous N +1 addresses, and simultaneously, starting iteration from a first initial value of the data bus by using a first pseudo-random calculator to obtain N +1 pseudo-random values;
and determining the read-write reliability of the SDRAM according to whether the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are equal to the N +1 pseudo-random values cached by the SDRAM correspondingly.
3. The method according to claim 2, wherein the determining the read/write reliability of the SDRAM according to whether the N +1 pseudo random values calculated by the first pseudo random calculator and the N +1 SDRAM-buffered pseudo random values are equal to each other comprises:
if the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are correspondingly equal to the N +1 pseudo-random values cached by the SDRAM, calculating the initial value of the first address by using the function of the first pseudo-random calculator to obtain an address calculation result;
taking the address calculation result as a new first address initial value, taking the (N + 1) th pseudo random value in the (N + 1) th pseudo random values as a new first initial value of the data bus, and executing the following steps: performing iterative computation for N times from a first initial value of the data bus by using the first pseudorandom calculator function to obtain N computation results; sequentially writing N +1 pseudo random values including the N calculation results and a first initial value of the data bus into N +1 storage units with continuous addresses from a storage unit corresponding to the first initial value of the address; until the first pseudo-random calculator calculates the N +1 pseudo-random value that obtains has the pseudo-random value unequal to said N +1 pseudo-random value that SDRAM buffers, or the above-mentioned method runs and exceeds the predetermined duration.
4. The method according to claim 1, wherein said determining a first pseudo-random calculator function based on a data bus width of a synchronous dynamic random access memory SDRAM comprises:
determining a first target N value of a pseudo random counter function according to the data bus width of the SDRAM;
determining a first target feedback coefficient corresponding to the first target N value according to the corresponding relation between the N value and the feedback coefficient;
determining a first pseudorandom calculator function according to the first target feedback coefficient.
5. The method of claim 1, further comprising:
determining a second pseudorandom calculator function according to the number of address buses;
determining a second address initial value of the address bus and a second initial value of a data bus;
writing a second initial value of the data bus in a storage unit corresponding to the second address initial value;
starting iterative computation from a second initial value of the data bus by using the second pseudorandom calculator function to obtain a pseudorandom computation result of each iterative computation;
writing the same pseudo-random calculation result in a storage unit corresponding to the pseudo-random calculation result until the pseudo-random calculation result covers all addresses of the SDRAM;
reading a pseudo-random value cached by an SDRAM (synchronous dynamic random access memory) from a storage unit corresponding to the initial value of the second address, performing iterative computation from the second initial value by using a second pseudo-random calculator function, obtaining the address of the next storage unit and the corresponding pseudo-random value cached by the SDRAM, and performing iterative computation from the second initial value by using the second pseudo-random calculator;
and comparing the pseudo-random value cached by the SDRAM with the pseudo-random value obtained by the calculation of the corresponding second pseudo-random calculator until the pseudo-random value which is not equal to the pseudo-random value cached by the SDRAM exists in the pseudo-random values obtained by the calculation of the second pseudo-random calculator or the addresses of the SDRAM are completely read.
6. The method of claim 5, wherein determining the second pseudo-random calculator function based on the number of address buses comprises:
determining a second target N value of the pseudo-random counter function according to the number of the address buses;
determining a second target feedback coefficient corresponding to the second target N value according to the corresponding relation between the N value and the feedback coefficient;
and determining a second pseudo-random calculator function according to the second target feedback coefficient.
7. A device for detecting reliability of reading and writing, the device comprising:
the first function determining module is used for determining a first pseudo random calculator function according to the data bus width of the synchronous dynamic random access memory SDRAM;
the first initial determination module is used for determining a first address initial value of an address bus and a first initial value of a data bus;
the function calculation module is used for starting iterative calculation for N times from a first initial value of the data bus by using the first pseudorandom calculator function to obtain N calculation results;
and the reliability determining module is used for determining the read-write reliability of the SDRAM by using the N +1 pseudo-random values and the first address initial value, wherein the N pseudo-random values are composed of the N calculation results and the first initial value of the data bus.
8. The apparatus of claim 7, wherein the reliability determination module is configured to:
sequentially writing N +1 pseudo random values including the N calculation results and a first initial value of the data bus into N +1 storage units with continuous addresses from a storage unit corresponding to the first initial value of the address;
reading N +1 pseudo-random values cached by SDRAM from the storage units with the continuous N +1 addresses, and obtaining N +1 pseudo-random values by iteration starting from a first initial value of the data bus by using the first pseudo-random calculator;
and determining the read-write reliability of the SDRAM according to whether the N +1 pseudo-random values obtained by the calculation of the first pseudo-random calculator are equal to the N +1 pseudo-random values cached by the SDRAM correspondingly.
9. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is operating, the processor executing the machine-readable instructions to perform the method of any one of claims 1-6 when executed.
10. A readable storage medium, having stored thereon a computer program which, when executed by a processor, performs the method of any one of claims 1-6.
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