CN115774635A

CN115774635A - Read-write test method and device, computer storage medium and electronic equipment

Info

Publication number: CN115774635A
Application number: CN202111050167.5A
Authority: CN
Inventors: 黄国维
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2023-03-10
Also published as: WO2023035413A1

Abstract

The embodiment of the application provides a read-write test method and device, a computer storage medium and electronic equipment, wherein the method comprises the following steps: receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, performing read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; acquiring a target write value of a target storage object in a memory module in the latest write operation; and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result. Therefore, the physical storage address of the storage object can be directly determined through the data instruction sent by the memory controller, the physical storage address is further used for carrying out subsequent testing, the address mapping relation does not need to be reestablished aiming at different system control platforms, and the flexibility and the universality of the read-write testing can be improved.

Description

Read-write test method and device, computer storage medium and electronic equipment

Technical Field

The present application relates to the field of memory testing technologies, and in particular, to a read/write testing method and apparatus, a computer storage medium, and an electronic device.

Background

In servers, personal computers, and various consumer electronic products, dynamic Random Access Memories (DRAMs) are generally used as Memory components to provide temporary data storage functions. According to the data storage principle of the DRAM, the DRAM needs to be continuously refreshed during use, so that data is kept stable.

At present, the DRAM is generally read-write tested by a test application (such as Stress APP tool), so as to ensure the stability and reliability of the memory. Because the Stress APP tool needs to perform read-write test by using the logical storage address, if one or more data errors occur, the Stress APP tool needs to determine the physical storage address where the error occurs through analysis. In other words, for different system platforms, the Stress APP tool needs to redesign the address mapping relationship and the corresponding test parameters, and the development cycle is long; in addition, the Stress APP tool may also have compatibility issues, resulting in poor flexibility and versatility of the Stress APP tool.

Disclosure of Invention

The application provides a read-write test method and device, a computer storage medium and an electronic device, which can directly utilize a physical storage address to carry out read-write test on a memory module, and improve the flexibility and compatibility of the read-write test.

The technical scheme of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a read-write testing method, which is applied to a read-write testing apparatus, and the method includes:

receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction;

when the data instruction indicates read operation, performing read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address;

acquiring a target write value of a target storage object in a memory module in the latest write operation;

and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result.

In some embodiments, the method further comprises: when the data instruction indicates write operation, determining a target write value according to the data instruction; and performing write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

In some embodiments, a read-write test device includes a first storage unit and a second storage unit; the method further comprises the following steps: after determining the target write value, correspondingly storing the physical storage address and the target write value into a first storage unit; after the target read value is determined, the physical memory address and the target read value are stored in the second memory location.

In some embodiments, the comparing the target read value with the target write value and determining a test result of the target memory object in the memory module according to the comparison result includes:

acquiring a target write-in value corresponding to a physical storage address from a first storage unit; acquiring a target reading value corresponding to the physical storage address from the second storage unit; determining that a target storage object in the memory module is in a normal state under the condition that the target write-in value is the same as the target read-out value; alternatively, when the target write value and the target read value are different, it is determined that the target memory object in the memory module is in an abnormal state.

In some embodiments, the method further comprises: when the target write-in value is the same as the target read-out value or the target write-in value is different from the target read-out value and the system recovery instruction is not received, returning the target read-out value to the memory controller; or, when the target write value and the target read value are different and a system recovery command is received, performing data recovery processing on the target storage object in the memory module.

In some embodiments, the performing data recovery processing on the target storage object in the memory module includes:

rewriting a target storage object in the memory module to write a target write value into the target storage object in the memory module; re-reading a target storage object in the memory module, and receiving a corrected read value sent by the memory module; if the corrected read value is the same as the target write value, the corrected read value is returned to the memory controller.

In some embodiments, the method further comprises: counting the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit; after controlling the memory controller to be in an idle state, determining a storage object to be processed according to the read-write times of each storage object in the memory module; and performing read-write test processing on the storage objects to be processed based on a preset test mode so that the read-write times of each storage object in the memory module meet the preset requirement.

In some embodiments, after performing read-write test processing on the storage object to be processed based on the preset test mode, the method further includes:

acquiring an effective write value corresponding to a storage object to be processed from a first storage unit; the effective write-in value is a target write-in value of the to-be-processed storage object in the last write operation before the memory controller is in an idle state; writing the storage object to be processed to write the effective write value into the storage object to be processed; and controlling the memory controller to exit the idle state.

In a second aspect, an embodiment of the present application provides a read/write testing apparatus, including:

the analysis control unit is used for receiving the data instruction sent by the memory controller and determining a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, the target storage object in the memory module is read, and a target read value sent by the memory module is received; the target storage object in the memory module is determined according to the physical storage address;

the comparison unit is used for acquiring a target write-in value of a target storage object in the memory module in the latest write operation; and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result.

In some embodiments, the parsing control unit is further configured to determine a target write value according to the data instruction when the data instruction indicates a write operation; and performing write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

In some embodiments, the read-write test device further comprises a first storage unit and a second storage unit; the first storage unit is used for storing a write-in value of each storage object in the memory module; the second storage unit is used for storing the read value of each storage object in the memory module;

correspondingly, the analysis control unit is also used for correspondingly storing the physical storage address and the target write-in value into the first storage unit after the target write-in value is determined; after the target read value is determined, the physical memory address and the target read value are stored in the second memory location.

In some embodiments, the comparing unit is specifically configured to obtain a target write value corresponding to the physical memory address from the first storage unit; acquiring a target reading value corresponding to the physical storage address from the second storage unit; determining that a target storage object in the memory module is in a normal state under the condition that the target write-in value is the same as the target read-out value; or, in the case that the target write value and the target read value are different, it is determined that the target storage object in the memory module is in an abnormal state.

In some embodiments, the read-write test device further comprises an output unit; the output unit is used for generating alarm information under the condition that the target written value and the target read value are different, and displaying the alarm information on a preset display screen; the warning information is used for indicating that the target storage object in the memory module is in an abnormal state.

In some embodiments, the parsing control unit is further configured to return the target read value to the memory controller when the target write value and the target read value are the same or when the target write value and the target read value are different and a system recovery instruction is not received; or, when the target write value and the target read value are different and a system recovery instruction is received, performing data recovery processing on the target storage object in the memory module.

In some embodiments, the parsing control unit is further configured to perform a rewrite operation on the target storage object in the memory module, so as to write the target write value into the target storage object in the memory module; re-reading a target storage object in the memory module, and receiving a corrected read value sent by the memory module; if the corrected read value is the same as the target write value, the corrected read value is returned to the memory controller.

In some embodiments, the read-write test device further comprises a test mode unit; a test mode unit for providing a preset test mode; the comparison unit is also used for counting the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit; the analysis control unit is also used for determining the storage objects to be processed according to the read-write times of each storage object in the memory module after controlling the memory controller to be in an idle state; and performing read-write test processing on the storage objects to be processed based on a preset test mode so that the read-write times of each storage object in the memory module meet the preset requirement.

In some embodiments, the parsing control unit is further configured to, after performing read-write test processing on the storage object to be processed based on the preset test mode, obtain an effective write value corresponding to the storage object to be processed from the first storage unit; writing the storage object to be processed to write the effective write value into the storage object to be processed; and controlling the memory controller to exit the idle state; the valid write value is a target write value of the to-be-processed storage object in the last write operation before the memory controller is in the idle state.

In some embodiments, the read-write test device further comprises a data selector; the analysis control unit is also used for sending a first selection instruction to the data selector; or sending a second selection instruction to the data selector;

the data selector is used for controlling the analysis control unit and the memory controller to be in a communication state after receiving the first selection instruction; or after receiving the second selection instruction, controlling the analysis control unit to be in a communication state with the memory module.

In a third aspect, the present application provides a computer storage medium storing a computer program, which when executed by a processor implements the steps of the method according to the first aspect.

In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the read-write testing apparatus according to the second aspect.

The embodiment of the application provides a read-write test method and device, a computer storage medium and electronic equipment, which are used for receiving a data instruction sent by a memory controller and determining a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, performing read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address; acquiring a target write-in value of a target storage object in a memory module in the latest write operation; and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result. Therefore, the physical storage address of the storage object can be directly determined through the data instruction sent by the memory controller, so that the physical storage address is used for carrying out subsequent testing, and the address mapping relation does not need to be reestablished aiming at different system control platforms; in addition, the read-write test method only relates to the operation of the memory controller and the memory module, does not need to interact with an external operating system, does not have the compatibility problem, and can improve the flexibility and the universality of the read-write test.

Drawings

Fig. 1 is a schematic flow chart of a read-write testing method according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of another read-write testing method according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a read/write testing apparatus according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another read/write testing apparatus according to an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of another read/write testing apparatus provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of Module1 provided in the embodiments of the present application;

FIG. 7 is a schematic structural diagram of Module2 according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant application and are not limiting of the application. It should be noted that, for the convenience of description, only the parts related to the related applications are shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

It should be noted that the terms "first \ second \ third" are used merely to distinguish similar objects and do not denote a particular ordering, and it should be understood that "first \ second \ third" may be interchanged under appropriate circumstances in order to enable the embodiments of the present application described herein to be implemented in other sequences than those illustrated or described herein.

The following description will be made of the english vocabulary and its abbreviations referred to in the examples of the present application.

Dynamic Random Access Memory, DRAM: a dynamic random access memory;

memory Down: welding the memory in the mainboard;

dual Inline Memory Module, DIMM: a dual in-line memory module;

RDIMM: a two-wire memory module with a register;

LRDIMM: a low load dual inline memory module;

a UDIMM unbuffered dual channel memory module;

SODIMM: a small dual in-line memory module;

memory: memory, memory module;

cell: the memory unit in the memory module is also called a memory object;

temporarily Store: a temporary storage space;

memory Controller: a memory controller;

DIMM Slot: a DIMM socket;

rank: a logic block in the memory;

and (2) Bank: a physical block in the memory;

row Address: a row address;

column Address: a column address;

Pre-Charge: pre-charging;

refresh: refreshing;

central Processing Unit, CPU: a central processing unit;

JEDEC: semiconductor industry standards as specified by the solid state technology association;

raw Card: a memory card type;

serial Presence Detect, SPD: sequence presence detection information;

field Programmable Gate Array, FPGA: a field programmable gate array;

application Specific Integrated Circuit, ASIC: an application specific integrated circuit;

idle: an idle state.

DRAM is an important electronic device for the semiconductor industry, and can provide a memory function for a terminal device. In particular, since the DRAM is a dynamic random access memory device, storing charges of data allows the data to be held for only a certain time. At normal temperature, the retention time of one memory Cell Capacitor (Cell Capacitor) is generally about 64 milliseconds. Therefore, in order to ensure that data is stored normally, periodic refreshing (periodic Refresh) is required to be performed on the memory cells to keep the data stable.

During normal operation of the terminal, the CPU usually stores both the operating data and temporary data during operation in a memory, i.e. the memory can be understood as a very large temporary storage (temporary storage). If the data is not completely stored in the memory, an error occurs when the operating system reads the data, which may cause the entire system to be down or the system to be restarted.

For the terminal equipment, corresponding instructions are sent to the DRAM through the memory controller so as to realize the writing and reading of data. Specifically, in the working process of the DARM, a Memory Controller (Memory Controller) sequentially sends the following parameters to a Memory DRAM: (1) selecting a Memory Controller; (2) selecting a DIMM Slot; (3) selecting a Rank address; (4) selecting Bank Address and Row Address; (5) selecting Column Address to perform read/write operation; (6) Other operation contents, such as Pre-Charge/Refresh operation.

In general, servers, notebook computers, and various consumer electronic products involve DRAM devices for storing large amounts of data that are temporarily involved during CPU operation. Therefore, data errors stored in the DRAM may cause catastrophic failures to the electronic product, such as a system down, a system restart.

Therefore, the read/write test (also called Stress test) of the memory is an important test of the memory, and is used for testing the reliability and stability of the DRAM. Currently, general Stress APP tools include MemtestX86, primer95, memtester, stress APP, and the like. However, in practical tests, the software is found to involve problems of system compatibility, software upgrading and the like; moreover, the addresses of the same test position which are reported by different Stress APPs are possibly different, and the Stress APP is likely to have errors when the addresses are analyzed; moreover, if a plurality of errors occur in the memory, the system may be down or restarted, and then the Stress APP is hung, which brings great trouble to system analysis; in addition, all the Stress APPs are developed under a specific operating system, so that the compatibility of the operating system and the compatibility of a CPU are considered during development, and the development period is quite long; finally, none of the Stress APPs shown above has a way to control the Stress pressure applied to each address in the memory (i.e., the number of times each address is read and written may be different), resulting in an inaccurate final test result.

Based on this, the embodiment of the present application provides a read-write test method, and the basic idea is: receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, performing read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address; acquiring a target write-in value of a target storage object in a memory module in the latest write operation; and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result. Therefore, the physical storage address corresponding to the data instruction can be directly determined through the data instruction sent by the memory controller, and then the physical storage address is used for carrying out subsequent testing without reestablishing an address mapping relation aiming at different system control platforms; secondly, the read-write test method only relates to the operation of the internal memory controller and the internal memory module, does not need to interact with an external system control platform, does not have the compatibility problem, and can improve the flexibility and the universality of the read-write test; in addition, the read-write test method also has an error correction mechanism, so that the found read-write errors can be corrected in time, and system breakdown is avoided; finally, the read-write test method also has a pressure equalization mechanism, so that the read-write pressures of different storage units can be ensured to be the same, and the test accuracy is improved.

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, referring to fig. 1, a flowchart of a read-write testing method provided in the embodiment of the present application is shown. As shown in fig. 1, the method may include:

s101: and receiving a data instruction sent by a memory controller, and determining a physical storage address corresponding to the data instruction.

It should be noted that the read-write test method provided in the embodiment of the present application is applied to a read-write test device or a terminal device integrated with the read-write test device. The terminal device may be various types of devices having a memory module in the implementation process. For example, the terminal device may be a device such as a smart phone, a tablet computer, a palmtop computer, a television, a projector, a Personal computer, a Personal Digital Assistant (PDA), a wearable device, and the like, which is not limited herein.

The read/write test apparatus is a hardware module connected between a Memory Controller (Memory Controller) and a Memory module (e.g., DIMM). Specifically, the memory module includes a plurality of memory objects (or called memory cells, cells), and the memory controller may send different instructions to the memory module to implement read/write operations on different memory objects.

It should be noted that, in the actual process of writing or reading the memory module by the memory controller, the memory module needs to be operated by sending the actual physical address of the target storage object. On this basis, because the read-write test device is arranged between the memory controller and the memory module in a hardware mode, the read-write test device can receive and analyze the data instruction sent by the memory controller and determine the corresponding physical storage address according to the data instruction.

For example, when the memory module is composed of a plurality of DIMMs, the data command issued by the memory controller at least includes the following addresses: a Memory Channel Address (Memory Channel), a dual in-line Memory module slot Address (DIMM Position), a Memory Rank Address (Rank Selection), a Memory Bank Address (Bank Selection), a Row Address (Row Address Selection), and a Column Address (Column Address Selection), which constitute the physical Memory Address of the data command.

In other words, in the related art, generally, the Stress APP needs to implement a read-write test on the memory module, and the Stress APP needs to test the memory module according to the logical storage address, and when an error is found, the physical storage address can be determined by further address resolution. The embodiment of the application develops a read-write testing device from the hardware perspective, the read-write testing device is arranged between a memory controller and a memory module, a data instruction issued by the memory controller can be directly analyzed through the read-write testing device to obtain a physical storage address, and then the physical storage address is used for carrying out subsequent testing instead of a logical storage address. Therefore, even in different operating systems, the address mapping relation does not need to be reestablished, and therefore universality and flexibility of the stress test are improved.

S102: when the data instruction indicates read operation, performing read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address.

It should be noted that there are a plurality of different memory objects (cells) in the memory module, and these memory objects are distinguished by physical memory addresses. Therefore, when the data command indicates a read operation, the read-write test device can control the memory module to perform the read operation according to the physical storage address, so as to obtain a target read value of the target storage object.

S103: and acquiring a target write value of a target storage object in the memory module in the last write operation.

It should be noted that the read/write test apparatus has a separate storage space for storing the write value of each storage object in the memory module in the last write operation.

S104: and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result.

It should be noted that, on the premise that the target storage object is in a normal state, the target read value and the target write value should be the same. Thus, from the actual comparison of the target read value and the target write value, the test result of the target memory object may be determined.

In some embodiments, the method may further comprise:

when the data instruction indicates write operation, determining a target write value according to the data instruction;

and performing write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

It should be noted that, when the data instruction indicates a write operation, the read/write test apparatus needs to parse the data instruction to determine a target write value, and then write the target write value into the target storage object.

It should be noted that the read-write test apparatus may be provided with a separate storage space for storing data required in the test process. Thus, in some embodiments, the read-write test device includes a first memory cell and a second memory cell. Accordingly, the method may further comprise:

after determining the target write value, correspondingly storing the physical storage address and the target write value into a first storage unit;

after the target read value is determined, the physical memory address and the target read value are stored in the second memory location.

It should be noted that the first storage unit is used to store physical storage addresses and values to be written (e.g., target write values) in all write operations; the second storage unit is used to store the physical memory address and the actual read value (e.g., the target read value) in all read operations.

In this way, by comparing the write value and the read value at the same physical memory address in the first memory cell and the second memory cell, the read-write test result of the memory object can be obtained. Therefore, in some embodiments, the comparing the target read value with the target write value and determining the test result of the target storage object in the memory module according to the comparison result may include:

acquiring a target write-in value corresponding to a physical storage address from a first storage unit;

acquiring a target reading value corresponding to the physical storage address from the second storage unit;

determining that a target storage object in the memory module is in a normal state under the condition that the target write-in value is the same as the target read-out value; or, in the case that the target write value and the target read value are different, it is determined that the target storage object in the memory module is in an abnormal state.

It should be understood that the same storage object may actually have repeated read and write processes, that is, there may be multiple write values at one physical storage address in the first storage unit, and multiple read values at one physical storage address in the second storage unit. In the embodiment of the present application, the target write value refers to a write value in a last write operation to the physical memory address before a read operation corresponding to the target read value occurs.

In particular, in some embodiments, the read-write test apparatus may include only the first storage unit, and may compare the read target read value with the target write value stored in the first storage unit immediately after the read operation is performed on the target storage object, so as to obtain the test result this time.

It should be noted that, for the terminal device, in order to save the calculation amount, the read-write test apparatus is only activated when the read-write test is required. That is to say, when the system is in a normal working state, the memory controller is directly connected with the memory module, and at this time, the memory controller directly issues the data instruction to the memory module to perform corresponding read/write operation; when the system is in a read-write test state, the memory controller is connected with the memory module through the read-write test device, at this time, the memory controller needs to send a data instruction to the read-write test device, the read-write test device performs corresponding read/write operation on the memory module, and meanwhile, the read-write test device can also execute other test operation.

The read/write test procedure is described in detail below.

Firstly, the memory controller issues a data instruction, and supposing that the data instruction instructs to write "1" into the storage object of the address a, at this time, the read-write test device correspondingly stores the address a and the write value "1" into the first storage unit, and controls the memory module to write "1" into the storage unit corresponding to the address a.

Then, when the memory controller issues a data instruction again and the data instruction instructs to read the address 1, the read-write testing device controls the memory module to read the storage object of the address a, and if the read value "1" is obtained, the read-write testing device stores the address a and the read value "1" in the second storage unit.

Finally, the read value and the write value are compared, and if the write value "1" is the same as the read value "1", it indicates that the storage object indicated by the address a is in a normal state. On the other hand, if the read value is "0", it indicates that the memory object indicated by the address a is in an abnormal state.

When the target storage object is in an abnormal state, an alarm mechanism can be set to remind workers of paying attention. Thus, in some embodiments, where the target write value and the target read value are different, the method may further comprise:

generating alarm information; the warning information is used for indicating that a target storage object in the memory module is in an abnormal state; and displaying the alarm information on a preset display screen.

For example, the preset display screen may be divided into a left part and a right part, where one part is used to display the written values of different storage objects in the memory module in real time, and the other part is used to display the read values of different storage objects in the memory module in real time. If the target writing value and the target reading value of a certain storage object are different, the staff can be reminded through pop-up window information, highlight marking, red frame warning and other modes.

In some embodiments, the method further comprises:

when the target write-in value is the same as the target read-out value or the target write-in value is different from the target read-out value and the system recovery instruction is not received, returning the target read-out value to the memory controller; or, when the target write value and the target read value are different and a system recovery command is received, performing data recovery processing on the target storage object in the memory module.

It should be noted that after obtaining the target read value, the read/write testing apparatus needs to return the target read value to the memory controller, and then the command closed loop of the memory controller can be completed, otherwise the memory controller may generate an error. However, if a data error occurs in a large number of/an important memory object, returning the read value directly may cause a system crash. Therefore, the embodiment of the application also provides a system recovery mechanism. Here, the system recovery mechanism may be enabled or disabled according to user requirements.

Specifically, if the target write value and the target read value are the same, that is, the target storage object is in a normal state, the target read value may be directly returned to the memory controller. And if the target write value is different from the target read value and a system recovery instruction sent by a user is not received, returning the target read value to the memory controller. And if the target write-in value is different from the target read-out value and a system recovery command sent by a user is received, performing data recovery processing on the target storage object.

It should be further noted that the data recovery process specifically refers to an attempt to perform writing and reading processes to the target storage object again. Therefore, in some embodiments, the performing data recovery processing on the target storage object in the memory module may include:

rewriting a target storage object in the memory module to write a target write value into the target storage object in the memory module;

re-reading a target storage object in the memory module, and receiving a corrected read value sent by the memory module;

if the corrected read value is the same as the target write value, the corrected read value is returned to the memory controller.

It should be noted that, if the corrected read value and the target write value are different, the above steps may be tried to be repeated; or returning an error corrected read value to the memory controller, or reminding a worker to process.

Therefore, through a system recovery mechanism, the conditions of excessive data errors and system downtime can be avoided, and the stability of the system is improved.

It should be further noted that, in the related art, the read/write times of each memory cell in the memory module may be different, which causes different read/write pressures of different memory cells and thus affects the test result. To address this issue, in some embodiments, as shown in fig. 2, the method may further include:

s201: and counting the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit.

S202: and after controlling the memory controller to be in an idle state, determining the storage object to be processed according to the read-write times of each storage object in the memory module.

S203: and performing read-write test processing on the storage objects to be processed based on a preset test mode so that the read-write times of each storage object in the memory module meet the preset requirement.

It should be noted that, according to the foregoing, if a write operation is performed on a certain storage object once, a write value is added to a physical storage address of the storage object in the first storage unit; if a certain memory object is read once, a read value is added to the physical memory address of the memory object in the second memory cell. Therefore, the read-write times of different storage objects can be counted according to the data quantity stored in the first storage unit and the second storage unit respectively. And then, determining the storage object with less read-write times as a storage object to be processed, and performing read-write test on the storage object to be processed independently so as to enable the read-write times of different storage objects to be approximately the same.

It should be noted that the number of read/write times may indicate the number of read times, the number of write times, the sum of the number of read times and the number of write times, or the number of read times and the number of write times may also include both the number of read times and the number of write times. Accordingly, the preset test mode may indicate a specific process of how to determine the read-write times according to the read-write times of the storage object to be processed. The parameters of the preset test mode may be defined by the user.

In addition, a threshold value (for example, 5 times or 10 times) may be set according to an actual requirement, and if the difference between the read-write times of two storage objects in the memory module does not exceed the threshold value, it is determined that the read-write times of different storage objects meet a preset requirement.

It should be noted that, since the pressure equalization mechanism is provided by the read/write test apparatus 30, it is not related to the memory controller. Therefore, after determining the storage objects to be processed with a smaller number of read/write times, the memory controller 31 needs to be controlled to enter the idle state, and the control right of the memory module 32 is handed over to the read/write testing apparatus 30, so that the read/write testing apparatus 30 performs read/write testing on the storage objects to be processed by using the preset testing mode.

In some embodiments, after performing the read-write test processing on the storage object to be processed based on the preset test mode, the method may further include:

acquiring an effective write value corresponding to a storage object to be processed from a first storage unit; the effective write value is a target write value of a to-be-processed storage object in the last write operation before the memory controller is in an idle state;

writing the storage object to be processed to write the effective write value into the storage object to be processed;

and controlling the memory controller to exit the idle state.

It should be noted that, for the memory controller, the written value in the memory object to be processed needs to be kept unchanged, otherwise the system crashes. Therefore, before controlling the memory controller to exit the idle state, the previous valid write value needs to be rewritten to the pending memory object.

Therefore, by providing a pressure equalization mechanism, the situation that the read-write pressures of different storage objects are different can be avoided, and the reliability of the test result is improved.

In the related art, the memory bank is generally subjected to a Stress test by a Stress test tool (Stress APP), thereby testing the stability and reliability of the memory. On one hand, however, since the Stress APP tool needs to perform read-write test by using a logic storage address, if one or more data input/output channel signals (generally referred to as DQ signals) are wrong in the test process, the Stress APP needs to perform resolution according to an address mapping resolution relationship to know the address of the wrong data, and if a system platform is replaced, the Stress APP needs to re-develop software to re-establish a new address mapping resolution relationship to correctly position the error; on the other hand, the Stress APP also needs to consider the problems of compatibility of an operating system and the like, so that a Stress APP tool needs to be continuously updated, and the universality is not very friendly; on the other hand, when there are too many errors, the error correction capability of the system platform may be exceeded, and at this time, the system has crashed, and then the Stress APP crashes, that is, the Stress APP cannot cope with the situation of more errors; on the other hand, the existing Stress APP has no good method for counting and ensuring the pressure result of each address in the memory.

In order to solve the problem existing when the Memory module runs the read-write test, the embodiment of the application develops a module which can test the pressure of different storage objects in the Memory and can ensure that the pressure of each storage object is equal from the hardware perspective, and avoids the problem that the test cannot be carried out due to the overlong development period and verification period of Stress APP.

Specifically, since the system operates the Memory by sending the actual physical Memory address during the actual write or read operation of the Memory, the specific command sending sequence is generally as follows: memory Channel, rank Selection & DIMM Position, bank Selection, row Address Selection and Column Address Selection.

Therefore, a read-write test device capable of analyzing the Memory command can be established between the Memory Controller and the Memory, and the written data and the read data are respectively recorded according to the recording modes of Memory Channel, rank Selection (DIMM Selection), bank Selection, row Address Selection and Column Address Selection, namely, the written value in the write operation is stored by using the first storage unit, and the read value in the read operation is stored by using the second storage unit. Then, the written value and the read value are compared, and the compared result is displayed and output through a display screen.

Thus, when error data occurs, the specific physical address of the error data can be directly displayed, and additional address analysis is not needed. In addition, according to the first storage unit and the second storage unit, stress statistics can be carried out on different addresses, and a single Stress test is carried out on addresses with smaller Stress by using a self-contained preset test mode, so that the Stress of each address is ensured to be the same or similar. Therefore, the address with small Stress can be independently stressed by counting the Stress of each address in the memory, so that the Stress of each address in the memory is ensured to be equal or equal as much as possible. Besides, the phenomenon that the system is down or restarted due to too much error data can be avoided through a data recovery mechanism.

The embodiment of the application provides a read-write test method, which comprises the steps of determining a physical storage address corresponding to a data instruction by receiving the data instruction sent by a memory controller; when the data instruction indicates read operation, performing read operation on a target storage object in the memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address; acquiring a target write value of a target storage object in a memory module in the latest write operation; and comparing the target reading value with the target writing value, and determining the test result of the target storage object in the memory module according to the comparison result. Therefore, the physical storage address corresponding to the data instruction can be directly determined through the data instruction sent by the memory controller, and then the physical storage address is used for carrying out subsequent testing without reestablishing an address mapping relation aiming at different system control platforms; secondly, the read-write test method only relates to the operation of the internal memory controller and the internal memory module, does not need to interact with an external system control platform, does not have the compatibility problem, and can improve the flexibility and the universality of the read-write test; in addition, the read-write test method also has an error correction mechanism, so that the found read-write errors can be corrected in time, and system breakdown is avoided; finally, the read-write test method also has a pressure equalization mechanism, so that the read-write pressures of different storage units can be ensured to be the same, and the test accuracy is improved.

In another embodiment of the present application, refer to fig. 3, which shows a schematic structural diagram of a read/write testing apparatus 30 provided in an embodiment of the present application. As shown in fig. 3, the read/write test apparatus 30 may include:

the analysis control unit 301 is configured to receive a data instruction sent by a memory controller, and determine a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, the target storage object in the memory module is read, and a target read value sent by the memory module is received; the target storage object in the memory module is determined according to the physical storage address;

a comparing unit 302, configured to obtain a target write value of a target storage object in the memory module in the last write operation; and comparing the target read value with the target write value, and determining the test result of the target storage object in the memory module according to the comparison result.

It should be noted that, in the embodiment of the present application, a read/write testing apparatus 30 is provided from a hardware perspective, and is disposed between a memory controller and a memory module, where the read/write testing apparatus 30 is capable of analyzing a data instruction sent by the memory controller, so as to determine a physical storage address corresponding to the data instruction, and further perform a subsequent test by using the physical storage address, instead of performing the subsequent test by using a logical storage address, without establishing an address mapping relationship, so as to improve the universality.

Please refer to fig. 4, which illustrates a schematic structural diagram of another read/write testing apparatus 30 according to an embodiment of the present application. As shown in fig. 4, the apparatus for testing read/write operations 30 is connected between a memory controller 31 and a memory module 32. The memory module 32 includes a plurality of storage objects, and the memory controller 31 may send different instructions to the memory module 32 through the read/write test device 30, so as to perform read/write operations on different storage objects.

The read-write test apparatus 30 includes an analysis control unit 301 and a comparison unit 302. Specifically, after the read/write testing apparatus 30 receives the data instruction sent by the memory controller 31, the parsing control unit 301 parses the data instruction to determine a physical storage address, and controls the memory module 32 to perform corresponding read/write operation according to the data instruction. And the comparing unit 302 is used for comparing the target write value and the target read value of the target memory object, thereby determining the test result.

Here, the physical memory address includes at least one of: channel address, dual inline memory module slot address, memory Rank address, memory Bank address, row address, and column address.

It should be further noted that, in some embodiments, the parsing control unit 301 is further configured to determine a target write value according to the data instruction when the data instruction indicates a write operation; and performing write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

That is to say, after the read/write testing apparatus 30 receives the data instruction sent by the memory controller 31, if the data instruction indicates a write operation, the parsing control unit 301 performs a write operation on the target storage object in the memory module 32 according to the physical storage address, and stores the physical storage address and the target write value; if the data instruction indicates a read operation, the parsing control unit 301 performs a read operation on a target storage object in the memory module 32 according to the physical storage address to obtain a target read value returned by the memory module 32, and stores the physical storage address and the target read value; then, the comparison unit 302 compares the target write value and the target read value to determine a test result of the target memory object.

The read-write test device 30 may be provided with a separate memory space for storing physical memory addresses/write values or physical memory addresses/read values.

As shown in fig. 4, the read/write test device 30 may further include a first storage unit 303 and a second storage unit 304. Correspondingly, the parsing control unit 301 is further configured to, after determining the target write value, store the physical storage address and the target write value into the first storage unit 303 correspondingly; after the target read value is determined, the physical memory address and the target read value are stored into second memory cell 304 correspondingly.

It should be noted that the first storage unit 303 is used to store a write value of each storage object in the memory module 32; the second storage unit 304 is used for storing the read value of each storage object in the memory module 32.

In some embodiments, the comparing unit 302 is specifically configured to obtain a target write value corresponding to the physical storage address from the first storage unit 303; acquiring a target read value corresponding to the physical storage address from the second storage unit 304; and determining that the target storage object in the memory module 32 is in a normal state under the condition that the target write-in value and the target read-out value are the same; alternatively, in the case where the target write value and the target read value are different, it is determined that the target memory object in the memory module 32 is in an abnormal state.

In some embodiments, as shown in FIG. 4, the read/write test device 30 further includes an output unit 305;

and an output unit 305, configured to generate alarm information and display the alarm information on a preset display screen when the target write value and the target read value are different.

It should be noted that the alarm information is used to indicate that the target storage object in the memory module 32 is in an abnormal state, so as to remind a worker to perform processing. In addition, the preset display screen can be divided into a left part and a right part, and the written values and the read values corresponding to different storage objects can be displayed in real time.

In order to complete the logic loop of the memory controller, if the memory controller 31 issues a data command indicating a read operation, the read/write test apparatus 30 needs to recover the read value to the memory controller 31. However, if more data errors occur, the memory controller 31 may crash. To address this issue, in some implementations, the read-write test device 30 also has a system recovery mechanism. Specifically, the parsing control unit 301 is further configured to return the target read value to the memory controller 31 when the target write value and the target read value are the same, or when the target write value and the target read value are different and a system recovery instruction is not received; alternatively, when the target write value and the target read value are different and a system restore command is received, the data restore process is performed on the target storage object in the memory module 32.

It should be noted that the system recovery mechanism may be enabled or disabled according to the user requirement, so that the data recovery processing is performed on the target storage object only after a data error occurs (the target write value is different from the target read value) and a system recovery instruction is received; otherwise, the obtained target read value is returned to the memory controller 31. Of course, in other embodiments, the system recovery mechanism may be designed to be always enabled, that is, to perform data recovery processing on the target storage object whenever a data error occurs.

In addition, a data recovery key may be provided in the read/write testing apparatus 30, and if the user presses the data recovery key, it is determined that a system recovery instruction is received.

It should be further noted that the essence of the data recovery process is to perform the rewriting and re-reading processes on the target storage object. Therefore, in some embodiments, the parsing control unit 301 is further configured to perform a rewrite operation on the target storage object in the memory module 32, so as to write the target write value into the target storage object in the memory module 32; rereading a target storage object in the memory module 32, and receiving a corrected read value sent by the memory module 32; when the corrected read value is the same as the target write value, the corrected read value is returned to the memory controller 31.

In the related art, the read-write times of different storage objects in the test process may be different, thereby affecting the accuracy of the test result. Therefore, in some embodiments, the read-write test device 30 may further include a test mode unit 306. In particular, the amount of the solvent to be used,

a test mode unit 306 for providing a preset test mode;

the comparing unit 302 is further configured to count the read-write times of each storage object in the memory module 32 according to the first storage unit and the second storage unit;

the analysis control unit 301 is further configured to determine a storage object to be processed according to the read-write frequency of each storage object in the memory module 32 after controlling the memory controller 31 to be in the idle state; the storage objects to be processed are subjected to read-write test processing based on a preset test mode, so that the read-write frequency of each storage object in the memory module 32 meets a preset requirement.

It should be noted that, according to the data in the first storage unit 303 and the data in the second storage unit 304, the read-write times of different storage objects can be counted, and then, the read-write test processing is performed on the storage object with a smaller read-write time, so that the read-write times of different storage objects are controlled to meet the preset requirement.

It should be noted that the preset test mode specifies a specific method for the read/write test processing, such as what default write value is, the sequence of write operation and read operation, and the preset test mode may be modified accordingly according to the requirement of the user.

In addition, the read/write testing apparatus 30 further includes a power management unit 307 for supplying power to the read/write testing apparatus. Thus, the read/write test apparatus 30 has a separate power scheme, so that the control function can still be performed after the memory controller 31 enters the idle state.

It should be noted that, after the read/write times of different storage objects satisfy the preset requirement, and after the read/write times of each storage object satisfy the preset requirement, the read/write testing apparatus 30 needs to return the control right to the memory controller 31, that is, the memory controller 31 exits the idle state. However, the values in the pending memory objects must be consistent before and after the memory controller 31 enters the idle state, otherwise the memory controller 31 may crash.

Therefore, in some embodiments, the parsing control unit 31 is further configured to, after performing read-write test processing on the storage object to be processed based on the preset test mode, obtain a valid write value corresponding to the storage object to be processed from the first storage unit 303; writing the storage object to be processed to write the effective write value into the storage object to be processed; and controls the memory controller 31 to exit the idle state.

It should be noted that the valid write value refers to a target write value of the to-be-processed memory object in the last write operation before the memory controller 31 is in the idle state.

It should be further noted that, in order to facilitate the working staff to grasp the test situation, the output unit 305 is further configured to display the read-write times of each storage object in the memory module 32 on the preset display screen 33.

As can be seen from the above, for the read/write testing apparatus 30, first, a data path is formed with the memory controller 31, so as to receive and analyze the data command sent by the memory controller 31; then, a data path is formed with the memory module 32, so as to perform read/write operations on the target storage object; finally, a data path is formed with the memory controller 32 to return the result of the operation of the data instruction.

In other words, the read/write testing apparatus 30 needs to sequentially form a data path with the memory controller 31 and the memory module 32. To achieve this, in some embodiments, the read-write test device 30 further includes a data selector;

the analysis control unit 301 is further configured to send a first selection instruction to the data selector; or sending a second selection instruction to the data selector;

It should be noted that, in addition to setting the data selector, a software-controlled method may be adopted to achieve the above-mentioned object.

In the related art, according to the data storage principle of the DRAM, the time for which the DRAM keeps data stable is limited, and thus the DRAM needs to be continuously refreshed to keep the data stable. In other words, if the Data Retention time (Retention) of the entire memory Cell (Cell) in the DRAM is insufficient, or the Retention of a portion of the Cell is insufficient, important Data may be lost, for example, the Data Bits (Data Bits) change from 1 to 0, or from 0 to 1. When data bits are unexpectedly changed, it may cause the entire system to be down or the system to be restarted. Therefore, the read-write test of DRAM is an important performance test, but the conventional read-write test apparatus has various problems.

Therefore, the embodiment of the present invention provides a read/write testing apparatus 30, and the read/write testing apparatus 30 can be integrated on a Motherboard (Motherboard) of a terminal device or used as an independent module. In particular, the literacy test device 30 has a completely independent operating system, while it has an independent power supply system. There are four main functions:

(1) By the read-write test device 30, the pressure of each address in the memory module can be judged in the Stress pressure test process, and the pressure of each address (according to Channel/DIMM/Rank/Row address) is displayed through the display screen. Meanwhile, when the error data is tested, the information of the error address is displayed through the display screen.

(2) And selecting a specific test mode to carry out individual stress test on the address with low stress according to the stress size counted by the Channel/DIMM/Rank/Row address, thereby ensuring that the stress size of each address is equal or approximately equal.

(3) The method can improve and replace the function of the Stress APP, saves the development period of the Stress APP due to the upgrading and compatibility of the platform, and can position the specific information of the error data in a hardware mode.

(4) When the system finds one or more error data, the data can be restored and set, and the stability of the operating system is ensured.

The embodiment of the application provides a read-write testing device, which comprises an analysis control unit, a storage unit and a reading unit, wherein the analysis control unit is used for receiving a data instruction sent by a memory controller and determining a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, performing read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; wherein, the target storage object in the memory module is determined according to the physical storage address; the comparison unit is used for acquiring a target write value of a target storage object in the memory module in the latest write operation; and comparing the target read value with the target write value, and determining a test result of a target storage object in the memory module according to a comparison result. Therefore, the physical storage address corresponding to the data instruction can be directly determined through the data instruction sent by the memory controller, and then the physical storage address is used for carrying out subsequent testing without reestablishing an address mapping relation aiming at different system control platforms; in addition, the read-write test method only relates to the operation of the internal memory controller and the internal memory module, does not need to interact with an external system control platform, does not have the compatibility problem, and can improve the flexibility and the universality of the read-write test.

In another embodiment, refer to fig. 5, which shows a schematic structural diagram of another read/write test apparatus 30 provided in this embodiment of the present application. The application scenario includes a Memory Controller (Memory Controller) 31, a read/write test device 30, and at least one Memory module (DIMM or Memory Down) 32.

As shown in fig. 5, the read/write testing apparatus 30 is disposed between the memory controller 31 and the memory module 32. The read/write testing apparatus 30 is a completely independent control system, and includes a Controller, a power supply and power management unit (corresponding to the power management unit 307 in fig. 4), a data recovery key, a display screen, a storage unit, a test mode unit (or called a Pattern unit), a calculation/comparison unit, and an output unit (not shown). The principle of the controller may be FPGA or custom CPU, and the storage unit may include a write data storage unit 1 (equivalent to the first storage unit 303 in fig. 4) and a read data storage unit 2 (equivalent to the second storage unit 304 in fig. 4).

It should be understood that the structure of the read/write test apparatus 30 in fig. 5 refers to some module physical structures, not to a strict functional structure, for example, a part of the controller in fig. 5 that plays a role of parsing control corresponds to the parsing control unit 301 in fig. 4, the controller and the calculation/comparison unit in fig. 5 correspond to the comparison unit 302 in fig. 4, and the controller in fig. 5 and some devices (not shown in fig. 5) that can perform data output correspond to the output unit 305 in fig. 4.

In practical applications, the memory controller 31 may have a plurality of data channels (channels), and for each Channel, a read/write test apparatus 30 may be separately provided for locating an address where a data error occurs in the memory module 32 and for error correction. In order to improve the efficiency of the device usage, a controller (e.g., controller 0, controller N, etc. in fig. 5) may be provided separately for each Channel, while other portions are shared.

Embodiments of the present application relate generally to various types of electronic products, and are applied to memories (e.g., DRAM, LR/RDIMM, UDIMM, SODIMM, etc.) on servers, computers, and consumer platforms, where data integrity in the Memory affects the overall system operation, and is particularly important in server applications. The read-write testing device 30 provided in the embodiment of the present application can quickly and accurately locate a data address where an error occurs when the Memory (e.g., normal read-write or pressure test) has an error, so as to effectively improve the stability and reliability of the Memory, and help to ensure the smooth performance of the function test and the pressure test; moreover, the read-write testing device 30 can also count the actual Stress of the storage object in each Rank/Bank in the Memory, and perform a single Stress test on the address with low Stress according to a specific Pattern according to the counted Stress, so as to ensure that the Stress of each address is equal or similar; in addition, when a plurality of data errors occur, the error correction can be carried out on the erroneous data, and the stable operation of an operating system is also greatly facilitated.

The read/write testing apparatus 30 can be implemented by two different hardware structures, which are respectively called Module1 and Module2. In other words, in the following embodiments, the Module1 and the Module2 are substantially read/write test devices 30, and can perform the same function, and the main differences are: (1) The hardware of the Module1 is more complex and higher in cost than that of the Module2, and certain time is consumed, but the software is slightly simple; (2) Module2 is software complex, but hardware cost is low. In particular, the controllers in Module1 and Module2 have a function of parsing data commands (or called Command commands) of the memory controller 31.

Please refer to fig. 6, which illustrates a schematic structural diagram of Module1 provided in the embodiment of the present application. As shown in fig. 6, the Module1 includes a controller, a data recovery button, a High Speed data selector (High Speed Mux), a power supply and power management unit, a first storage unit (or called as a write data storage unit 1), a second storage unit (or called as a read data storage unit 2), and a test mode unit. Meanwhile, the controller is integrated with a comparison unit, an output unit and an analysis control unit. The analysis control unit is mainly used for analyzing the Command Command and controlling the high-speed data selector. In particular, the controller may be implemented by, for example, an FPGA or an ASIC.

In fig. 6, the data path between the high speed data selector and the memory controller 31 is referred to as a, the data path between the high speed data selector and the controller is referred to as B, and the data path between the high speed data selector and the memory module is referred to as C.

As shown in fig. 6, when writing data, the high speed data selector first controls the AB to be turned on, so that the memory controller 31 issues data commands (generally including CMD signal/CA signal/CTL signal/DQ signal/DQs signal) to the controller; the high-speed data selector controls the BC to be turned on again, so that the controller issues a Control signal (generally, a Control Signals signal) to the memory module 32 to Control the memory module 32 to write data; on the contrary, when reading data, the high-speed data selector firstly controls the CB to be turned on, so that the controller controls the memory module 32 to read data; the high speed data selector then controls AB to conduct so that the controller returns the read result to the memory controller 31.

That is, the Module1 has independent power supply and power management units, and can switch the data paths of the memory controller 31, the read/write test apparatus 30 and the memory Module 32 through the high speed data selector. In this way, the read/write testing apparatus 30 can collect data commands and other information between the memory controller 31 and the memory module 32, and store the information. Then, by comparing the written and read information before and after, the comparison result is displayed on the display screen by means of the data comparison output unit, for example, the address of the error data can be displayed. In addition, the read/write test apparatus 30 counts the number of times of reading and writing (i.e., the magnitude of stress) for each address, thereby performing a more targeted individual test.

In particular, each DIMM has a Raw Card definition in JEDEC, on which Raw Card type information can be obtained by reading SPD information, and if the test result indicates that error data occurs, the position of the particle on the DIMM where the data error occurs (i.e. the memory object where the data error occurs) can be located according to the Raw Card information and the address where the data error occurs, and the error position information can be displayed through a display screen.

For Module1, the specific control logic is divided into the following parts:

(1) The controller in Module1 can parse the Command between the memory controller 31 and the memory Module 32, and separately record the read Command and the write Command according to the Command of the memory controller 31. When storing data, it is necessary to form a physical memory address in accordance with information such as Channel, DIMM Slot, rank, banks, row, column, and the like, and to record the data.

(2) In a write operation, after the controller in Module1 resolves the write command, the controller records all write data and stores the write data into the first memory unit according to Channel, DIMM Slot, rank, banks, row, column. At the same time, the controller switches the high-speed data selector from the original BA path to the BC path, and the controller writes all the write values (data recorded in sequence) into the designated storage object in the memory module 32.

(3) In the reading operation, after the controller in the Module1 analyzes a reading command, the high-speed data selector is switched to the BC Channel, the controller reads data, and the read data is stored in the second storage unit according to Channel, DIMM Slot, rank, banks, row and Column; the read data is then compared to the data in the first memory cell (compare the same Channel, DIMM Slot, rank, banks, row, column). If no error occurs, the controller switches the high-speed data selector from the CB path to the BA path, and if one or more data are found to be abnormal, error information can be displayed through the display screen, and corresponding information such as Channel, DIMM Slot, rank, banks, row, column and the like can be displayed at the same time.

Particularly, if the read operation is directed to a plurality of memory objects, when the read operation is continued according to the read command, if the subsequently read data and the previously written data have new errors after being compared, the error information is also displayed through the display screen, and the corresponding information such as Channel, DIMM Slot, rank, banks, row, column, and the like is displayed at the same time.

(3.1) an error recovery mechanism (or called as a system recovery mechanism), wherein if the controller finds that one or more data errors exist, the user can press a data recovery key (equivalent to sending a system recovery instruction), the controller can rewrite the data into the memory once and read the data again once, if the read data is consistent with the written data, the controller switches the high-speed data selector from the original BC path to the BA path or from the original BC path to the CA path according to actual needs, and at this time, the memory controller 31 is directly connected with the memory module 32.

And (3.2) when a data error occurs, if a data recovery key is not pressed, the controller automatically switches the high-speed data selector from the BC path to the BA path.

(4) For the worker, the particles on the DIMM are found by the recorded information of Channel, DIMM Slot, rank, banks, row, column, etc. and the Row Card information (obtainable by SPD information) of the corresponding DIMM, and the DIMM with the error and the position of the particles can be displayed by the display screen.

(5) And counting the data in the first storage unit and the second storage unit by using the comparison unit, determining the read-write times of each address according to the result of the comparison unit, and obtaining the statistical result of the Stress sizes of different addresses. And carrying out specific Stress test on the address with low Stress according to the statistical result. The method comprises the following steps: firstly, making the memory controller 31 enter Idle mode, at this time, the memory controller 31 does not operate the DRAM, and since the Module1 has separate power supply and power management units, the Module1 can work normally and can operate the memory Module 32; then, according to the previous Stress test results of different addresses in the memory, the Module1 performs an independent pressure test on the addresses with small Stress according to a preset test mode, wherein the preset test mode can be provided by a test mode unit, so that the Stress pressure of each address can be ensured to be equal or approximately equal; finally, when the stress test module exits the operation on the DRAM, the stress test module writes the data previously written into the first memory cell into the DRAM.

Thus, the Module1 can realize all functions of the read/write test apparatus 30.

Please refer to fig. 7, which illustrates a schematic structural diagram of Module2 according to an embodiment of the present application. As shown in fig. 7, the Module2 includes a controller, a data recovery key, a power supply and power management unit, a display screen, a first storage unit, a second storage unit, and a test mode unit; meanwhile, a comparison unit, an output unit and an analysis control unit are integrated in the controller. The analysis control unit is mainly used for analyzing the Command Command and playing a control role.

For Module2, the specific control logic is divided into the following parts:

(1) When the mainboard runs, the Module2 is used as the function of analyzing data information between the Memory controller 31 and the Memory Module 32 and analyzing Memory control commands; according to the Command information of the memory controller 31, separately recording the write-in data and the read-out data, and recording according to the information of Channel, DIMM Slot, rank, banks, row, column and the like;

(2) Writing operation, after the controller in the Module2 analyzes a write command, the controller records all write data and stores the write data into a first storage unit according to Channel, DIMM Slot, rank, banks, row and Column;

(3) And in the reading operation, after the controller in the Module2 analyzes the reading command, the controller reads data, stores the read data into the second storage unit according to the Channel, the DIMM Slot, rank, bank, row and Column, compares the read data with the data in the first storage unit (aiming at the same Channel, the DIMM Slot, rank, bank, row and Column), and displays error information and simultaneously displays corresponding information of the Channel, the DIMM Slot, rank, bank, row and Column through the display screen if one or more data are different.

Then, in the subsequent reading operation, if new error information is found after the data is compared, the error information is displayed through the display screen, and the corresponding information of Channel, DIMM Slot, rank, banks, row, column and the like is displayed at the same time.

(4) An error recovery mechanism, wherein when the controller finds that there is one or more data, the controller can immediately press a data recovery key on the Module2, and the controller can rewrite the memory once (at this time, the memory controller 31 does not operate the memory Module 32), and then read the memory data;

(5) The particles on the DIMM are found through the recorded information of Channel, DIMM Slot, rank, banks, row, column and the like and the Row Card information of the corresponding DIMM, and the DIMM with the error and the position of the particles can be displayed through a display.

(6) And counting the reading and writing times of each address according to the result of the comparison unit to obtain the statistical result of the Stress sizes of different addresses. And according to the statistical result, carrying out a specific Pattern pressure test on the address with low Stress. The method comprises the following steps: firstly, the memory controller 31 enters the Idle mode, at this time, the memory controller 31 does not operate the DRAM, and since the power supply and power management units of the Module2 are independent, the Module2 can normally operate and operate the memory Module 32, and according to the previous Stress test results for different addresses in the memory, the Module2 performs an independent pressure test on addresses with low Stress according to the preset test mode. The preset test mode can be one or more of Pattern units in the pressure test Module, so that the Stress pressure of each address can be ensured to be equal or approximately equal, and when Module2 exits the operation on the DRAM, module2 writes the data previously written into the first storage unit into the DRAM.

In FIG. 7, DQ/DQS are signals of data-related content and CMD/CA/CTL are signals related to command, address and control-related content, respectively.

Thus, the Module2 can also realize the whole functions of the read/write test device 30.

In summary, the embodiments of the present application are directed to protecting a mechanism module and similar functions that can test the Memory Stress and ensure the equal pressure. Specifically, the embodiment of the present application provides a read/write test apparatus 30, which has the following functions: on one hand, the read-write testing device 30 can detect whether error data occurs when the Stress test is performed on the memory module, and can visually see the physical address information of the error data through the display screen; on the other hand, the read/write testing device 30 may count the Stress of each address, and select a specific testing mode for the address with low Stress to perform a Stress test, so as to ensure that the Stress of each address is the same or similar; on the other hand, when the Memory is subjected to the pressure test, the read-write test device 30 records the address according to a hardware physical method, without considering the compatibility of the Stress APP system, and when a data error occurs, the problem that the error address cannot be located or the location is inaccurate does not exist; on the other hand, when the memory module 32 sends a data error, the read-write testing device 30 can correct the data with the error, so as to prevent the system from going down or restarting.

The embodiment of the application provides a read-write test method, and the specific implementation method of the embodiment is elaborated in detail through the embodiment, so that it can be seen that a physical storage address corresponding to a data instruction can be directly determined through the data instruction sent by a memory controller, and further, the physical storage address is utilized for carrying out subsequent tests, and address mapping relations do not need to be reestablished for different system control platforms; secondly, the read-write test method only relates to the operation of the internal memory controller and the internal memory module, does not need to interact with an external system control platform, does not have the compatibility problem, and can improve the flexibility and the universality of the read-write test; in addition, the read-write test method also has an error correction mechanism, so that the found read-write errors can be corrected in time, and system breakdown is avoided; finally, the read-write test method also has a pressure equalization mechanism, so that the read-write pressures of different storage units can be ensured to be the same, and the test accuracy is improved.

In a further embodiment of the present application, based on the composition schematic diagram of the read/write testing apparatus 30, referring to fig. 8, a composition structural schematic diagram of an electronic device 40 provided in an embodiment of the present application is shown. As shown in fig. 8, the electronic device 40 at least includes the read-write test apparatus 30 in any of the previous embodiments.

For the electronic device 40, because it includes the read-write test device 30, the data instruction sent by the memory controller can directly determine the physical storage address corresponding to the data instruction, and further perform subsequent tests by using the physical storage address without re-establishing an address mapping relationship for different system control platforms; secondly, the read-write test method only relates to the operation of the internal memory controller and the internal memory module, does not need to interact with an external system control platform, does not have the compatibility problem, and can improve the flexibility and the universality of the read-write test; in addition, the read-write test method also has an error correction mechanism, so that the found read-write errors can be corrected in time, and system breakdown is avoided; finally, the read-write test method also has a pressure equalization mechanism, so that the read-write pressures of different storage units can be ensured to be the same, and the test accuracy is improved.

It is to be understood that, in the foregoing embodiments, a "unit" may be a part of a circuit, a part of a processor, a part of a program or software, or the like, and may also be a module, and may also be non-modular. Moreover, each component in the embodiment may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware or a form of a software functional module.

Based on the understanding that the technical solution of the present embodiment essentially or partly contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) or a Processor (Processor) to execute all or part of the steps of the method of the present embodiment. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Accordingly, the present embodiment provides a computer storage medium storing a computer program which, when executed by a plurality of processors, implements the steps of the method of any one of the preceding embodiments.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application.

It should be noted that, in the present application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.

Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.

The features disclosed in the several method or apparatus embodiments provided herein may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A read-write test method is applied to a read-write test device, and the method comprises the following steps:

when the data instruction indicates read operation, performing read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address;

acquiring a target write-in value of a target storage object in the memory module in the latest write operation;

2. The read-write test method according to claim 1, characterized in that the method further comprises:

when the data instruction indicates write operation, determining the target write value according to the data instruction;

3. The read-write test method according to claim 2, wherein the read-write test apparatus includes a first storage unit and a second storage unit; the method further comprises the following steps:

after determining the target write value, storing the physical storage address and the target write value in the first storage unit correspondingly;

after determining the target read value, storing the physical storage address and the target read value into the second storage unit correspondingly.

4. The method of claim 3, wherein the comparing the target read value with the target write value and determining a test result of the target storage object in the memory module according to the comparison result comprises:

acquiring a target write-in value corresponding to the physical storage address from the first storage unit;

determining that a target storage object in the memory module is in a normal state under the condition that the target write-in value is the same as the target read-out value; alternatively, the first and second electrodes may be,

and under the condition that the target write-in value and the target read-out value are different, determining that a target storage object in the memory module is in an abnormal state.

5. The read-write test method of claim 4, further comprising:

returning the target read value to the memory controller when the target write value and the target read value are the same or when the target write value and the target read value are different and a system recovery instruction is not received; alternatively, the first and second liquid crystal display panels may be,

and under the condition that the target write-in value is different from the target read-out value and the system recovery instruction is received, performing data recovery processing on a target storage object in the memory module.

6. The read-write test method according to claim 5, wherein the performing data recovery processing on the target storage object in the memory module includes:

rewriting a target storage object in the memory module to write the target write value into the target storage object in the memory module;

re-reading the target storage object in the memory module, and receiving a corrected read value sent by the memory module;

and returning the corrected read value to the memory controller when the corrected read value is the same as the target write value.

7. The read-write test method of claim 3, further comprising:

counting the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit;

after controlling the memory controller to be in an idle state, determining a storage object to be processed according to the read-write times of each storage object in the memory module;

and performing read-write test processing on the storage object to be processed based on a preset test mode so that the read-write times of each storage object in the memory module meet preset requirements.

8. The read-write test method according to claim 7, wherein after the read-write test processing is performed on the storage object to be processed based on the preset test mode, the method further comprises:

obtaining an effective write value corresponding to the storage object to be processed from the first storage unit; the effective write value refers to a target write value of the to-be-processed storage object in the last write operation before the memory controller is in an idle state;

and controlling the memory controller to exit the idle state.

9. A read-write test apparatus, comprising:

the analysis control unit is used for receiving a data instruction sent by the memory controller and determining a physical storage address corresponding to the data instruction; when the data instruction indicates read operation, performing read operation on a target storage object in a memory module, and receiving a target read value sent by the memory module; the target storage object in the memory module is determined according to the physical storage address;

the comparison unit is used for acquiring a target write value of a target storage object in the memory module in the latest write operation; and comparing the target reading value with the target writing value, and determining a test result of a target storage object in the memory module according to a comparison result.

10. The read-write test device according to claim 9,

the analysis control unit is further configured to determine the target write value according to the data instruction when the data instruction indicates a write operation; and performing write operation on the target storage object in the memory module to write the target write value into the target storage object in the memory module.

11. The read-write test device according to claim 10, characterized in that the read-write test device further includes a first storage unit and a second storage unit; wherein the content of the first and second substances,

the first storage unit is used for storing the write-in value of each storage object in the memory module;

the second storage unit is used for storing the read value of each storage object in the memory module;

correspondingly, the parsing control unit is further configured to, after determining the target write value, store the physical storage address and the target write value into the first storage unit correspondingly; after determining the target read value, storing the physical storage address and the target read value into the second storage unit correspondingly.

12. The read-write test device according to claim 11,

the comparing unit is specifically configured to obtain a target write value corresponding to the physical memory address from the first storage unit; acquiring a target reading value corresponding to the physical storage address from the second storage unit; determining that a target storage object in the memory module is in a normal state under the condition that the target write-in value is the same as the target read-out value; or, determining that a target storage object in the memory module is in an abnormal state when the target write value and the target read value are different.

13. The read-write test device according to claim 12, characterized in that the read-write test device further comprises an output unit;

the output unit is used for generating alarm information under the condition that the target writing value is different from the target reading value, and displaying the alarm information on a preset display screen;

the alarm information is used for indicating that a target storage object in the memory module is in an abnormal state.

14. The read-write test device according to claim 12,

the analysis control unit is further configured to return the target read value to the memory controller when the target write value and the target read value are the same or when the target write value and the target read value are different and a system recovery instruction is not received; or, when the target write value and the target read value are different and the system recovery instruction is received, performing data recovery processing on the target storage object in the memory module.

15. The read-write test device according to claim 14,

the analysis control unit is further configured to perform a rewrite operation on a target storage object in the memory module, so as to write the target write value into the target storage object in the memory module; re-reading the target storage object in the memory module, and receiving a corrected read value sent by the memory module; and returning the corrected read value to the memory controller when the corrected read value is the same as the target write value.

16. The read-write test device according to claim 15, characterized in that the read-write test device further comprises a test mode unit;

the test mode unit is used for providing a preset test mode;

the comparison unit is further configured to count the read-write times of each storage object in the memory module according to the first storage unit and the second storage unit;

the analysis control unit is also used for determining a storage object to be processed according to the read-write times of each storage object in the memory module after controlling the memory controller to be in an idle state; and performing read-write test processing on the storage object to be processed based on the preset test mode so that the read-write times of each storage object in the memory module meet preset requirements.

17. The apparatus according to claim 16, wherein the parsing control unit is further configured to obtain a valid write value corresponding to the storage object to be processed from the first storage unit after performing the read-write test processing on the storage object to be processed based on a preset test mode; writing the storage object to be processed to write the effective write value into the storage object to be processed; and controlling the memory controller to exit the idle state;

the valid write value refers to a target write value of the to-be-processed storage object in the last write operation before the memory controller is in the idle state.

18. The device of claim 9, where the device further comprises a data selector;

the analysis control unit is also used for sending a first selection instruction to the data selector; or sending a second selection instruction to the data selector;

the data selector is used for controlling the analysis control unit and the memory controller to be in a communication state after receiving the first selection instruction; or after receiving the second selection instruction, controlling the analysis control unit and the memory module to be in a communication state.

19. A computer storage medium, characterized in that it stores a computer program which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 8.

20. An electronic device characterized in that it comprises a read-write test apparatus according to any of claims 9 to 18.