CN117766007A - Built-in self-test method and device - Google Patents
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- G11C—STATIC STORES
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Abstract
The present disclosure provides a built-in self-test method and apparatus, comprising: the method comprises the steps of obtaining a first initial address of a storage area of data to be written, shielding at least one bit address of the first initial address to activate a plurality of storage areas, writing test data into the corresponding storage areas according to the first compressed writing address, obtaining a second initial address of the storage area of the data to be read, shielding at least one bit address of the second initial address to activate a plurality of storage areas, reading the test data corresponding to the plurality of storage areas according to the first compressed reading address, compressing the test data in a reading process, calculating ideal reading data according to the test data and a preset compression processing rule, and comparing the reading data of the memory with the ideal reading data to obtain a test result. By the arrangement, the testing efficiency is improved.
Description
Technical Field
The present disclosure relates to, but is not limited to, a built-in self-test method and apparatus.
Background
Semiconductor memory is the most important component of electronic devices, and memory plays a critical role in both performance and stability of electronic devices. Therefore, reliability of the memory used in these electronic devices must be ensured, and testing for the memory is necessary.
However, in the existing test method, different addresses need to be accessed, and read-write operations need to be executed on the different addresses, which results in longer test time and lower test efficiency.
Disclosure of Invention
The present disclosure provides a built-in self-test method, a memory including a plurality of memory regions, the method comprising:
acquiring a first initial address of a storage area of data to be written;
shielding at least one address of the first initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed write addresses;
writing test data into the corresponding storage area according to the first compressed write address;
acquiring a second initial address of the storage area of the data to be read;
shielding at least one address of the second initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed read addresses;
reading the test data corresponding to the storage areas according to the first compressed read address, and compressing the test data in the reading process so that the bit number of the compressed data read out by the memory is equal to the bit number of the uncompressed data read out by one storage area;
and calculating ideal read-out data according to the test data and a preset compression processing rule, and comparing the read-out data of the memory with the ideal read-out data to obtain a test result.
In some embodiments, masking at least one bit address of the first initial address specifically includes:
and acquiring a compressed write instruction, and forcing at least one address in the first initial address and an inversion signal thereof to be the same specific value based on the compressed write instruction so as to activate a plurality of corresponding storage areas.
In some embodiments, masking at least one bit address of the second initial address specifically includes:
and acquiring a compressed read instruction, and forcing at least one address in the second initial address and an inversion signal thereof to be the same specific value based on the compressed read instruction so as to activate a plurality of corresponding storage areas.
In some embodiments, each storage area includes a plurality of storage arrays;
writing test data into the corresponding storage area according to the first compressed write address, specifically comprising:
and in the storage area corresponding to each first compressed writing address, starting a current word line according to the current row address, starting a current column selection line in a storage array on the current word line so as to write test data into a target value storage unit, and updating a next column selection line until the test data are written into all storage units on the current word line.
In some embodiments, each storage area includes a plurality of storage arrays;
reading test data corresponding to the storage areas according to the first compressed read address, specifically including:
and in the storage area corresponding to each first compressed read address, starting a current word line according to the current row address, starting a current column selection line in the storage array on the current word line so as to read out test data from a target value storage unit, and updating a next column selection line until the test data are read out from all storage units on the current word line.
In some embodiments, the number of memory regions that are activated simultaneously when writing data is greater than the number of memory regions that are activated simultaneously when reading data.
In some embodiments, before calculating ideal read data from the test data and the rule of the compression process, comparing the read data of the memory with the ideal read data to obtain a test result, the method further comprises:
acquiring a third initial address of a storage area of data to be written;
shielding at least one address of the third initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as second compressed write addresses;
writing test data into the corresponding storage area according to the second compressed write address;
acquiring a fourth initial address of the storage area of the data to be read;
shielding at least one address of the fourth initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as second compressed read addresses;
and reading the test data corresponding to the storage areas according to the second compressed read addresses, and compressing the test data in the reading process so that the number of bits of the compressed data read out by the memory is equal to the number of bits of the uncompressed data read out by one storage area.
Another embodiment of the present disclosure provides a built-in self-test device, a memory including a plurality of memory regions, the device comprising:
the writing module is used for acquiring a first initial address of a storage area of data to be written; shielding at least one address of the first initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed write addresses; writing test data into the corresponding storage area according to the first compressed write address;
the reading module is used for acquiring a second initial address of the storage area of the data to be read; shielding at least one address of the second initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed read addresses; reading the test data corresponding to the storage areas according to the first compressed read address, and compressing the test data in the reading process so that the bit number of the compressed data read out by the memory is equal to the bit number of the uncompressed data read out by one storage area;
and the output module is used for calculating ideal read-out data according to the test data and a preset compression processing rule, and comparing the read-out data of the memory with the ideal read-out data to obtain a test result.
In some embodiments, the writing module is configured to obtain a compressed writing instruction, and force at least one address of the first initial address and its inverse signal to the same specific value based on the compressed writing instruction, so as to activate the corresponding plurality of storage areas.
Another embodiment of the present disclosure provides a computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, are configured to implement the built-in self-test method involved in the above-described embodiments.
The built-in self-test method and the built-in self-test equipment provided by the disclosure mask at least one address of the first initial address to activate a plurality of storage areas, and write test data into the activated storage areas, so that data writing compression is realized, and data writing time is shortened. At least one address of the second initial address is shielded to activate a plurality of storage areas, test data is read from the activated storage areas, data reading compression is realized, data reading time is shortened, and the read test data is compressed to adapt to the data reading bit number of the memory, so that the structure of the existing memory is not required to be changed. By shortening the data writing time and the data reading time, the test time can be shortened, and the test efficiency can be improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a schematic diagram of a memory;
FIG. 2 is a schematic diagram of a memory area in the memory of FIG. 1;
FIG. 3 is a flow chart of a built-in self-test method according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of data writing in a built-in self-test method according to another embodiment of the present disclosure;
FIG. 5 is a flow chart of data read out in a built-in self-test method according to another embodiment of the present disclosure;
fig. 6 is a schematic diagram of a built-in self-test device according to another embodiment of the disclosure.
Specific embodiments of the present disclosure have been shown by way of the above drawings and will be described in more detail below. These drawings and the written description are not intended to limit the scope of the disclosed concepts in any way, but rather to illustrate the disclosed concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
As a test method, a built-in self test (Mbist) of the memory is automatically generated by built-in memory test logic, not by an external test machine.
When the Mbit controller receives the instruction for starting the test, the controller controls the test module of the memory to work, the test vector of the test module is automatically generated by the inside, and the output expected value of the memory is calculated. When the memory receives the test vector, the memory traverses all addresses in the memory by executing read-write operation at equal intervals, accesses all memory units, reads out the memory read-out data through the mode register, compares the memory read-out data with the output expected value of the memory, records the address of the error, and repairs the error.
Since Mbist needs to access different addresses and needs to perform read-write operations on different addresses, testing time is relatively long, and testing efficiency is reduced.
An embodiment of the present disclosure provides a built-in self-test method and apparatus, which implement shortening of test time and improving of test efficiency by simultaneously performing read-write on a plurality of storage areas and performing compression read-write on each storage area.
As shown in fig. 1, a memory 100 includes a plurality of memory regions 110, an Mbist controller 120, an address bus 150, an exclusive or gate 130, and DQ circuits 140. After the Mbist controller 120 receives the instruction to start the test, it controls a test module (not shown) to perform the test.
DQ circuits 140 are used to receive pattern registers (not shown) test data and write the test data into each memory region 110 via an address bus. Data read from each memory area 110 is output to the exclusive or gate 130 via the address bus 150, compressed by the exclusive or gate 130, and output to another mode register.
As shown in fig. 2, one memory region 110 includes a plurality of Memory Arrays (MATs) 230, the memory arrays of the same row share the same set of word lines 210, and the memory arrays of the same column share the same set of column select lines 220 and the same set of bit lines (not shown). One column select line 220 controls a unit number of bit lines to enable reading and writing data into the unit number of memory cells when one column select line is turned on.
In some embodiments, data is read from and written to 8 memory cells when one column select line is on.
As shown in fig. 3, an embodiment of the disclosure provides a built-in self-test method, which includes the following steps:
s101, acquiring a first initial address of a storage area to be written with data, and shielding at least one bit address of the first initial address to activate a plurality of storage areas.
The method comprises the steps of obtaining a first initial address of a storage area of data to be written by analyzing a test vector. For example: the address of the memory area has 4 bits, and the first initial address BA <3:0> is 0000 by parsing the test vector using the BA <3:0> tag.
In some embodiments, the first initial address includes a plurality of address bits, at least one address of the first initial address is masked, and the plurality of memory regions are activated based on the masked address.
In some embodiments, a compressed write instruction is obtained, and at least one bit address of the first initial address and its inverse are forced to the same specific value based on the compressed write instruction, so as to implement masking of the at least one bit address of the first initial address, so as to activate a plurality of corresponding memory areas.
In some embodiments, a compressed write instruction is fetched, and at least one high order address in the first initial address itself and its inverse are forced to the same particular value based on the compressed write instruction to activate a corresponding plurality of memory regions.
For example: the fourth bit address BA <3> of the first initial address BA <3:0> is set to a high level and the inversion signal BA <3>B of the fourth bit address is set to a high level. By decoding the forced first initial address, the 1 st storage area BA0 and the 9 th storage area BA8 are activated, so that two storage areas are activated simultaneously.
Also for example: the fourth bit address BA <3> and the third bit address BA <2> of the first initial address BA <3:0> are set to high level, and the inversion signal BA <3>B of the fourth bit address and the inversion signal BA <2>B of the third bit address are set to high level. By decoding the forced first initial address, the 1 st memory area BA0, the 5 th memory area BA4, the 9 th memory area BA8, and the 13 th memory area BA12 are activated, thereby realizing the simultaneous activation of four memory areas.
Also for example: the fourth bit address BA <3>, the third bit address BA <2> and the second bit address BA <1> of the first initial address BA <3:0> are set to high level, and the inversion signal BA <3>B, the inversion signal BA <2>B and the inversion signal BA <1>B of the third bit address are set to high level. By decoding the forced first initial address, the 1 st storage area BA0, the 3 rd storage area BA2, the 5 th storage area BA4, the 7 th storage area BA6, the 9 th storage area BA8, the 11 th storage area BA10, the 13 th storage area BA12, and the 15 th storage area BA14 are activated, thereby realizing the simultaneous activation of 8 storage areas.
S102, writing test data into the corresponding storage area according to the first compressed write address.
And writing test data into the corresponding storage areas according to the first compressed write address.
In some embodiments, the same test data is written into the corresponding memory area according to the first compressed write address.
S103, acquiring a second initial address of a storage area of data to be read, and shielding at least one address of the second initial address to activate a plurality of storage areas.
And obtaining a second initial address of the storage area of the data to be read by analyzing the test vector. For example: the address of the memory area has 4 bits, and the second initial address BA <3:0> is 0000 by parsing the test vector using the BA <3:0> tag.
In some embodiments, the second initial address includes a plurality of address bits, and the plurality of memory regions are activated based on the masked address by masking at least one address of the second initial address.
In some embodiments, a compressed read instruction is obtained, and at least one address of the second initial address and its inverse are forced to the same specific value based on the compressed read instruction, so as to implement masking of the at least one address of the second initial address, so as to activate a plurality of corresponding memory areas.
In some embodiments, a packed read instruction is obtained, and the at least one higher address in the second initial address and its inverse are forced to the same specific value based on the packed read instruction to activate the corresponding plurality of memory regions.
S104, reading the test data corresponding to the storage areas according to the first compressed read address, and compressing the test data in the reading process so that the bit number of the compressed data read out by the memory is equal to the bit number of the uncompressed data read out by one storage area.
And recording the addresses of the activated storage areas as first compressed read addresses, and reading the test data corresponding to the storage areas according to the first compressed read addresses.
In some embodiments, the number of bits of uncompressed data read from one storage area is M bits, and when data is read from only one storage area, the number of bits of memory read data is M bits.
If data are read out from N storage areas at the same time, when test data are compressed in the reading process, the number of read-out bits in each storage area is compressed to M/N bits by using a preset compression processing rule, so that the number of bits of compressed data read out from a memory is equal to the number of bits of uncompressed data read out from one storage area.
In some embodiments, the preset compression processing rule is that, for each memory array, one data is selected from a plurality of test data read out from the memory array on the current column selection line, after the selected data is grouped, the grouped data is subjected to exclusive-or processing, and then the next data is selected from a plurality of test data read out from each memory array until compression of all test data read out from the memory array on the current column selection line is completed.
For example: in one memory area, 16 memory arrays share one group of word lines, and data is read and written into 8 memory cells when one column selection line is opened. For each of the 16 memory arrays, the current column select line is turned on in the memory array to read out 8 test data, and 1 test data is selected from the 8 test data. Of the 16 memory arrays, 16 test data may be selected. The method comprises the steps of dividing 16 pieces of test data into two groups, dividing 8 pieces of test data of the first 8 storage arrays into one group, carrying out exclusive-or processing on the 8 pieces of test data to output one bit, dividing 8 pieces of test data of the last 8 storage arrays into the other group, carrying out exclusive-or processing on the 8 pieces of test data to output one bit, and completing compression of the 16 pieces of test data.
And selecting the next test data from the 8 test data read out from each memory array, processing according to the same rule until compression of the 16 multiplied by 8 test data is completed, and finally outputting the 16 test data.
In some embodiments, the number of memory regions that are activated simultaneously when writing data is greater than the number of memory regions that are activated simultaneously when reading data. The number of the storage areas which are activated simultaneously when the data are read out is reduced, the quality of the read-out data can be ensured, and the accuracy of the test is improved.
S105, calculating ideal read data according to the test data and a preset compression processing rule, and comparing the read data of the memory with the ideal read data to obtain a test result.
Wherein the test data is processed using a compression processing rule to output ideal read data. The read data from the memory is compared with the ideal read data, and if the read data from the memory is the same as the ideal read data, the memory function of the tested memory area is normal. If the read data from the memory and the ideal read data differ by at least one bit, the memory function of the memory region under test is characterized as faulty.
In the technical scheme, at least one address of the first initial address is shielded to activate a plurality of storage areas, test data is written into the activated storage areas, data writing compression is realized, and data writing time is shortened. At least one address of the second initial address is shielded to activate a plurality of storage areas, test data is read from the activated storage areas, data reading compression is realized, data reading time is shortened, and the read test data is compressed to adapt to the data reading bit number of the memory, so that the structure of the existing memory is not required to be changed. By shortening the data writing time and the data reading time, the test time can be shortened, and the test efficiency can be improved.
In some embodiments, writing test data into the corresponding storage area according to the first compressed write address specifically includes:
s201, in a storage area corresponding to each first compressed writing address, starting a current word line according to a current row address, starting a current column selection line in a storage array on the current word line to write test data into a target value storage unit, and updating a next column selection line until the test data are written into all storage units on the current word line.
And decoding the current row address in the storage area corresponding to each first compressed write address, and starting the current word line according to the decoding result. There are M memory arrays on each word line. And selecting the current column selection line from each of the M memory arrays to be opened so as to write test data into the target value memory cells on the current word line, and completing one cycle. And updating a next column of selection lines, selecting the next column of selection lines from each of the M memory arrays to be opened, writing test data into a target value memory cell on the next column of selection lines, and completing one cycle. Repeating the steps until the test data are written into all the memory cells on the current word line.
And writing test data into all the memory cells on the current word line, updating the next row address, and starting the next word line according to the next row address. And starting a current column selection line in the memory array on the current word line to write test data into a target value memory cell on the next word line, and updating the next column selection line until the test data is written into all memory cells on the next word line.
For example: in one memory area, there are 16 memory arrays on each word line, and one column select line controls 8 bit lines. Starting a current word line, starting a first column selection line in a1 st memory array, writing test data into 8 memory cells on the current word line, starting the first column selection line in a2 nd memory array, writing test data into 8 memory cells on the current word line, and so on, starting the first column selection line in a 16 th memory array, writing test data into 8 memory cells on the current word line, and writing test data into 128 memory cells on the current word line to complete one cycle. Updating the next column selection line, and repeating the steps until test data is written into all the memory cells on the current word line.
In the technical scheme, when test data is written from each activated storage area, the test data is written in a quick writing mode, and data is written into a plurality of storage units when one column selection line is started each time, so that the data writing time is shortened.
In some embodiments, reading test data corresponding to the plurality of storage areas according to the first compressed read address specifically includes:
s301, in a storage area corresponding to each first compressed read address, starting a current word line according to a current row address, starting a current column selection line in a storage array on the current word line, reading test data from a target value storage unit on the current word line, and updating a next column selection line until the test data is read from all storage units on the current word line.
And decoding the current row address in the storage area corresponding to each first compressed read address, and starting the current word line according to the decoding result. There are M memory arrays on each word line. And selecting the current column selection line from each of the M memory arrays to be opened so as to read test data from the target value memory cells on the current word line and complete one cycle.
After one cycle is completed, ideal read-out data is calculated according to the test data and a preset compression processing rule, and the data read out in one cycle is compared with the ideal read-out data, so that a test result is obtained.
And updating the next column of selection lines, selecting the next column of selection lines from each of the M memory arrays to be started, realizing reading test data from a target value memory unit on the current word line, completing one cycle, and comparing the data read in one cycle with ideal read data to obtain a test result. Repeating the steps until the test data is read from all the memory cells on the current word line.
And reading out test data in all the memory cells on the current word line, updating the next row address, and starting the next word line according to the next row address. The current column select line in the memory array on the current word line is turned on to read test data from the target value of the memory cells on the next word line, and the next column select line is updated until the test data is read from all the memory cells on the next word line.
In the technical scheme, when the test data is read out from each activated storage area, the data is read out by adopting a fast write mode, and the data is read out from a plurality of storage units each time when one column selection line is started, so that the data reading time is shortened.
An embodiment of the present disclosure provides a built-in self-test method, which includes the following steps:
s401, repeatedly executing the test data writing in the plurality of storage areas simultaneously, and completing the data writing in the storage.
S402, refreshing data in each storage area.
S403, repeating the execution and reading out the test data from the plurality of storage areas at the same time, and completing the writing of the data in the storage.
S404, comparing the read test data with the written test data to obtain a test result.
As shown in fig. 4, in S401, the method specifically includes the following sub-steps:
s501, acquiring a first initial address of a storage area to be written with data, and shielding at least one bit address of the first initial address to activate a plurality of storage areas.
Wherein the first initial address BA <3:0> is 0000, the fourth bit address BA <3> and the third bit address BA <2> in the first initial address BA <3:0> are set to high level, and the inversion signal BA <3>B of the fourth bit address and the inversion signal BA <2>B of the third bit address are set to high level. The 1 st storage area BA0, the 5 th storage area BA4, the 9 th storage area BA8 and the 13 th storage area BA12 are activated by decoding the forced first initial address, so that four storage areas are activated simultaneously.
S502, writing test data into the corresponding storage areas according to the first compressed write address.
The 1 st, 5 th, 9 th, and 13 th storage areas BA0, BA4, BA8, and BA12 that are activated are described as a first compressed write address, and test data is written into the 1 st, 5 th, 9 th, and 13 th storage areas BA0, BA4, BA8, and BA12 according to the first compressed write address.
S503, judging whether the data writing of all the storage areas is completed, if yes, entering S504, otherwise, entering S505.
S504, refreshing the data in each storage area.
S505, acquire the next initial address, and return to S501.
In some embodiments, the next initial address is marked as a third initial address. At least one bit address of the third initial address is masked to activate the plurality of memory regions. And recording the activated multiple storage areas as second compressed write addresses, and writing test data into the corresponding storage areas according to the second compressed write addresses.
For example: the third initial address BA <3:0> is 0001, the fourth bit address BA <3> and the third bit address BA <2> in the third initial address BA <3:0> are set to high level, and the inversion signal BA <3>B of the fourth bit address and the inversion signal BA <2>B of the third bit address are set to high level. The forced third initial address is used for decoding, and the 2 nd storage area BA1, the 6 th storage area BA5, the 10 th storage area BA9 and the 14 th storage area BA13 are activated, so that four storage areas are activated simultaneously.
The activated 2 nd, 6 th, 10 th, and 14 th memory areas BA1, BA5, BA9, and BA13 are described as second compressed write addresses, and the 2 nd, 6 th, 10 th, and 14 th memory areas BA1, BA5, BA9, and BA13 are written according to the second compressed write addresses.
As shown in fig. 5, in S403, the method specifically includes the following sub-steps:
s601, acquiring a second initial address of a storage area of data to be read, and shielding at least one bit address of the second initial address to activate a plurality of storage areas.
Wherein the second initial address BA <3:0> is 0000, the fourth bit address BA <3> of the second initial address BA <3:0> is set to a high level, and the inversion signal BA <3>B of the fourth bit address is set to a high level. And decoding through the forced first initial address, and activating the 1 st storage area BA0 and the 9 th storage area BA8 to realize the simultaneous activation of the two storage areas.
S602, reading test data corresponding to a plurality of storage areas according to a first compressed read address, and compressing the test data in the reading process so that the number of bits of the compressed data read out by the memory is equal to the number of bits of uncompressed data read out by one storage area.
The 1 st and 9 th memory areas BA0 and BA8 are written as the first compressed read addresses, and the test data is read out from the 1 st and 9 th memory areas BA0 and BA8 according to the first compressed read addresses.
In some embodiments, in the 1 st memory area BA0 and the 9 th memory area BA8 of the first compressed read address, the current word line is turned on according to the current row address, the current column select line in the memory array on the current word line is turned on, so as to read out the test data from the target value memory cells on the current word line, and the compression process is performed on the test data read out from the target value memory cells.
When the read data in one storage area is uncompressed, the read data is 128 bits. The 128-bit data read out from the 1 st memory area BA0 is compressed to 64 bits according to a preset compression processing rule, and the 128-bit data read out from the 9 th memory area BA8 is compressed to 64 bits according to a preset compression processing rule, so that the number of bits of the compressed data read out from the memory is 128 bits.
In some embodiments, the predetermined compression processing rule comprises an exclusive-or logic operation.
S603, after data are read out from the storage area each time, the read-out test data and the written-in test data are compared, and a test result is obtained.
S604, judging whether the first compressed read address is used for reading the test data corresponding to the storage areas, if not, entering S605, and if yes, entering S606.
S605 updates the row address or the column address, and returns to S602.
If the data of all the memory cells on the current word line are read out, the row address is updated, and the test data of the memory cells on the next word line are read. If the data of all the memory cells on the current word line are not read out, the column address is updated, that is, the next column of the selection line is updated, and the test data of the memory cells on the bit line controlled by the next column of the selection line is read.
S606, judging whether the data reading of all the storage areas is completed, if not, proceeding to S607, if so, ending the flow.
S607, acquire the next initial address, and return to S601.
In some embodiments, the next initial address is marked as a fourth initial address, and at least one bit address of the fourth initial address is masked to activate the plurality of memory regions. The addresses of the activated storage areas are recorded as second compressed read addresses. And reading the test data corresponding to the storage areas according to the second compressed read address, and compressing the test data in the reading process so that the number of bits of the compressed data read out by the memory is equal to the number of bits of the uncompressed data read out by one storage area.
As shown in fig. 6, an embodiment of the disclosure provides a built-in self-test device 700, a memory including a plurality of memory areas, the built-in self-test device 700 comprising:
a writing module 701, configured to obtain a first initial address of a storage area where data is to be written; shielding at least one bit address of the first initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed write addresses; writing test data into the corresponding storage area according to the first compressed write address;
a reading module 702, configured to obtain a second initial address of a storage area of data to be read; shielding at least one bit address of the second initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed read addresses; reading test data corresponding to the storage areas according to the first compressed read address, and compressing the test data in the reading process so that the number of bits of the compressed data read out by the memory is equal to the number of bits of uncompressed data read out by one storage area;
and an output module 703 for calculating ideal read data according to the test data and the preset compression processing rule, and comparing the read data of the memory with the ideal read data to obtain a test result.
In some embodiments, the writing module 701 is specifically configured to:
and acquiring a compressed write instruction, and forcing at least one address in the first initial address and an inversion signal thereof to be the same specific value based on the compressed write instruction so as to activate a plurality of corresponding storage areas.
In some embodiments, the readout module 702 is specifically configured to:
and acquiring a compressed read instruction, and forcing at least one address in the second initial address and an inversion signal thereof to be the same specific value based on the compressed read instruction so as to activate a plurality of corresponding storage areas.
In some embodiments, each storage area includes a plurality of storage arrays, and the writing module 701 is specifically configured to:
and in the storage area corresponding to each first compressed writing address, starting a current word line according to the current row address, starting a current column selection line in a storage array on the current word line so as to write test data into a target value storage unit, and updating a next column selection line until the test data are written into all storage units on the current word line.
In some embodiments, each memory region includes a plurality of memory arrays, and the readout module 702 is specifically configured to:
and in the storage area corresponding to each first compressed read address, starting a current word line according to the current row address, starting a current column selection line in the storage array on the current word line so as to read out test data from a target value storage unit, and updating a next column selection line until the test data are read out from all storage units on the current word line.
In some embodiments, the number of memory regions that are activated simultaneously when writing data is greater than the number of memory regions that are activated simultaneously when reading data.
In some embodiments, the writing module 701 is specifically configured to:
acquiring a third initial address of a storage area of data to be written;
shielding at least one bit address of the third initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as second compressed write addresses;
writing test data into the corresponding storage area according to the second compressed write address;
the readout module 702 is specifically configured to:
acquiring a fourth initial address of a storage area of data to be read;
shielding at least one address of the fourth initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as second compressed read addresses;
and reading the test data corresponding to the storage areas according to the second compressed read address, and compressing the test data in the reading process so that the number of bits of the compressed data read out by the memory is equal to the number of bits of the uncompressed data read out by one storage area.
The disclosed embodiments also provide a computer readable storage medium having stored therein computer instructions which, when executed by a processor, implement the steps of the methods of the above embodiments.
The disclosed embodiments also provide a computer program product comprising computer instructions which, when executed by a processor, implement the steps of the methods of the above embodiments.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (10)
1. A method of built-in self-test, wherein a memory includes a plurality of memory regions, the method comprising:
acquiring a first initial address of a storage area of data to be written;
shielding at least one address of the first initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed write addresses;
writing test data into the corresponding storage area according to the first compressed write address;
acquiring a second initial address of the storage area of the data to be read;
shielding at least one address of the second initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed read addresses;
reading the test data corresponding to the storage areas according to the first compressed read address, and compressing the test data in the reading process so that the bit number of the compressed data read out by the memory is equal to the bit number of the uncompressed data read out by one storage area;
and calculating ideal read-out data according to the test data and a preset compression processing rule, and comparing the read-out data of the memory with the ideal read-out data to obtain a test result.
2. The method of claim 1, wherein masking at least one address of the first initial address, in particular, comprises:
and acquiring a compressed write instruction, and forcing at least one address in the first initial address and an inversion signal thereof to be the same specific value based on the compressed write instruction so as to activate a plurality of corresponding storage areas.
3. The method of claim 2, wherein masking at least one address of the second initial address, in particular, comprises:
and acquiring a compressed read instruction, and forcing at least one address in the second initial address and an inversion signal thereof to be the same specific value based on the compressed read instruction so as to activate a plurality of corresponding storage areas.
4. A built-in self-test method according to any one of claims 1 to 3, wherein each memory region comprises a plurality of memory arrays;
writing test data into the corresponding storage area according to the first compressed write address, wherein the writing test data comprises the following steps:
and in the storage area corresponding to each first compressed writing address, starting a current word line according to a current row address, starting a current column selection line in the storage array on the current word line so as to write the test data into a target value storage unit, and updating a next column selection line until the test data is written into all storage units on the current word line.
5. A built-in self-test method according to any one of claims 1 to 3, wherein each memory region comprises a plurality of memory arrays;
reading the test data corresponding to the storage areas according to the first compressed read address, wherein the method specifically comprises the following steps:
and in the storage area corresponding to each first compressed read address, starting a current word line according to a current row address, starting a current column selection line in the storage array on the current word line so as to read out the test data from a target value storage unit, and updating a next column selection line until the test data is read out from all storage units on the current word line.
6. A built-in self-test method according to any one of claims 1 to 3, wherein the number of memory areas activated simultaneously when writing data is larger than the number of memory areas activated simultaneously when reading data.
7. A method of built-in self-test according to any one of claims 1 to 3, wherein prior to obtaining the second initial address of the storage area of the data to be read, the method further comprises:
acquiring a third initial address of a storage area of data to be written;
shielding at least one address of the third initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as second compressed write addresses;
writing test data into the corresponding storage area according to the second compressed write address;
accordingly, before calculating ideal readout data according to the test data and a preset compression processing rule, and comparing the readout data of the memory with the ideal readout data to obtain a test result, the method further includes:
acquiring a fourth initial address of the storage area of the data to be read;
shielding at least one address of the fourth initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as second compressed read addresses;
and reading the test data corresponding to the storage areas according to the second compressed read addresses, and compressing the test data in the reading process so that the number of bits of the compressed data read out by the memory is equal to the number of bits of the uncompressed data read out by one storage area.
8. A built-in self-test device, wherein a memory includes a plurality of memory regions, the device comprising:
the writing module is used for acquiring a first initial address of a storage area of data to be written; shielding at least one address of the first initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed write addresses; writing test data into the corresponding storage area according to the first compressed write address;
the reading module is used for acquiring a second initial address of the storage area of the data to be read; shielding at least one address of the second initial address to activate a plurality of storage areas, and recording the addresses of the activated storage areas as first compressed read addresses; reading the test data corresponding to the storage areas according to the first compressed read address, and compressing the test data in the reading process so that the bit number of the compressed data read out by the memory is equal to the bit number of the uncompressed data read out by one storage area;
and the output module is used for calculating ideal read-out data according to the test data and a preset compression processing rule, and comparing the read-out data of the memory with the ideal read-out data to obtain a test result.
9. The built-in self-test device according to claim 8, wherein the writing module is specifically configured to:
and acquiring a compressed write instruction, and forcing at least one address in the first initial address and an inversion signal thereof to be the same specific value based on the compressed write instruction so as to activate a plurality of corresponding storage areas.
10. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to implement the built-in self-test method according to any of claims 1 to 7.
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|---|---|---|---|
| CN202211137932.1A CN117766007A (en) | 2022-09-19 | 2022-09-19 | Built-in self-test method and device |
| PCT/CN2022/123947 WO2024060316A1 (en) | 2022-09-19 | 2022-10-09 | Built-in self-test method and device |
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| CN202211137932.1A CN117766007A (en) | 2022-09-19 | 2022-09-19 | Built-in self-test method and device |
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| JP2746222B2 (en) * | 1995-08-31 | 1998-05-06 | 日本電気株式会社 | Semiconductor storage device |
| CN103310852B (en) * | 2013-05-13 | 2015-11-04 | 桂林电子科技大学 | Based on the mbist controller structural system of IEEE 1500 operating such SRAM/ROM |
| CN103310850B (en) * | 2013-06-27 | 2016-01-20 | 桂林电子科技大学 | The BIST Structure of network-on-chip resource node storer and self-test method |
| CN103943152B (en) * | 2014-03-31 | 2017-02-01 | 西安紫光国芯半导体有限公司 | Rapid built-in self-testing system and method of memory |
| CN106971761B (en) * | 2016-01-13 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Circuit and method for testing SRAM cycle time |
| CN111145826B (en) * | 2018-11-05 | 2021-08-31 | 珠海格力电器股份有限公司 | Memory built-in self-test method, circuit and computer storage medium |
| CN112614534B (en) * | 2020-12-17 | 2023-09-05 | 珠海一微半导体股份有限公司 | MBIST circuit system |
| CN114582411A (en) * | 2022-03-01 | 2022-06-03 | 长鑫存储技术有限公司 | Memory detection method, circuit, device, equipment and storage medium |
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