CN114582411A

CN114582411A - Memory detection method, circuit, device, equipment and storage medium

Info

Publication number: CN114582411A
Application number: CN202210212388.6A
Authority: CN
Inventors: 陆天辰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2022-06-03
Also published as: WO2023165044A1

Abstract

The disclosure provides a memory detection method, circuit, device, equipment and storage medium. The memory detection method comprises the following steps: writing test data into at least a portion of the memory cells of the memory; opening a word line connected to the memory cell; taking 2N storage units corresponding to an even number of input and output pins as a compression group, and reading target data stored in each storage unit in the compression group, wherein N is a positive integer; calculating target data corresponding to the compression group according to a preset processing method, and determining detection information of the compression group; and determining whether the storage units in the compression group have defects according to the detection information. By adopting the memory detection method, whether the memory unit of the memory has defects can be quickly tested, a large amount of detection time is saved, the test efficiency is improved, and the test cost is saved.

Description

Memory detection method, circuit, device, equipment and storage medium

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory detection method, circuit, device, apparatus, and storage medium.

Background

Before the chip leaves the factory, the chip is usually subjected to a series of tests to be applied as a product, such as a wafer Test (CP Test for short), a Final Test (FT Test for short), and the like. In the wafer test (CP test) stage, a memory cell matrix of a memory chip needs to be tested, and a unit with an error is rapidly detected in the memory cell matrix, so that a defect is rapidly repaired, and subsequent manufacturing is not affected. The traditional detection mode aiming at the memory cell matrix only can carry out detection operation of one row and one column, so that the test efficiency is not high, a large amount of time is wasted, and the test cost is high.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a memory detection method, circuit, device, equipment and storage medium.

According to a first aspect of embodiments of the present disclosure, there is provided a memory detection method, including:

writing test data into at least some memory cells of the memory;

opening a word line connected to the memory cell;

taking 2N storage units corresponding to an even number of input and output pins as a compression group, and reading target data stored in each storage unit in the compression group, wherein N is a positive integer;

calculating the target data corresponding to the compression group according to a preset processing method, and determining the detection information of the compression group;

and determining whether the storage units in the compression group have defects according to the detection information.

According to some embodiments of the present disclosure, the operating the target data corresponding to the compression group according to a preset processing method to determine the detection information of the compression group includes:

comparing target data in two storage units corresponding to two different input and output pins according to a first preset method to obtain N pieces of comparison result information; wherein the first preset method comprises an exclusive or logic operation;

and determining the detection information of the compression group according to the comparison result information.

According to some embodiments of the disclosure, the determining detection information of the compression group according to the comparison result information includes:

inputting the N pieces of comparison result information into the corresponding N transistors respectively;

dividing the N transistors into two comparison groups, and acquiring the state information of the transistors in each comparison group;

determining output information of each of the comparison groups according to the state information of each of the transistors in each of the comparison groups;

and determining the detection information of the compression group according to the output information.

According to some embodiments of the disclosure, the transistor comprises an NMOS transistor.

According to some embodiments of the disclosure, the determining detection information of the compression group according to the output information includes:

and carrying out NOR logic operation on the output information of the two comparison groups, wherein the operation result is used as the detection information of the compression group.

According to some embodiments of the present disclosure, the determining whether the storage units in the compressed group have defects according to the detection information includes:

when the operation result is low level, determining that the memory cells in the compression group have defects;

and when the operation result is high level, determining that the memory cells in the compression group have no defects.

According to some embodiments of the disclosure, the detection method further comprises:

and after each compression group finishes detection, controlling the comparison group to carry out reset operation.

caching preset data stored in each storage unit except the target data, and controlling the preset data not to participate in the process of reading the target data stored in each storage unit.

A second aspect of the present disclosure provides a memory detection circuit, comprising:

the compression circuit comprises a first processing circuit, the first processing circuit is connected with an even number of input and output pins of a memory, the input and output pins correspond to 2N storage units of the memory, the first processing circuit comprises N logic gates, each logic gate is connected with the input and output pins corresponding to two storage units, and N is a positive integer;

the second processing circuit comprises N transistors which are respectively connected to the output ends of N logic gates of the first processing circuit, the N transistors are respectively two comparison groups, and the detection circuit comprises output ends respectively corresponding to the two comparison groups;

and the judging circuit is connected with the output ends respectively corresponding to the two comparison groups.

According to some embodiments of the present disclosure, the judging circuit includes a judging logic gate connected to the output ends corresponding to the two comparison sets, respectively.

According to some embodiments of the present disclosure, the memory detection circuit further comprises a reset circuit connected between the output terminal of the transistor corresponding to each of the comparison groups and the input terminal of the judgment logic gate.

According to some embodiments of the disclosure, the compression circuit further comprises a latch connected to the even number of input-output pins.

According to some embodiments of the present disclosure, the detection circuit further comprises a precharge circuit connected to the input terminal of the judgment circuit for precharging the input terminal of the judgment circuit to a high level.

A third aspect of the present disclosure provides a memory device, including:

the writing module is used for writing the test data into at least part of storage units of the memory;

the control module is used for opening a word line connected with the storage unit;

the reading module is used for taking 2N storage units corresponding to an even number of input and output pins as a compression group and reading target data stored in each storage unit in the compression group, wherein N is a positive integer;

the judging module is used for determining the detection information of the compression group according to a preset processing method and the target data;

the judging module is further configured to determine whether the storage unit in the compression group has a defect according to the detection information.

According to some embodiments of the present disclosure, the detection apparatus further includes a reset module, configured to control the comparison group to perform a reset operation after each compression group completes detection.

According to some embodiments of the present disclosure, the detection apparatus further includes a buffer for buffering preset data stored in each of the storage units, except for the target data;

the control module is further configured to:

and controlling the preset data not to participate in the target process of reading the data stored in each storage unit.

A fourth aspect of the present disclosure provides a memory device, including:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to perform the memory detection method of the first aspect.

According to a fifth aspect of embodiments of the present disclosure, there is provided a non-transitory computer readable storage medium having instructions thereon which, when executed by a processor of a memory test device, enable the memory test device to perform the memory detection method according to the first aspect.

The memory detection method, the circuit, the device, the equipment and the storage medium provided by the embodiment of the disclosure solve the problems of low operation efficiency, time waste, detection resource waste and the like in wafer test in the prior art. By using the memory detection method disclosed by the invention, the memory detection efficiency can be improved, the detection time can be shortened, a large amount of time can be saved for subsequent processing, and the test cost can be saved.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.

FIG. 1 is a flow chart illustrating a memory sensing method according to an exemplary embodiment;

FIG. 2 is a schematic diagram illustrating the connection of memory wordlines to memory cells in accordance with an example embodiment;

FIG. 3a is a schematic diagram illustrating a data entry structure according to an exemplary embodiment;

FIG. 3b is a schematic diagram of a data entry structure shown in accordance with an exemplary embodiment;

FIG. 4a is a schematic diagram of a compression group shown in accordance with an exemplary embodiment;

FIG. 4b is a schematic diagram of a compression group shown in accordance with an exemplary embodiment;

FIG. 5a is a schematic diagram of a compression circuit shown in accordance with an exemplary embodiment;

FIG. 5b is a schematic diagram of a detection circuit and a determination circuit shown in accordance with an exemplary embodiment

FIG. 6 is a diagram illustrating a compressed memory cell in accordance with an exemplary embodiment;

FIG. 7 is a block diagram illustrating a memory detection arrangement in accordance with an exemplary embodiment;

FIG. 8 is a block diagram illustrating a memory detection device in accordance with an exemplary embodiment.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

Before the chip is shipped, a series of tests are usually performed to be applied as a product, such as a wafer Test (CP Test for short) using a chip probe, a Final Test (FT Test for short), and the like. In the wafer test (CP test) stage, a memory cell matrix of a memory chip needs to be tested, and a defective memory cell in the memory cell matrix is mainly detected quickly, so that defects can be repaired quickly and the influence on subsequent processes can be avoided.

For one-time writing operation defined by microelectronic product standards, only one row and one column can be operated. For one read operation, only 64 bits of data can be read, resulting in inefficient testing. If the above reading operation is also used for testing in the wafer test (CP test) stage, a lot of time is wasted and the testing cost is consumed. Therefore, it is necessary to design a memory test method to perform this phase of test, so as to be able to test the memory cells in the whole memory more quickly.

In order to solve the above problem, the present disclosure provides a memory detection method. In the memory detection method, test data is written into at least part of the memory cells. When data is read, the storage units are grouped according to the input and output pins, 2N storage units corresponding to even number of input and output pins are used as a compression group, target data stored in the compression group are operated, detection information of the compression group is finally determined, and whether the storage units in the compression group have defects or not is determined according to the detection information. The storage units in the memory are divided into the compression groups for detection, and a large number of storage units can be detected in one detection process, so that whether the storage units in the memory have defects or not can be quickly detected, and the detection efficiency is improved while the detection accuracy and reliability are ensured.

An exemplary embodiment of the present disclosure provides a method for detecting a memory, as shown in fig. 1, the method for detecting a memory provided by the present embodiment includes the following steps:

s110, writing the test data into at least part of memory cells of the memory;

s120, opening a word line connected with the storage unit;

s130, taking 2N storage units corresponding to an even number of input and output pins as a compression group, and reading target data stored in each storage unit in the compression group, wherein N is a positive integer;

s140, calculating target data corresponding to the compression group according to a preset processing method, and determining detection information of the compression group;

and S150, determining whether the storage units in the compression group have defects or not according to the detection information.

In step S110, it is necessary to detect whether the memory cells can normally store data in the wafer test stage, that is, to detect whether the written data and the read data are consistent, so before performing the subsequent detection step, the test data needs to be written into at least some memory cells of the memory, and then the test data needs to be read in the subsequent step, and then whether the memory cells have defects is detected by comparing the written test data and the read data.

When writing test data, it is determined which part of the memory cells in the memory is to be tested, and then the test data is written into the part of the memory cells. For example, the test data may be written into all the memory cells of the memory at the same time when all the memory cells of the memory are detected. For another example, some memory cells of the memory may be detected, and after determining the range of the memory cell to be detected, the test data may be written into the selected memory cell.

Referring to fig. 2, first, test data is written into memory cells of the memory to be tested, and in one example, 16 banks (banks) in the memory are selected, that is, the bank 0, the bank 1, the bank 2, the bank … …, and the bank 15 shown in fig. 2. It should be noted that the memory cell is usually the smallest memory cell in the memory, each memory cell stores data of one bit, each memory bank includes a plurality of memory cells, each memory bank includes two memory blocks (halfbank), and the amount of data stored in each memory block is half of the memory bank. It should be noted that at least part of the memory cells in step S110 may be memory cells corresponding to a row of word lines in the memory block, and when the compression set is compressed subsequently, 64-bit data stored corresponding to one word line may be compressed to 1bit, or two 32-bit data may be compressed to 1 bit.

In order to test whether the memory cells in the 16 banks have problems and can normally store data, test data is written into each bank. For example, in the compression mode, one row of word lines of each of the two memory blocks in each memory bank is activated to be opened by one activation command, that is, 32 word lines are opened, so as to pre-store the test data used in the test process into the memory cells connected to each word line. Specifically, in the present embodiment, there are 16 memory banks in total, and each memory bank includes two memory blocks, so there are 32 memory blocks in total, and the activate command activates one row of word lines of each memory block, so the activate command activates 32 word lines in total.

In order to improve the test accuracy and convenience, when test data is written, the test data written in each port for writing the test data is ensured to be consistent. Referring to fig. 2, the port for writing test data in the present embodiment includes a row address latch 111, a command latch 112, and a bank address latch 113. The row address latch 111, the command latch 112, and the bank address latch 113 may each receive an instruction, respectively, wherein the row address latch 111 is electrically connected to the first control module 100; the command latch 112 is connected to a command decoder 114, and the command decoder 114 is electrically connected to the first control module 100 and the second control module 200, respectively; the bank address latch 113 is electrically connected to a bank address decoder 115, and the bank address decoder 115 is electrically connected to the second control module 200. The input of the row address latch 111 is connected to the third amplifier 01, the input of the command latch 112 is connected to the first amplifier 02, and the input of the bank address latch 113 is connected to the second amplifier 03. Each amplifier is provided with a positive input terminal and a negative input terminal, the negative input terminal of each amplifier is a command and address reference voltage signal terminal, the positive input terminal of the third amplifier 01 is a voltage signal terminal of a row address signal, the positive input terminal of the first amplifier 02 is a voltage signal terminal of an activation command, and the positive input terminal of the second amplifier 03 is a voltage signal terminal of an address signal of a memory bank. The test data to be written into the memory cell is written into the memory cell through the ports.

In this embodiment, one word line of each of the 32 memory blocks in the 16 memory banks is opened by an activation command, so as to ensure that each memory cell connected to the word line in the 32 memory blocks in the 16 memory banks writes consistent test data, that is, to ensure that pulses received by each memory cell are the same, so as to avoid detection errors occurring in a subsequent detection process due to the writing of different test data, for example, the data written into each memory cell is inconsistent to affect subsequent determination operations, thereby causing a false determination of whether the memory cell has a fault.

In step S120, referring to fig. 2, the first signal lines 311 are electrically connected to the memory banks 0 to 15, respectively, and the first signal lines 311 are further electrically connected to the first control module 100; the second signal line 322 is electrically connected to the memory banks 0 to 15, respectively, and the second signal line 322 is also electrically connected to the second control module 200. Wherein, the input end of the first control module 100 is electrically connected to the row address latch 111 and the command decoder 114, respectively, and the first control module 100 is configured to receive a row address signal transmitted by the row address latch 111 and receive an activation command transmitted by the command decoder 114. The second control module is electrically connected to the command decoder 114 and the bank address decoder 115, respectively, and is configured to receive the bank address signal and the activate command.

Test data to be read from the memory cells, which has been written into the memory cells, is defined as target data, and in reading the target data, first, the first signal lines 311 and the second signal lines 322, which are electrically connected to the banks 0 to 15, are opened. Then, the active command amplified by the first amplifier 02 is transferred to the command latch 112 for latching, and transferred from the command latch 112 to the command decoder 114, and further transferred to the first control module 100. When the first control module 100 receives the activate command from the command decoder 114, the first control module 100 outputs a control signal to the first signal line 311, and opens the word lines of one memory block in each of the memory banks 0 to 15 (16 memory banks in total), that is, opens 16 word lines.

When the second control module 200 receives the activate command from the command decoder 114, the second control module 200 outputs a control signal to the second signal line 322 to turn on the word lines of another memory block in each of the memory banks 0 to 15 (16 memory banks in total), i.e., turn on 16 word lines. Therefore, in the compression mode, the first control module 100 outputs a control signal to the first signal line 311, and the second control module 200 outputs a control signal to the second control line 322 to open the word lines of each memory block included in each of the memory banks 0 to 15, i.e., a total of 32 word lines are opened by one activation command.

In an exemplary embodiment, referring to fig. 3a and 3b and fig. 2, in the memory cells of the memory bank in the embodiment, in addition to storing the test data, other preset data except the test data may be written into the memory cells of the memory banks 0 to 15. In order to avoid that other preset data is read when the target data is read, and the read target data is affected by the other preset data, the decoder 330 is provided in the embodiment. The decoder 330 has a wide range of applications, and is not only used for code conversion, digital display of terminals, but also for data distribution, memory addressing, and combination of control signals. In the present embodiment, the input terminals of the decoder 330 are electrically connected to the row address latch 111, the command latch 112 and the bank address latch 113 respectively, and the test data and other preset data required to be written into the memory cells in the banks 0 to 15 are transmitted to the decoder 330 from the row address latch 111, the command latch 112 and the bank address latch 113 respectively according to the source and the effect of the signal, and transmitted to the memory cells in the banks 0 to 15 through the decoder 330.

In some possible embodiments, as shown in fig. 3b and fig. 2, a latch or flip-flop is provided at the input-output pin 700 corresponding to the memory banks 0 to 15. In order to improve data operation reliability, latches, namely latches 341, latches 342, … …, and latches 3416 shown in fig. 3b are provided at the input and output pins 700 of each memory cell, the number of latches corresponding to the number of banks one to one, wherein the corresponding input and output pin 700 of each bank is connected to the latch through one pin of a logic nor gate, and the other pin of the logic nor gate is connected to the voltage terminal of the address signal of the bank.

Each latch is provided with an input port, an output port (i.e., an output enable port), a reset port, and a latch activation command port. The latch activation command port is used for receiving a latch activation command, and the latch latches data after receiving the latch activation command. The reset port is used for receiving a reset command, and after the reset command is received, the latch is reset, so that data input into the latch can be stored again. The output port of the latch outputs enable. In the present embodiment, memory cell 0 is set corresponding to latch 341, memory cell 1 is set corresponding to latch 342, … …, and memory cell 15 is set corresponding to latch 3416, and the test data enters into memory bank 0 to memory bank 15 through decoder 330 as shown in FIG. 3a, and enters into the latch corresponding to the memory bank as shown in FIG. 3b for latching.

When the latch does not receive the latch activating command, the output port of the latch does not change along with the input signal of the input port, and the latch still keeps the original state and does not output the data input by the input port of the latch. When the latch receives the latch activation command, the data is output from the output port. As shown in fig. 3b, when the latch activation command port of the latch 341 to the latch 3416 does not receive the latch activation command, no matter what data is input from the input port of each latch, no data is output from the output port of the latch, so that other preset data stored in the memory bank is saved, the output state of the test data in the memory bank is not affected, and the other preset data stored in the memory bank is prevented from affecting the read target data.

According to another embodiment of the present disclosure, a flip-flop may be set without setting a latch at the input-output pins 700 of the memory banks 0 to 15 shown in fig. 2. After passing through the decoder 330 shown in FIG. 3a, the test data may be written into the banks 0-15. The flip-flop will cause the output port of the flip-flop to keep outputting the data written from the input port unchanged until the clock signal comes. When the clock signal is received, the state of the output port of the trigger is changed by the trigger, and the data received by the trigger is output from the output port of the trigger after the clock signal is received. Therefore, the storage unit is connected with the trigger, so that the test data in the storage unit are not influenced by other preset data, and the accuracy of the output data cannot be influenced due to the self structure of the storage unit after the test data are written into the storage unit.

In step S130, as shown in fig. 4a and 4b, the DQ shown in fig. 4a and 4b is used to characterize the input/output pin of the memory as the data port of the data write memory cell. The method can be applied to memories such as DDR3 DRAM, DDR4 DRAM, DDR5 DRAM, etc., wherein DRAM (dynamic Random Access memory) generally refers to dynamic Random Access memory. As shown in fig. 4a, data transfer may be made with an external controller via 8 DQs. Referring to fig. 2, the banks 0 to 15 have 16 banks, i.e., 32 memory blocks. For data writing of a row of word lines in one memory block, when the Burst Length (BL) is 8, the 8 data ports will input 64 bits of data. The 8 data ports correspond to one compression group 44. bit is the data bit of the memory cell, as shown in fig. 4a, if the burst length is 8, one data port corresponds to 8 data bits, namely bit0, bit1, …, and bit7, that is, one data port DQ0 corresponds to bit0 to bit7, the other data port DQ1 corresponds to bit0 to bit7, and so on. Those skilled in the art will understand that the burst length is not limited thereto, for example, as shown in fig. 4b, the burst length may be 4, and one data port corresponds to 4 data bits, i.e. one data port DQ0 corresponds to bits 0 to bit3, another data port DQ1 corresponds to bits 4 to bit7, and so on.

It should be noted that, in this embodiment, the memory banks 0 to 15 are taken as an example, and the above-mentioned fig. 4a and 4b illustrate a data compression method of a data port of one word line of two memory blocks of one memory bank. In addition to forming the compression group by using the burst length of 4 or 8, in the implementation process, the compression group division may be performed by using the target data stored in 2N storage units as one compression group, where N is a positive integer, and for example, N may be 1, 2, 3, 4, and the like.

As shown in fig. 4a and 4b, after a plurality of compression groups 44 are formed, the information in the compression groups 44 is subjected to xor comparison, and each four ports are compressed to 1bit of data. Different ways of comparison may be used when performing an exclusive-or comparison of the information in the compressed set 44. In one example, the data between the two compressed groups 44 may be compared, for example, the data in DQ0 and DQ1 are xored to obtain a first result, the data in DQ2 and DQ3 are xored to obtain a second result, then the first result and the second result are xored to obtain a final result, and the output operation result is compressed to 1 bit. In another example, the memory cells in each packed group 44 may be xored two by two, each packed group outputting one comparison result a, i.e., DQ0 outputting comparison result a0, DQ1 outputting comparison result a1, and so on. Then, performing exclusive or operation on the comparison result A0 output by DQ0 and the comparison result A output by DQ1, and outputting a first result; and after the data in DQ2 and DQ3 are subjected to similar processing, outputting a second result, performing exclusive OR comparison on the first result and the second result to obtain a final result, and compressing the output operation result into 1 bit. By the method in the embodiment, the test data stored in the large number of storage units can be divided into the compression groups 44 with relatively small number, then the exclusive-or operation is performed on the compression groups 44, and finally the target data stored in the 2N storage units is compressed into 1bit, so that the purpose of rapidly detecting the storage units is achieved.

Because only 64 bits of information can be written or read when data is written or read conventionally, in the process of carrying out data writing and reading operation once, each detection can only aim at the memory cells corresponding to one row of word lines, and the detection efficiency is low. In the embodiment, in the detection process, one activation instruction can simultaneously open the word lines in each of the 32 memory blocks, and each word line can output 64-bit information, so that 2048-bit information can be obtained in one writing and reading operation, and the detection efficiency in the detection process is greatly improved.

Referring to FIG. 4a and the memory cell after compression as shown in FIG. 6, when the data in one compression group 44 is 8 bits, the 64-bit data corresponding to one word line is compressed to 2 bits, i.e. the 64-bit data corresponding to one word line in one memory block is compressed to 2 bits. The information in each bank is compressed to 4 bits, and in the embodiment shown in fig. 6, the information of 2048 bits in 16 banks, i.e., from bank 0 to bank 15, is finally compressed to 64 bits. Specifically, the repository 0 includes two storage blocks, each storage block is compressed to 2 bits, each storage block includes compressed 4-bit data, the 4-bit data are respectively marked as bit0 'to bit 3', the repository 0 corresponds to information of compressed bit0 'to bit 3', the repository 1 corresponds to information … … of compressed bit8 'to bit 11', and so on, and it is known that the repositories 0 to the storage unit 7 correspond to compressed bit0 'to bit 31'. Similarly, the banks 8 to 15 correspond to the compressed bits 0 'to 31' similarly, so that, of the 16 banks, the bank 0 to the bank 15 correspond to the compressed 64-bit information, and the compressed 64-bit information can be read out by one command without writing data or reading data in rows and columns for each bank for many times, thereby achieving the purpose of quickly reading test data.

In step S140, the following two steps may be included in the implementation process:

s141, comparing target data in two storage units corresponding to two different input and output pins according to a first preset method to obtain N pieces of comparison result information; the first preset method comprises an exclusive-or logic operation.

And S142, determining the detection information of the compression group according to the comparison result information.

In step S141, an exclusive or logical operation is performed on each storage unit of each compression group, and a piece of comparison result information is obtained according to the logical operation. The total 816 bits of data of every two data ports DQ in the compression group are subjected to xor logic operation by a circuit shown in fig. 5a, so that 8-bit compression group information is finally obtained, and a 32-bit comparison result is finally obtained by xor logic operation for 64 bits corresponding to a row of word lines in a memory block.

In step S142, as shown with reference to fig. 5b, N pieces of comparison result information are input to the corresponding N transistors, respectively, the N transistors are divided into two comparison groups 444, state information of the transistors in each comparison group 444 is acquired, output information of the comparison groups 444 is determined according to the state information of each transistor in each comparison group 444, and detection information of the compression group 44 is determined according to the output information. Specifically, 16bit data is input to the 16 transistors shown in FIG. 5 b. The 16 transistors are divided into 2 comparison groups 444, and each comparison group 444 comprises 8 transistors. The input end of one comparison group 444 is connected with the first inverter 04, the input end of the other comparison group 444 is connected with the second inverter 05, in the process of reading target data, the input ends of the first inverter 04 and the second inverter 05 are both input with a high-level read signal READT, and after the high-level read signal READT is inverted by the first inverter 04 and the second inverter 05, low-level signals READB are respectively output to the two comparison groups 444.

The transistors comprise NMOS transistors, and when the comparison result information is output to be at a high level, the comparison result information is output to be at a low level through the NMOS transistors; and when the comparison result information is at a low level, the comparison result information is output as a high level after passing through the NMOS tube. As in the present embodiment, the comparison result information of the memory cells in the compression group 44 is inputted into the corresponding transistors, the transistors are divided into two comparison groups 444 as shown in fig. 5b, and the comparison result information is outputted through the transistors, wherein, when the comparison result information outputs of the memory cells are all 0, the comparison result information is outputted as high level after passing through the transistors. If there is a comparison result information output of 1, the transistor outputs a low level. Through the circuit shown in fig. 5b, two compression sets are divided into 8-bit comparison sets, and a total of 16 bits are compressed into 1 bit. For a row of word lines in a memory block, the 32 bits obtained by compression in fig. 5a are compressed to obtain a comparison result of 2 bits, and for 16 banks, that is, 32 memory blocks, 2048 bits are compressed to 64 bits.

In step S150, it is determined whether the memory cells in the compressed group have defects according to the detection information. And when the operation result is in a low level, determining that the memory cells in the compression group have defects, and when the operation result is in a high level, determining that the memory cells in the compression group have no defects. In an exemplary embodiment, the detection information of the two comparison sets 444 is obtained by performing a nor logic operation as shown in the judgment circuit 111 in fig. 5b, and when the operation result is a low level, it is determined that the memory cells in the compression set are defective, and when the operation result is a high level, it is determined that the memory cells in the compression set are not defective, so that the fast detection of the memory is completed, and the time consumed by performing a row-column data detection on each memory cell individually in the conventional method is saved.

In addition, it should be noted that after the detection is completed on each compression group, the comparison group is controlled to perform a reset operation, so that information in each detection process in the comparison group is deleted, thereby facilitating polarity multiple times and rapid detection in subsequent processes and achieving the effect of cycle detection.

Referring to fig. 5a, 5b, a memory sensing circuit is shown according to an exemplary embodiment. As shown in fig. 5a and 5b, the memory detection circuit includes: a compression circuit 555, a detection circuit 666 and a judgment circuit 111. Referring to fig. 5a, the compressing circuit 555 includes a first processing circuit 511, and the first processing circuit 511 is connected to 2N memory cells corresponding to the even number of input/output pins 700 (see fig. 2) of the memory. For example, 8 input/output pins with a burst length of 8 are used, 8 input/output pins 700 correspond to 64 memory cells of a row of word lines in a memory block, that is, 64-BIT data, 8-BIT data are output for an input/output pin DQ0, namely DQ0BIT 0, DQ0BIT 1 to DQ0BIT7, 8-BIT data are output for an input/output pin DQ1, namely DQ 1BIT 0, DQ 1BIT 1 to DQ 1BIT 7, and so on, 8-BIT data are output for an input/output pin DQ7, namely DQ7 BIT0, DQ7 BIT1 to DQ7 BIT 7.

The first processing circuit 511 includes N logic gates, each logic gate is connected to two input/output pins corresponding to two memory cells, where N is a positive integer, that is, each two memory cells use one logic gate to perform logic judgment and output a logic result. The test data stored in the memory cells enter the logic gate of the first processing circuit 511 through an even number of output pins to quickly perform operation on the test data in the memory cells, and if the data in 2N memory cells are compressed into Nbit data, the 64-bit data of 64 memory cells corresponding to a row of word lines in one memory block can be compressed and output as 32-bit data after passing through the compression circuit 555.

The detection circuit 666 includes the second processing circuit 611, and as shown in fig. 5b, the second detection circuit 611 includes N transistors, the N transistors are respectively connected to the output terminals of the N logic gates of the first processing circuit 511, the N transistors are divided into two comparison groups 444, and the detection circuit 666 further includes output terminals corresponding to the two comparison groups 444 respectively. The N transistors in the second processing circuit 611 are connected to the output end of the logic gate of the first processing circuit 511, the test data directly enters the N transistors in the second processing circuit 611 after being operated by the first processing circuit 511, and the test data is output through the N transistors of the two comparison groups 444 to form the output information of the two comparison groups 444. The N transistors may be NMOS transistors, and are used to output the output information of the two comparison sets 444. Because the storage unit prestores consistent data, after the compression circuit 555 performs exclusive-or logic operation, if the storage unit is not abnormal, the compression circuit 555 outputs a low level signal, and the NMOS transistors in the comparison group 444 are not conducted; if the memory cell is abnormal, the compression circuit 555 outputs a high level signal, the NMOS transistor in the comparison set 444 is turned on, and the comparison set 444 outputs a low level signal.

The judgment circuit 111 is connected to the output terminals corresponding to the two comparison groups 444, and performs final judgment on the output information of the two comparison groups 444. In an embodiment of the present disclosure, the determining circuit 111 includes a not gate and a nor gate, wherein the output ends of the two comparing groups 444 respectively correspond to one not gate, and the input ends of the two not gates are connected to the input ends of the nor gate, so as to make a final determination on the output information of the two comparing groups 444. When it is judged that the operation result is low level, it is determined that the memory cells in the compressed group 44 have defects, and when the operation result is high level, it is determined that the memory cells in the compressed group 44 have no defects.

In an exemplary embodiment, referring to fig. 5b, the detecting circuit further includes a reset circuit 333, the reset circuit 333 is connected between the output terminal of the transistor corresponding to each comparison group 444 and the judgment logic gate of the judging circuit 111, and the reset circuit 333 is used for resetting after each memory detection to facilitate the next detection.

In an exemplary embodiment, the compression circuit 555 further includes a latch (refer to fig. 3b) connected to an even number of input-output pins 700 (refer to fig. 2). The latch caches the data in the storage unit to ensure that other preset data do not participate in the process of reading the target data stored in each storage unit.

In an exemplary embodiment, the detection circuit further comprises a precharge circuit 222, the precharge circuit 222 being coupled to the output of each of the comparison sets 444 and the input of the judgment circuit 111 for precharging the input of the judgment circuit 111 to a high level prior to a read operation. The pre-charge circuit 222 includes a PMOS transistor, in the pre-charge process, the gate terminal of the PMOS transistor is connected to the low level, the PMOS transistor is turned on, and in the read operation process, the gate terminal of the PMOS transistor is connected to the high level, and the PMOS transistor is turned off. When the input terminals of the determining circuit 111 are all at high level during the reading operation, i.e. when each NMOS transistor in the comparing group 444 is turned off, the determining result is at high level after the non-logic and the nor-logic operation of the determining circuit 111, i.e. the memory cell corresponding to the comparing group 444 is error-free. When any one of the NMOS transistors in the comparison set 444 is turned on to make the output result of the comparison set 444 be a low level, the two comparison sets 444 are output as a low level after the non-logic and the non-logic operation of the determination circuit 111, and in this case, it can be determined that the memory cell corresponding to the comparison set 444 is faulty.

Fig. 7 illustrates a memory detection apparatus according to an exemplary embodiment, which includes at least a writing module 210, a control module 220, a reading module 230, and a determining module 240.

A writing module 210 configured to write the test data into at least a portion of the memory cells of the memory;

a control module 220 configured to open a word line connected to the memory cell;

the reading module 230 is configured to take 2N storage units corresponding to an even number of input/output pins as a compression group, and read target data stored in each storage unit in the compression group, where N is a positive integer.

And a judging module 240 configured to determine detection information of the compression group based on a preset processing method and the target data. And is further configured to determine whether the memory cells in the compressed group are defective based on the detection information.

In an exemplary embodiment, the detection apparatus further includes a reset module 250, configured to control the comparison set to perform a reset operation after each compression set completes detection, so as to facilitate multiple and rapid recycling.

In an exemplary embodiment, the detection apparatus further includes a latch for buffering preset data stored in each of the storage units, except for the target data, and the control module 220 is further configured to control the preset data not to participate in the process of reading the target data stored in each of the storage units.

FIG. 8 is a block diagram illustrating an apparatus, namely a computer apparatus 400, for memory detection in accordance with an exemplary embodiment. For example, the computer device 400 may be provided as a terminal device. Referring to fig. 6, the computer device 400 includes a processor 401, and the number of processors may be set to one or more as necessary. The computer device 400 further comprises a memory 402 for storing instructions, such as an application program, executable by the processor 401. The number of the memories can be set to one or more according to requirements. Which may store one or more application programs. The processor 401 is configured to execute instructions to perform the memory detection method described above.

As will be appreciated by one skilled in the art, embodiments of the present disclosure may be provided as a method, apparatus (device), or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied in the medium. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including, but not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer, and the like. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as is well known to those skilled in the art.

In an exemplary embodiment, a non-transitory computer readable storage medium comprising instructions, such as the memory 402 comprising instructions, executable by the processor 401 of the apparatus 400 to perform the above-described method is provided. For example, the non-transitory computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

A non-transitory computer readable storage medium, instructions in the storage medium, when executed by a processor of a memory test device, enable the memory test device to perform the memory detection method in the above embodiments.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional like elements in the article or device comprising the element.

While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A method for testing a memory, the method comprising:

writing test data into at least some memory cells of the memory;

opening a word line connected to the memory cell;

calculating the target data corresponding to the compression group according to a preset processing method, and determining detection information of the compression group;

2. The detection method according to claim 1, wherein the determining the detection information of the compression group by performing an operation on the target data corresponding to the compression group according to a preset processing method comprises:

comparing target data in two storage units corresponding to two different input and output pins according to a first preset method to obtain N pieces of comparison result information; wherein the first preset method comprises an exclusive or logical operation;

3. The detection method according to claim 2, wherein the determining the detection information of the compression group according to the comparison result information comprises:

4. The method of claim 3, wherein the transistor comprises an NMOS transistor.

5. The detection method according to claim 3, wherein said determining detection information of the compression group according to the output information comprises:

and performing NOR logic operation on the output information of the two comparison groups, wherein the operation result is used as the detection information of the compression group.

6. The method according to claim 5, wherein said determining whether the memory cells in the compressed group are defective according to the detection information comprises:

7. The method of claim 3, further comprising:

8. The detection method according to claim 1, further comprising:

9. A memory sense circuit, the memory sense circuit comprising:

the compression circuit comprises a first processing circuit, wherein the first processing circuit is connected to an even number of input and output pins of a memory, the input and output pins correspond to 2N storage units of the memory, the first processing circuit comprises N logic gates, each logic gate is connected to the input and output pins corresponding to two storage units, and N is a positive integer;

the second processing circuit comprises N transistors which are respectively connected to the output ends of N logic gates of the first processing circuit, the N transistors are divided into two comparison groups, and the detection circuit comprises output ends respectively corresponding to the two comparison groups;

10. The memory sensing circuit of claim 9, wherein the decision circuit comprises a decision logic gate coupled to the respective outputs of the two comparison sets.

11. The memory sensing circuit of claim 10, further comprising a reset circuit coupled between the output of the transistor corresponding to each of the comparison sets and the input of the decision logic gate.

12. The memory sensing circuit of claim 9, wherein the compression circuit further comprises a latch, the latch coupled to the even number of input-output pins.

13. The memory sensing circuit of claim 9, further comprising a precharge circuit coupled to the input of the judgment circuit for precharging the input of the judgment circuit to a high level.

14. A memory device, comprising:

15. The apparatus according to claim 14, further comprising a reset module for controlling the comparison set to perform a reset operation after each compression set completes the detection.

16. The memory test apparatus according to claim 14, wherein the test apparatus further comprises a buffer for buffering preset data other than the target data stored in each of the storage units;

the control module is further configured to:

and controlling the preset data not to participate in the process of reading the target data stored in each storage unit.

17. A memory sensing device, the sensing device comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor is configured to perform the method of any one of claims 1 to 8.

18. A computer-readable storage medium, wherein instructions in the storage medium, when executed by a processor, enable the processor to perform the method of any of claims 1 to 8.